JPS624018B2 - - Google Patents
Info
- Publication number
- JPS624018B2 JPS624018B2 JP56034174A JP3417481A JPS624018B2 JP S624018 B2 JPS624018 B2 JP S624018B2 JP 56034174 A JP56034174 A JP 56034174A JP 3417481 A JP3417481 A JP 3417481A JP S624018 B2 JPS624018 B2 JP S624018B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- period
- integrating circuit
- integrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005259 measurement Methods 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Measurement Of Current Or Voltage (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明は平均電流測定変換回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an average current measurement conversion circuit.
例えば時計の電流測定は、出力信号の1周期内
の平均電流を測定するものであるが、時計の種類
によつて出力信号の周期が異なるため、1台の電
流計で全種類の時計の電流測定を行なうことは難
しい。現在使われているのはV―Fコンバータを
用いたもので、そのゲート時間は0.25、0.5、
1.0、2.0秒とそれぞれの10倍の8種類に切換え可
能で、出力信号の周期が上記のいずれかであれば
測定できるが、これ以外のものは測定できない。 For example, when measuring the current of a watch, the average current within one period of the output signal is measured, but since the period of the output signal differs depending on the type of watch, one ammeter can measure the current of all types of watches. It is difficult to make measurements. The one currently in use uses a V-F converter, and its gate time is 0.25, 0.5,
It can be switched to 8 types, 1.0, 2.0 seconds, and 10 times each, and can measure output signal periods if they are any of the above, but cannot measure anything else.
近年、いわゆる擬似振子と呼ばれる、時計とは
無関係に駆動される飾り振子を有した時計が多数
製品化されており、その振子周期にはいろいのな
ものがあり、しかも同一製品でもばらつきがある
ため上記測定器では到底測定できないものであつ
た。 In recent years, many watches with decorative pendulums, so-called pseudopendulums, that are driven independently of the clock have been commercialized, and there are various pendulum periods, and even within the same product, there are variations. Therefore, it was impossible to measure it with the above-mentioned measuring device.
そこで本発明は2重積分型A―D変換回路の基
準電圧を入力信号の周期に応じて自動的に変化さ
せることにより、いかなる周期の入力信号でもそ
の平均値を計測することができるようにしたもの
である。 Therefore, the present invention makes it possible to measure the average value of an input signal of any period by automatically changing the reference voltage of a double integration type A-D conversion circuit according to the period of the input signal. It is something.
以下本発明の一実施例を図面に基づいて説明す
る。第1図において、Aは擬似振子の駆動回路、
OP1〜OP5は演算増幅器で、OP4,OP5はコンパ
レータとして動作する。S1〜S4はアナログスイツ
チで、アナログスイツチS2が制御回路を構成する
ものである。F1〜F3はフリツプフロツプ回路、
Wはワンシヨツトパルス発生器、G1,G2はゲー
ト回路、CTは計数回路である。C1,C2はコンデ
ンサ、R0〜R4は抵抗、Dはツエナーダイオー
ド、Eは電池である。コンデンサC1、抵抗R1お
よび演算増幅器OP2によつて第1の積分回路を構
成し、コンデンサC2、抵抗R2および演算増幅器
OP3によつて第2の積分回路を構成している。 An embodiment of the present invention will be described below based on the drawings. In Fig. 1, A is a pseudo-pendulum drive circuit;
OP1 to OP5 are operational amplifiers, and OP4 and OP5 operate as comparators. S 1 to S 4 are analog switches, and analog switch S 2 constitutes a control circuit. F1 to F3 are flip-flop circuits,
W is a one-shot pulse generator, G 1 and G 2 are gate circuits, and CT is a counting circuit. C 1 and C 2 are capacitors, R 0 to R 4 are resistors, D is a Zener diode, and E is a battery. A first integrating circuit is formed by a capacitor C 1 , a resistor R 1 and an operational amplifier OP 2 , and a capacitor C 2 , a resistor R 2 and an operational amplifier
OP 3 constitutes a second integration circuit.
つぎに動作について説明する。振動回路Aから
生じる周期Tの振動子の駆動電流をiとすると、
演算増幅器OP1の出力e1はe1=iROとなり、この
出力電圧は第2図aのごとく周期Tで発生する。
この出力電圧は第2図bのごとくコンパレータ
OP4で波形整形され、フリツプフロツプ回路F2の
出力が第2図Cのごとく“1”に反転してアナロ
グスイツチS1,S3がオンになる。 Next, the operation will be explained. If the driving current of the vibrator with period T generated from the vibrating circuit A is i,
The output e 1 of the operational amplifier OP 1 becomes e 1 =i RO , and this output voltage is generated with a period T as shown in FIG. 2a.
This output voltage is determined by a comparator as shown in Figure 2b.
The waveform is shaped by OP 4 , and the output of flip-flop circuit F 2 is inverted to "1" as shown in FIG. 2C, and analog switches S 1 and S 3 are turned on.
したがつて、第1の積分回路は端子aからの出
力電圧を積分してその出力に第2図eの電圧が生
じ、第2の積分回路はツエナーダイオードDおよ
び抵抗R4によつて設定された基準電圧ESを積分
し、その出力に第2図hの電圧が生じる。 Therefore, the first integrator circuit integrates the output voltage from terminal a, resulting in the voltage shown in FIG . The reference voltage ES obtained is integrated, and the voltage shown in Fig. 2h is generated at its output.
そこで、第1の積分回路の1周期T後における
電圧e0についてみると、
e0=1/R1C1∫T 0e1 dt=−R0/R1C1∫T 0idt
で表わされる。但し、演算増幅器OP1,OP2のバ
イアス電流およびオフセツト電圧は0と仮定す
る。 Therefore, looking at the voltage e 0 after one period T of the first integrating circuit, it is expressed as e 0 = 1/R 1 C 1 ∫ T 0 e 1 dt = −R 0 /R 1 C 1 ∫ T 0 idt It can be done. However, it is assumed that the bias current and offset voltage of operational amplifiers OP 1 and OP 2 are zero.
一方、第2の積分回路の1周期T後における出
力電圧e′0は、e′0=−1/R2C2∫T 0es dt
で表わされる。基準電圧esは一定であるので、
e′0=−Tes/R2C2 ……(1)
で表わされる。 On the other hand, the output voltage e' 0 of the second integrating circuit after one period T is expressed as e' 0 =-1/R 2 C 2 ∫ T 0 es dt. Since the reference voltage es is constant, it is expressed as e′ 0 =−Tes/R 2 C 2 (1).
そして、1周期Tが終わるとフリツプフロツプ
回路F3の出力が“0”に反転し、ゲート回路
G1の出力によつてフリツプフロツプ回路F1,F2
がリセツトされ、アナログスイツチS1,S3が閉じ
る。一方、フリツプフロツプ回路F3の出力Qが
第2図dのごとく“1”に反転するためアナログ
スイツチS2がオンになる。そのため、第2の積分
回路の出力電圧e′0によつて第1の積分回路が上
記とは逆方向に積分され、その出力電圧e0が0V
になるまでの時間をtとすると、
−1/R1C1∫t 0e′0 dt−R0/R1C1∫T 0idt=0
となり、上記式(1)を代入すると、
t/R1C1・Tes/R2C2−R0/R1C1∫T 0idt=0
tT/R2C2・es=R0∫T 0idt……(2)
となる。 Then, when one period T ends, the output of the flip-flop circuit F3 is inverted to "0", and the gate circuit
Flip-flop circuits F 1 , F 2 by the output of G 1
is reset and analog switches S 1 and S 3 are closed. On the other hand, since the output Q of the flip-flop circuit F3 is inverted to "1" as shown in FIG. 2d, the analog switch S2 is turned on. Therefore, the output voltage e′ 0 of the second integration circuit integrates the first integration circuit in the opposite direction to the above, and the output voltage e 0 becomes 0V.
If the time taken for _ _ _ _ _ /R 1 C 1・Tes/R 2 C 2 −R 0 /R 1 C 1 ∫ T 0 idt=0 tT/R 2 C 2・es=R 0 ∫ T 0 idt...(2).
いま、本例で求める平均電流は
=1/T∫T 0idt
で表わされるので、上記式(2)より、
=1/T∫T 0idt=es/R0R2C2・t
で表わされる。この式中、R0、R2、C2、esは定
数なので、時間tを以下のように測定することに
よつて、1周期T内での平均電流が求められる。 Now, the average current found in this example is expressed as = 1/T∫ T 0 idt, so from the above formula (2), it is expressed as = 1/T∫ T 0 idt=es/R 0 R 2 C 2・t. It can be done. In this equation, since R 0 , R 2 , C 2 , and es are constants, the average current within one period T can be determined by measuring time t as follows.
第1の積分回路の出力電圧が0Vになると演算
増幅器OP5の出力が第2図fのごとく“0”に反
転してワンシヨツトパルス発生器Wがトリガさ
れ、その出力Qから第2図gのごとく1パルスが
生じる。その立上りによつてフリツプフロツプ回
路F3がリセツトされる。したがつて、フリツプ
フロツプ回路F3の出力Qからは、第2図dのご
とく上記時間tを幅とするパルスが生じ、これに
よつてゲート回路G2が開く。ゲート回路G2の端
子Pにクロツクパルスを供給しておくことによ
り、計数回路CTによつて時間tが計数される。 When the output voltage of the first integrating circuit becomes 0V, the output of the operational amplifier OP5 is inverted to "0" as shown in Fig. 2f, and the one-shot pulse generator W is triggered, and its output Q is changed to Fig. 2g. One pulse is generated as shown below. The flip-flop circuit F3 is reset by this rising edge. Therefore, from the output Q of the flip-flop circuit F3 , a pulse having a width equal to the above-mentioned time t is generated as shown in FIG. 2d, thereby opening the gate circuit G2 . By supplying a clock pulse to the terminal P of the gate circuit G2 , the time t is counted by the counting circuit CT.
なお本発明は上記の実施例に限定されるもので
はなく、周期的な平均電圧測定等種々のものに適
用できる。 Note that the present invention is not limited to the above-mentioned embodiments, but can be applied to various methods such as periodic average voltage measurement.
以上のように本発明によれば、任意の周期の入
力信号の平均値を正確に計測できる。したがつ
て、例えば時計の擬似振子の駆動平均電流を測定
する場合など、入力信号の周期にばらつきがある
場合に特に有効である。 As described above, according to the present invention, the average value of an input signal of any period can be accurately measured. Therefore, it is particularly effective when there are variations in the period of the input signal, such as when measuring the average driving current of a pseudopendulum of a watch.
第1図は本発明の一実施例を示した電気回路
図、第2図は動作説明のための電圧波形図であ
る。
OP2,OP3…演算増幅器、C1,C2…コンデン
サ、R1,R2…抵抗、CT…計数回路、S2…制御回
路。
FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is a voltage waveform diagram for explaining the operation. OP 2 , OP 3 ... operational amplifier, C 1 , C 2 ... capacitor, R 1 , R 2 ... resistor, CT ... counting circuit, S 2 ... control circuit.
Claims (1)
第1の積分回路と、上記1周期の間基準信号を積
分する第2の積分回路と、上記積分動作の終了後
に第2の積分回路の出力を第1の積分回路で逆方
向に積分せしめる制御回路と、第1の積分回路に
よる第2の積分回路の出力の積分開始から第1の
積分回路の出力が初期値に達するまでの時間を計
数する計数回路とからなる平均電流測定回路。1. A first integrating circuit that integrates a periodic input signal for one period, a second integrating circuit that integrates a reference signal for one period, and a second integrating circuit that integrates a periodic input signal for one period. A control circuit that integrates the output in the opposite direction with a first integrating circuit, and a time period from when the first integrating circuit starts integrating the output of the second integrating circuit until the output of the first integrating circuit reaches the initial value. An average current measurement circuit consisting of a counting circuit that performs counting.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3417481A JPS57148423A (en) | 1981-03-10 | 1981-03-10 | A-d converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3417481A JPS57148423A (en) | 1981-03-10 | 1981-03-10 | A-d converting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57148423A JPS57148423A (en) | 1982-09-13 |
JPS624018B2 true JPS624018B2 (en) | 1987-01-28 |
Family
ID=12406835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3417481A Granted JPS57148423A (en) | 1981-03-10 | 1981-03-10 | A-d converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57148423A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0625150Y2 (en) * | 1988-12-23 | 1994-07-06 | 松下電工株式会社 | The lower structure of the bag |
-
1981
- 1981-03-10 JP JP3417481A patent/JPS57148423A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0625150Y2 (en) * | 1988-12-23 | 1994-07-06 | 松下電工株式会社 | The lower structure of the bag |
Also Published As
Publication number | Publication date |
---|---|
JPS57148423A (en) | 1982-09-13 |
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