JPS624016B2 - - Google Patents
Info
- Publication number
- JPS624016B2 JPS624016B2 JP9689780A JP9689780A JPS624016B2 JP S624016 B2 JPS624016 B2 JP S624016B2 JP 9689780 A JP9689780 A JP 9689780A JP 9689780 A JP9689780 A JP 9689780A JP S624016 B2 JPS624016 B2 JP S624016B2
- Authority
- JP
- Japan
- Prior art keywords
- tuning
- diode switch
- circuit
- vco
- control voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/02—Details
- H03J3/16—Tuning without displacement of reactive element, e.g. by varying permeability
- H03J3/18—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance
- H03J3/185—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance with varactors, i.e. voltage variable reactive diodes
Landscapes
- Superheterodyne Receivers (AREA)
Description
【発明の詳細な説明】
本発明は、受信機の高周波増巾段に用いられる
VCOを備えた同調回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a high frequency amplification stage of a receiver.
It concerns a tuned circuit with a VCO.
ある程度の受信帯域を有するセツトにおいて、
第１図のような固定非同調式の同調回路が用いら
れている。同図において１は増巾用トランジス
タ、２は同調回路である。しかしこの非同調式に
おいては、第２図のように帯域の両端で感度差が
出やすい欠点があり、これを解決しようとして同
調回路の選択度を広くとると、逆にスプリアス妨
害等が悪化する欠点が生じる。 In a set that has a certain amount of reception band,
A fixed non-tuned tuning circuit as shown in FIG. 1 is used. In the figure, 1 is an amplifying transistor, and 2 is a tuning circuit. However, this non-tuned system has the disadvantage that sensitivity differences tend to occur at both ends of the band, as shown in Figure 2, and if the selectivity of the tuned circuit is widened in an attempt to solve this problem, spurious interference etc. will worsen. There are drawbacks.
本発明は以上の欠点を除去するためなされたも
ので、可変方式の同調回路を提供するものであ
る。以下図面を参照して本発明実施例を説明す
る。第３図は本発明実施例による同調回路を示
し、１は増巾用トランジスタ、２は同調回路、３
は同調容量、４はこれに直列に接続されたダイオ
ードスイツチ、５は電圧制御型発振器（以下
VCOと称する）、６はPLL回路等からの制御電圧
ＶDの入力端子、７はコンパレーター、８は基準
電圧設定用抵抗である。 The present invention has been made to eliminate the above-mentioned drawbacks, and provides a variable tuning circuit. Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a tuning circuit according to an embodiment of the present invention, where 1 is an amplifying transistor, 2 is a tuning circuit, and 3 is a tuning circuit according to an embodiment of the present invention.
is a tuning capacitor, 4 is a diode switch connected in series with this, and 5 is a voltage controlled oscillator (hereinafter referred to as
(referred to as VCO), 6 is an input terminal for a control voltage V D from a PLL circuit, etc., 7 is a comparator, and 8 is a reference voltage setting resistor.
以上の構成において、VCO５の発振周波数を
高くするためには上記制御電圧ＶDを高くしてい
き、予め設定された値より高い制御電圧ＶDが入
力端子６に加わるとコンパレーター７の出力がＬ
レベルとなり、同調回路２に並列に接続されてい
るダイオードスイツチ４がオフとなる。この結果
同量容量３は同調回路２に付加されなくなり、第
４図のように、同調周波数波形はダイオードスイ
ツチのオフ前のからへと高い周波数側へ移動
し同調が行われる。 In the above configuration, in order to increase the oscillation frequency of the VCO 5, the control voltage V D is increased, and when a control voltage V D higher than a preset value is applied to the input terminal 6, the output of the comparator 7 increases. L
level, and the diode switch 4 connected in parallel to the tuned circuit 2 is turned off. As a result, the same amount capacitance 3 is no longer added to the tuning circuit 2, and as shown in FIG. 4, the tuning frequency waveform moves to a higher frequency side from before the diode switch is turned off, and tuning is performed.
これにより受信感度差Ｄが改善されることにな
る。は高周波増巾段における選択度を示してい
る。 This improves the reception sensitivity difference D. indicates the selectivity in the high frequency amplification stage.
また上記より感度差が全帯域でなくスプリアス
妨害もとれるような選択度をとる事も可能とな
る。 Further, from the above, it is also possible to obtain a selectivity such that the sensitivity difference does not cover the entire band but also eliminates spurious interference.
以上の本発明によれば、同調回路はバリキヤツ
プ等によりリニアに可変同調するのではなく予め
設定した幅でのみ変化させるものであり回路構成
を簡単にすることができる。 According to the present invention as described above, the tuning circuit does not perform variable tuning linearly using a varicap or the like, but only changes the tuning within a preset width, thereby simplifying the circuit configuration.
バリキヤツプ等を使用した場合は、過大入力時
整流作用を起こして周波数ずれを発生させること
があるが本発明ではそのような心配はない。 If a varicap or the like is used, a rectification effect may occur when an excessive input is applied, causing a frequency shift, but there is no such concern with the present invention.
また選択度を上げた状態でも受信帯域内での感
度差を少なくすることができ、良好な同調作用を
行うことができる。 Further, even when the selectivity is increased, the difference in sensitivity within the reception band can be reduced, and a good tuning effect can be achieved.
第１図および第２図は従来例を示す回路図およ
び特性図、第３図および第４図は本発明実施例を
示す回路図および特性図である。
２…同調回路、３…同調容量、４…ダイオード
スイツチ、５…VCO、６…入力端子、７…コン
パレーター、８…基準電圧設定用抵抗。
FIGS. 1 and 2 are circuit diagrams and characteristic diagrams showing a conventional example, and FIGS. 3 and 4 are circuit diagrams and characteristic diagrams showing an embodiment of the present invention. 2... Tuning circuit, 3... Tuning capacitor, 4... Diode switch, 5... VCO, 6... Input terminal, 7... Comparator, 8... Reference voltage setting resistor.
Claims (1)
オードスイツチから成る直列回路と、上記ダイオ
ードスイツチに接続されたVCO制御電圧源とを
含み、予め設定された値より高い制御電圧が上記
ダイオードスイツチに加えられた時ダイオードス
イツチがオフして同調が行われるように構成した
ことを特徴とするVCOを備えた同調回路。 ２ 上記VCO制御電圧がコンパレーターを介し
て上記ダイオードスイツチに加えられるように構
成したことを特徴とする特許請求の範囲第１項記
載のVCOを備えた同調回路。[Claims] 1. A series circuit consisting of a tuning capacitor and a diode switch provided in parallel with a tuning circuit, and a VCO control voltage source connected to the diode switch, the control voltage being higher than a preset value. 1. A tuning circuit equipped with a VCO, characterized in that when the diode switch is applied to the diode switch, the diode switch is turned off and tuning is performed. 2. A tuning circuit equipped with a VCO according to claim 1, characterized in that the VCO control voltage is applied to the diode switch via a comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9689780A JPS5723334A (en) | 1980-07-17 | 1980-07-17 | Tuning circuit equipped with vco |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9689780A JPS5723334A (en) | 1980-07-17 | 1980-07-17 | Tuning circuit equipped with vco |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5723334A JPS5723334A (en) | 1982-02-06 |
| JPS624016B2 true JPS624016B2 (en) | 1987-01-28 |
Family
ID=14177159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9689780A Granted JPS5723334A (en) | 1980-07-17 | 1980-07-17 | Tuning circuit equipped with vco |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5723334A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0261853A (en) * | 1988-08-26 | 1990-03-01 | Toshiba Corp | Tape recorder device |
| US5369536A (en) * | 1991-04-17 | 1994-11-29 | Matsushita Electric Industrial Co., Ltd. | Magnetic recording reproducing apparatus with stoppers for loading boats |
-
1980
- 1980-07-17 JP JP9689780A patent/JPS5723334A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5723334A (en) | 1982-02-06 |
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