JPS6239915A - Phase locked type closed loop logic circuit - Google Patents

Abstract

PURPOSE:To attain logic LSI and small size and low cost by digitizing an input signal so as to obtain a difference with an output digital phase thereby replacing a phase locked circuit by a logic circuit. CONSTITUTION:A counter circuit 8 counts a basic clock A to generate a basic period B. A counter circuit 9 uses the basic clock A to count the period of an input signal U and the result U(Ti) of the count is outputted in the timing of the basic period B. Then a subtraction circuit 10 calculates the difference E(Ti) between the digital phase U(Ti) and the output side digital phase Y(Ti) and sends the error phase difference E(Ti) to a register circuit 12 and an arithmetic circuit 18. Then the E(Ti) sent at each basic period B is stored in a way of shift in register circuits 12-14. On the other hand, the Y(Ti) outputted from the arithmetic circuit 18 is stored in register circuits 15-17 in the similar timing. A counter circuit 19 uses the basic clock A to shift the basic period B by the digital phase Y(Ti) to form a VCO output Y.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a phase-locked closed-loop logic circuit, and particularly to a phase-locked closed-loop logic circuit suitable for converting a phase-locked circuit of a magnetic recording device into a logic LSI to make it compact and inexpensive. It relates to a synchronous closed loop logic circuit.

[Background of the invention]

As shown in FIG. 2, a conventional phase synchronization circuit includes a phase difference detection circuit 1 that detects a phase difference between an input signal U and a vCO output Y, and a phase difference current conversion circuit that converts the detected phase difference into a current. 2, a filter circuit 3 that low-pass filters the current, and a voltage controlled oscillator (VCO) that delivers the vCO output Y.
4 are arranged in a closed loop. However, the phase difference current conversion circuit 2. Filter circuit 3. Since the voltage controlled oscillator (VCo) 4 is generally constructed from an analog circuit, it requires adjustment points and increases the number of parts to ensure accuracy and performance, resulting in high costs.

In order to solve these problems, there is a method of configuring the phase locked circuit with a digital circuit.

Japanese Patent Application Laid-Open No. 53-639 was used to digitize phase-locked circuits.
As described in Publication No. 60, there is a method of realizing the function of the filter circuit 3 using a random access memory, but it is possible to implement the function of the filter circuit 3 using a single memory circuit (register) for storing the output phase Y of digitization. Therefore, it has been difficult to realize a complex (high-order transfer function) filter circuit 3.

[Purpose of the invention]

An object of the present invention is to solve such conventional problems, and to replace the phase-locked circuit with a logic circuit using a simple and inexpensive method, to create a logic LSI, and to realize a small and inexpensive phase-locked circuit. An object of the present invention is to provide a phase-locked closed loop logic circuit.

[Summary of the invention]

In order to achieve the above object, the phase-locked closed-loop logic circuit of the present invention uses a means (counter circuit) for digitizing the input signal U in a phase-locked circuit that generates a signal synchronized with an input analog signal. 9) and
Means for calculating the difference E (Ti) between the digitization amount U (Ti) and the digitization output phase Y (T i ) (subtraction port i1!10), the calculated difference E (Ti) and the output Means for storing a plurality of contents of phase Y(Ti) (
register circuits 12 to 17), means for calculating the digitized output phase Y(Ti) based on the stored contents of the storage means, and the calculated digitized output phase Y(Ti).
to the synchronized signal Y (counter circuit 1
9).

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

First, the principle of the present invention will be described with reference to FIGS. 3 and 4.

The above-mentioned FIG. 2 can be represented as shown in FIG. That is, the conventional phase synchronization circuit includes a functional unit 5 that takes the phase difference between the input signal U and the VC○ output Y, and the phase difference is sampled every period To to obtain the difference E(Ti).
It can be expressed as a circuit with a closed loop configuration including a functional section 6 (sampling circuit) that obtains a signal, and a functional section 7 that low-pass filters the current and sends out a vCO output Y. In addition, the functional section 7
is resistance R1s R2 and capacitor〇 1 p C
It consists of a filter and a voltage frequency conversion circuit. Moreover, To is a sampling period.

Figure 3 is the symbol (U, E, Y) in Figure 2 and the transfer function F.
Expressed in the formula, Y(s)=F(s)・U(s)/(1+F(s))...
...(1), and if this is replaced with a sampling circuit, Y(z)=F(z)・U(z)/(1+F(z)
)---(2).

Next, as shown in FIG. 4, E(Ti) is the phase difference between Y(Ti) and U(Ti). In other words, in equation (2), E
Substituting (z) = U (z) - Y (z), we get Y(z) = F(z)・E(z) ”(3
).

Since the denominator of F(z) is usually larger than the numerator,
Y (z), that is, vCO output Y, in the past E(
phase difference) and y (v co output). In addition, in this example described below,
The sampling period is the same To, the digital phase of the input signal U is U(Ti), the digital phase of the vC○ output Y is Y(Tt), and the difference between these U(Ti), -4- and Y(Ti). is expressed as E(Ti).

Next, the digitization of the phase locked circuit according to the present invention will be described with reference to FIGS. 1 and 4.

FIG. 1 is a block diagram of a phase-locked closed loop logic circuit showing an embodiment of the present invention, and FIG. 5 is an operation time chart of FIG. 1.

In FIG. 1, 8 is a counter circuit that divides the basic clock A into a basic period B, 9 is a counter circuit that digitizes the input signal U, and 10 is the digital phase U of the input signal U.
(Ti) and the difference E between the digital phase Y(Ti) of the output Y
(Ti), and 11 is a filter circuit, which is composed of register circuits 12 to 14 and 15 to 17 that store E (Ti) and Y (Ti), and an arithmetic circuit 18 that calculates Y (Ti). Become. 19 is Y(Ti) vCO
This is a counter circuit that converts to output Y.

In the circuit of this configuration, the counter circuit 8 uses the basic clock A
is counted to generate a fundamental period B as shown in FIG. Note that the generation is performed so that the basic period B is equal to the period of the input signal U that does not cause speed fluctuations, and this period is set as the sampling period To, and is used as the timing of calculation in each block.

The counter circuit 9 converts the period of the input signal U to the basic clock A.
The counting result U(Ti) is outputted at the timing of the fundamental period B as shown in FIG.

That is, if the number of U and the number of A in one period To are the same, U(Ti) is zero, and the number of differences is U(Ti).

Next, the subtraction circuit IO calculates the difference E (Ti) between the digital phase U (Ti) that is the above result and the digital phase Y (T1) on the output side, and stores the error phase difference E (Ti) in the register. The signal is sent to the circuit 12 and the arithmetic circuit 18. Therefore, in the register circuits 12 to 14, E(Ti) sent out every basic cycle B (sampling cycle To) is stored in a shifted manner. That is, register circuit 14, 1.3
．． 12 are the past E(T i +2L E(T
i-ILE(Ti) is stored and its contents are output to the arithmetic circuit 18.

On the other hand, the register circuits 15 to 17 store Y(Ti) output from the arithmetic circuit 18 at the same timing as above.

In other words, the register circuits 17, 16° 15 respectively record the past Y(T i -2), Y(T i -1), Y(
Ti) and outputs its contents to the arithmetic circuit 18.

The counter circuit 19 performs the opposite operation to the counter circuit 9, shifts the basic period B by the digital phase Y (Ti), and outputs vCoCo. For example, Y(
When there are several Ti), Y is obtained by adding (or subtracting) the number of Ti to To.

FIG. 5 shows that the input signal U is (To
12) and a triangular pattern with an amplitude of ±6. This case will be described.

At this time, the digital phase U(Ti) of the input signal U changes as shown in the figure for each sampling period To, so the difference E( Ti)=U(T1)-Y(T
i) changes as shown.

Furthermore, Y(Ti) as shown in the figure can be generated by calculating based on the past three times of E(Ti) and Y(Ti).

Regarding the calculation contents executed by the calculation circuit 18, the output digital phase Y (Ti) is determined by the transfer function of the filter circuit 11 as follows: Y (Ti) = ΣaJE (Ti J) + ΣbJyffi
Since it can be expressed as aL(4), the arithmetic circuit 18 first calculates the first term on the right side of equation (4) using E(Tl) e from the register circuits 12 to 14.
E(Tl -1) + E(Tl -2), and then the second term on the right side of equation (4) is calculated using Y(Ti) and Y(Ti-i) from the register circuits 15 to 17.
)*Y(Tl −2), and the two calculation results are added to obtain Y(Ti).

Also, aJ and )IJ in equation (4) can be expressed as 1, -8- after Z-transforming the transfer function of filter circuit 3 in Fig. 1, and from equation (4) and equation (6), aJtb
can be obtained corresponding to J. However, an”bn=o, n≧3
It is.

In this way, counter circuits, subtraction circuits, register circuits,
Since it is possible to replace all the phase synchronized circuits with logic circuits in the arithmetic circuit, it becomes possible to implement a logic LSI, and it is possible to realize a circuit similar to the conventional analog circuit at a lower cost than a configuration using a conventional analog circuit. Furthermore, by digitizing the filter circuit section, various changes can be easily made.

Furthermore, the register circuits 12 to 17 are expanded and the arithmetic circuit 18
A desired input/output function can be realized by deepening the logic.

〔Effect of the invention〕

As explained above, according to the present invention, the input signal U is digitized, the difference E(Tj,) from the output digital phase Y(T1) is obtained, and the difference E(Tj) and Y(Ti) are obtained.
Since Y(Tj) is generated by calculating Y(Tj) and its past part, it is possible to convert the phase locked circuit into a logic circuit, and at the same time, the logic r.

A small and inexpensive phase-locked circuit can be realized by SI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase-locked closed loop logic circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional phase-locked circuit, and FIGS. 3 and 4 are detailed explanations of the present invention. FIG. 5 is an operation time chart of FIG. 1. Phase difference projection circuit, 2: Phase difference current conversion circuit, 3.11
: Filter circuit, 4: Voltage controlled oscillator (VCO), 5~
7: functional section, 8, 9, 19: counter circuit, 10: subtraction circuit, 12 to 17: register circuit, 18: arithmetic circuit.

Claims (1)

[Claims] (1) In a phase locked circuit that generates a signal synchronized with an input signal, means for digitizing the input signal;
means for calculating the difference between the digitization amount and the digitization output phase; means for storing a plurality of contents of the calculated difference and output phase; A phase synchronized closed loop logic circuit comprising means for calculating an output phase and means for converting the calculated digitized output phase into the synchronized signal.