JPS6239882B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an orientation detection device that detects the direction of earth's magnetic field using a stationary sensor and obtains a digital signal.

FIG. 1 is a block diagram of a device devised for obtaining the azimuth from the earth's magnetic field detected by a flux gate magnetometer as a digital signal.
In the figure, Se ₁ 1 is an X-axis sensor that detects a magnetic field in the X direction, and Se ₂ 1' is a Y-axis sensor that detects a magnetic field in the Y direction, which are arranged orthogonally to each other. Each sensor Se ₁
The detection signals of 1 and Se ₂ 1' are respectively connected to orthogonal converters MOD ₁ 2 and MOD ₂ in order to stably amplify the minute signals.
2' converts the DC signal into an AC signal, which is amplified to a predetermined level by bandpass amplifiers AMP ₁ 3 and AMP ₂ 3'. Then, a synchronous rectifier circuit DEMO ₁ 4, DEMO ₂ reproduces the magnitude and polarity of the signal from this amplified output.
4' to obtain direct current again. This rectified output is then digitally converted by an analog-to-digital converter A/D7 via buffer amplifiers B.AMP ₁ 5 and B.AMP ₂ 5' and is applied to an arithmetic circuit ARITH8. The arithmetic circuit ARITH8 uses the following equation (1) to obtain the angle θ of the earth's magnetic field from the magnetic north, that is, tanθ of the azimuth, and further
Obtain the angle θ using equation (2).

_Y ^÷ _{_} Even if the output of ' is obtained by direct analog calculation and the result of this calculation is converted into digital, the same result will be obtained.

However, in such a device, the arithmetic circuit,
It has the disadvantage of requiring complicated and expensive parts such as an A/D converter.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an azimuth detection device that can digitally obtain an azimuth signal with a simple configuration and is inexpensive.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. In Figure 2, 1
1 is a clock oscillator, 12 is a clock oscillator 11
is an 8-bit counter whose output is applied to the count input Cu. Reference numeral 13 denotes an 8-bit latch that holds the count value of the 8-bit counter 12 in response to a strobe signal applied to the strobe input. 14 is a T-type flip-flop that inverts its output with the carry signal given from the carry output CA of the 8-bit counter 12; 15 is a D-type flip-flop; the output Q ₉ of the T-type flip-flop 14;
is applied to the D input, and the output Q7 of bit 7 of the 8-bit counter 12 is applied to the clock input CK. And the output Q ₉ of the T-type flip-flop 14
The output Q of the D-type flip-flop 15 is inverted by inverters 16 and 17, respectively, and applied to flux gate driving power amplifiers 18 and 19. Reference numerals 20 and 21 indicate flux gate sensors arranged orthogonally to which the outputs of the power amplifiers 18 and 19 are applied. The outputs of the flux gate sensors 20 and 21 are added to an adder and a phase corrector 22.
The bandpass amplifier 2 performs phase correction by adding
3 and provides it to the voltage comparator 24. The output of this voltage comparator 24 is applied to the clock input CK of a D-type flip-flop 25. The output Q of this D-type flip-flop 25 is applied to the D input of a D-type flip-flop 26. Also, the output of the clock oscillator 11 is applied to the clock input CK of this D-type flip-flop 26 via the inverter 32, and the output Q is applied to the strobe input of the 8-bit latch 13.
Give it to STB, output to resistor 27, capacitor 2
It is applied to one input of the NAND gate 29 via a delay circuit consisting of 8. On the other hand, the signal given to the inhibit terminal 31 of the strobe is transferred to the inverter 30.
to the other input of the NAND gate 29 via
This output is applied to the reset terminals of D-type flip-flops 25 and 26. Further, the signal applied to the inhibit terminal 31 is applied to the output disable input DS of the 8-bit latch 13.

With this configuration, the output of the clock oscillator 11 is synchronized with the rising edge of the 8-bit counter 1.
The frequency is divided by 2 to 1/256, and the frequency is further divided to 1/2 by the T-type flip-flop 14 and input to the power amplifier 18 via the inverter 16, and the flux gate drive power supply eb _x (Fig. 3a) is obtain. Similarly, from the power amplifier 19, with the same period as the drive power supply eb _x and 45
A drive power source e _y (FIG. 3b) having a phase difference of .degree. can be obtained. On the other hand, flux gate sensor 2
0 and 21 are arranged orthogonally to each other, and the x component ex (Fig. 3 c) and the y component ey (Fig. 3 d) of the magnetic field
Detect. These sensors 20 and 21 are driven by the drive power supplies eb x and eb y, and the sensor output is proportional to the x and y components of the magnetic field, has a frequency 2fc that is twice the driving frequency fc, and has an x component ex. The signal has a phase difference of 90° from the y component ey.
Then, the adder and phase corrector 22 combine the components ex and ey into vectors, and the bandpass amplifier 23 amplifies only the frequency 2fc, that is, the second harmonic component. Note that each component is used instead of the adder above.
The outputs of ex and ey may be connected in series. Then, the flux gate sensor 2 is adjusted by the phase corrector 22.
The resistance of the drive coils 0 and 21 and the phase shift caused by the bandpass amplifier 23 are corrected. Note that this correction may be performed digitally after setting the data in the 8-bit latch 13. The amplitude of the composite signal ex y (Fig. 3e) output from the amplifier 23 represents the magnitude of the magnetic field, and the distance from the rising point of the drive power supply eb _x to the zero cross point of the composite signal exy is the magnetic north. It becomes the deviation angle from .

Note that Fig. 4 a, b, and c show the components ex and y for the flux gate drive power supply eb _x with the X-axis sensor facing north, east, south, and west, respectively.
FIG. 3 is a waveform diagram showing changes in component ey and composite signal exy. Therefore, the zero-crossing point of this composite signal exy is detected by the comparator 24 in FIG. Therefore, the Q output of the D-type flip-flop 25 becomes "H" level due to the above detection output, and this output is applied to the D terminal of the D-type flip-flop 26. On the other hand, the D type flip-flop 26 is CK
The output of the clock oscillator 11 is connected to the terminal of the inverter 3.
Since it is inverted and given by the resistor 2, it goes to the "H" level in response to the "H" output of the D-type flip-flop 25 and in synchronization with the falling edge of the clock.
7. Apply the strobe signal determined by the delay circuit consisting of the capacitor 28 to the STB terminal of the 8-bit latch 13. Therefore, the 8-bit latch 13 stores the contents of the counter 12 by means of this strobe signal. Also, at this time, the D-type flip-flop 26
The output changes from the "H" level to the "L" level, and one input of the NAND gate 29 is brought to the "L" level via a delay circuit consisting of a resistor 27 and a capacitor 28. Therefore, the output of the NAND gate 29 becomes "H" level, and this signal is applied to the R terminals of the D-type flip-flops 25 and 26 to reset them.
By applying an "H" level signal to the INT terminal 31, the transfer from the counter 12 is temporarily stopped when the stored contents are read from the _Q1 to _Q8 terminals of the 8-bit latch 13.

Therefore, an 8-bit digital signal corresponding to the orientation of the flux gate sensors 20 and 21 is obtained from the Q ₁ to _{Q 8} terminals of the 8-bit latch 13, which is particularly convenient when arithmetic processing is performed on this digital signal using a digital computer or the like. It is.

As described in detail above, the present invention counts the output of the clock oscillator with a digital counter to determine the phase.
Obtain a flux gate drive power source shifted by 45 degrees, apply it to a pair of flux gate sensors arranged orthogonally, add the detection outputs of the flux gate sensors, extract the second harmonic component, and calculate at this zero cross point. The count value of the counter is latched to obtain the detected direction as a digital value. Therefore, the overall configuration is simple and no special arithmetic equipment is required.
In addition, since the outputs of the flux gate sensors are added together, it is possible to provide an azimuth detection device that produces no phase error and is less expensive than a device that uses a special amplifier.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a direction detection device using a conventional flux gate sensor, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 explains the operation of the above embodiment. FIGS. 4A, 4B, 4D, and 4D show the relationship between the position of the flux gate sensor and the detection signal. 11...Clock oscillator, 12...Counter,
13... Latch, 20, 21... Flux gate sensor, 22... Adder and phase corrector, 2
3... Bandpass amplifier, 24... Comparator, 2
5, 26...flip flop.

Claims (1)

[Claims] 1. A digital counter that obtains a flux gate drive power supply that divides the output of a clock oscillator and outputs a square wave with a 45° phase difference, and a pair of flux gate drive power supplies that are arranged orthogonally and driven by the flux gate drive power supply. a flux gate sensor, a converter for adding the detected outputs of the pair of flux gate sensors having a phase difference of 90 degrees, a bandpass amplifier for amplifying the second harmonic component of the summed output of the adder; a comparator that detects the zero-crossing point of the output of the bandpass amplifier; a flip-flop that obtains a strobe signal from the comparison output of the comparator in synchronization with the output of the clock oscillator; An azimuth detection device comprising a latch that stores the stored contents using a strobe signal and outputs the stored contents as a digital value of a detected azimuth.