JPS623909B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <<Field of the Invention>> This invention relates to an improvement in an ultrasonic level meter that emits a switch output at an upper limit, a lower limit, etc.

≪Prior art and its problems≫ Fig. 1 is a block diagram showing a conventional circuit of an ultrasonic level meter with switch output, and Fig. 2 is a diagram showing waveforms of each part labeled a to h in Fig. 1. be.

To explain the operation of the circuit shown in FIG. 1, as shown in FIG. RS flip-flop 2 is set.

Further, the reference pulse is converted into a high frequency pulse through a modulation circuit 3, an oscillation circuit 4 and an amplifier circuit 5,
Ultrasonic pulses are emitted via the wave transmitter 6 toward the bottom of the tank where the contents to be measured are stored.

After the reflected wave is detected via the receiver 7, it is amplified via the amplifier circuit 8 as shown in FIG. The received pulse is shaped into a pulse, and the RS flip-flop 2 is reset by this received pulse.

As is well known, the time between the sending of the reference pulse and the detection of the received pulse corresponds to the reservoir level of the tank contents. Therefore, a rectangular wave having a time width corresponding to the content level at that time is outputted every period to the Q output side of the RS flip-flop 2, as shown in FIG. 2Q.

Then, this rectangular wave is converted into a sawtooth wave having a predetermined slope as shown in FIG. , a movable pointer type meter or a light emitting diode type level indicator circuit.

Here, the output of the smoothing circuit 11 has a characteristic that it rises almost following the peak value of the input voltage and falls slowly with a certain time constant. When a value is reached, the output remains high for a relatively long period of time, causing a large error in meters and the like.

On the other hand, 13 is a first monomulti, which receives the reference pulse and outputs a rectangular wave with a predetermined time width (hereinafter referred to as upper limit gate pulse) as shown in FIG. 2e;
Reference numeral 14 denotes a second monomultiplier that similarly outputs an "L" rectangular wave with a predetermined time width (hereinafter referred to as a lower limit gate pulse);
The lower limit gate pulse outputted from the inverter 15 is inverted to an "H" pulse as shown in FIG. 2g.

The first and second NAND gates 16 and 17 receive the upper limit gate pulse and the lower limit gate pulse, respectively, and time-discriminate the received pulses, and detect whether the received pulses are in an area exceeding a preset upper limit level or in an area below the lower limit level. If a received pulse exists in the corresponding receiving time range, the received pulse is passed as shown in FIG. 2 f or h.

Next, the first and second NAND gates 16 and 17
The received pulses that have passed through the inverters 16a and 16b (see FIG. 2 f and h) are the second and second pulses, respectively.
The signal is integrated and smoothed via the third integration circuit 18, 19, and further integrated and smoothed by the first and second Schmitt circuits 20, 21.
The signal is waveform-shaped into a logic level signal through a transistor, and its output drives a relay through a transistor (not shown), and an upper limit signal and a lower limit signal are output, respectively.

By the way, in the case of the conventional circuit explained above, if an air current is generated in the storage tank and the reflected wave is interrupted as shown in the second period of FIG. 2b, the RS flip-flop 2 is not reset, and this As a result, the sawtooth wave may rise forever, raising the output of the smoothing circuit 18 and giving an excessive input to the meter, causing it to break off, or due to the above-mentioned characteristics of the smoothing circuit, the meter may be damaged over a long period of time. There is a problem with giving incorrect instructions.

In addition, as shown in the third cycle of Figure 2b, when multiple reflected waves arrive, a received pulse is detected at the arrival timing of each reflected wave, and by chance this received pulse is below the lower limit level. Even though the liquid level in the storage tank is not actually below the lower limit level, the switch output corresponding to the lower limit level is generated as shown in Figure 2h, and the liquid level is controlled. This will cause problems.

≪Object of the invention≫ The object of the invention is to solve the above-mentioned damage to the meter.
The aim is to solve erroneous instructions and level switch malfunctions all at once.

<<Structure of the Invention>> In order to achieve the above object, the present invention includes a transmitter that emits ultrasonic pulses at a predetermined period toward a reservoir surface in a tank, and a receiver that receives reflected waves of the ultrasonic pulses. a receiving wave shaping circuit that shapes the output of this receiver into a receiving pulse, a simulated receiving pulse generating circuit that emits a simulated receiving pulse before the end of each cycle, and a transmitting timing of the ultrasonic pulse. and a time difference detection circuit that outputs a signal at a level corresponding to the time difference between the received pulses and the simulated received pulses, and the output level of the time difference detection circuit is averaged. a smoothing circuit, a level indicator driven by the output of the smoothing circuit, and an upper limit gate circuit that allows the received pulse to pass only during the reception time range corresponding to the reservoir surface being above the upper limit level. , a determination circuit that determines that the received wave pulse is present in a wave receiving time range corresponding to the case where the storage surface is above the lower limit level; A lower limit gate circuit that allows the received pulse to pass and is preferentially inhibited by the output of the determination circuit only during the reception time domain, and switching based on the output of the upper limit gate circuit and the output of the lower limit gate circuit. The present invention is characterized by comprising a switching circuit that performs the following steps.

<<Description of Embodiment>> Hereinafter, an embodiment of the present invention will be described in detail based on the accompanying drawings.

FIG. 3 is a block diagram showing the electrical configuration of the ultrasonic level meter with switch output according to the present invention, and FIG. 4 is a diagram showing waveforms at various locations indicated by the symbols .about. in FIG.

In the figure, the same components as those of the conventional circuit are designated by the same reference numerals, and the explanation thereof will be omitted.

As shown in FIG. 4, the reference pulse generating circuit 1 outputs a very small width "L" pulse (ie, a reference pulse) at regular intervals, and the RS flip-flop 2 is set by this reference pulse.

Further, the reference pulse is converted into a high frequency pulse through a modulation circuit 3, an oscillation circuit 4 and an amplifier circuit 5,
Ultrasonic pulses are emitted via the wave transmitter 6 toward the bottom of the tank where the contents to be measured are stored.

After the reflected wave is detected via the receiver 7, it is amplified via the amplifier circuit 8 as shown in FIG. This received pulse causes the RS flip-flop 2 to be reset via the NOR gate 22.

Therefore, when the received pulse is normally obtained, the Q output side of the RS flip-flop 2 is
As shown in FIG. 4, a rectangular wave having a time width corresponding to the storage tank content level is output, and this rectangular wave is converted into a sawtooth wave shown in FIG. 4 via an integrating circuit 10, and then converted into a smoothing circuit 11, DC amplifier circuit 12
The signal is smoothed, averaged, amplified to a sufficient output level, and supplied to a meter (needle type, light emitting diode type level indicator), etc.

In other words, as long as the received pulses are normally obtained, the meter will display a normal content level.

On the other hand, in response to the reference pulse, the first monomulti 13
An upper limit gate pulse as shown in FIG. Pass the received pulse.

In response to the output of this NAND gate 23, as shown in FIG. 4, a switch output RS flip-flop (hereinafter abbreviated as switch FF)
24 is set, causing relay 26 to be deenergized via transistor 25.

That is, when the reservoir contents level exceeds the upper limit level, relay 26 is deenergized and its contacts 27 are turned off.

Next, the second monomulti 14 receives the reference pulse and outputs an "L" lower limit gate pulse as shown in FIG. 2 reset terminal and NAND gate 2
9.

Therefore, the leading edge of the lower limit gate pulse is supplied to the reset terminal of the RS flip-flop 2 every cycle, and even if the reflected wave discontinuation occurs as shown in the second and fourth cycles of FIG. , RS flip-flop 2 is always reset by the leading edge of the lower limit gate pulse.

In other words, even if the reflected wave is interrupted, the RS flip-flop 2 is always reset before the end of each cycle, so the peak of the sawtooth wave output from the integrating circuit 10 is always limited to a certain value or less.
Excessive input to the meter is prevented, and the meter reading will not be erroneous for a long time due to the characteristics of the smoothing circuit 11.

Further, the lower limit gate pulse output from the second monomulti 14 is also supplied to the NAND gate 30.

Therefore, the NAND gate 30 opens only in the wave reception time range corresponding to the storage tank content level being above the lower limit, and the wave reception pulse outputted from the detection circuit 9 during that time range as shown in FIG. pass. The output of the NAND gate 30 is then delayed by at least one period via the rise delay circuit 31 and then supplied to the NAND gate 29.

Therefore, if even one reception pulse exists in the reception time range corresponding to the storage tank content level being above the lower limit, the NAND gate 29 is preferentially prohibited for at least the existence period. On the contrary, when there is no reception pulse in the above reception time range, it opens only in the reception time range corresponding to the storage tank contents level being below the lower limit level, and allows the reception pulse to pass through. become.

In other words, as shown in the first and third periods in FIG. Even if the wave exists in the reception time range that corresponds to below the lower limit level,
The erroneous reflected wave cannot pass through the NAND gate 29.

As a result, the received pulse passes through the output side of the NAND gate 29 only when the storage tank content level actually falls below the lower limit level, as shown in the sixth cycle of FIG. The pulse will reset switch FF 24 and energize relay 26.

Therefore, according to this circuit, the second and fourth circuits in FIG.
As shown in the period, even if the reflected waves are interrupted, the meter will no longer swing out or have incorrect readings for a long time, and even if multiple reflected waves arrive, as shown in the first and third periods of Figure 4, A switch output can be reliably generated only at preset upper and lower limit levels.

Note that the illustrated example is configured so that the switch FF 24 is provided so that a two-point level control output is generated via the contact 27 of the relay 26.
Of course, as shown in the conventional example shown in FIG. 1, an integrating circuit and a Schmitt circuit can be provided to issue separate switch outputs (for example, alarm outputs) at the upper limit level and lower limit level.

<<Effects of the Invention>> As is clear from the above description, according to the present invention, in this type of level meter with a switch output, meter damage caused by interruption of reflected waves, long-term incorrect indications, and multiple reflections are avoided. The malfunction of the level meter caused by this can be solved all at once, and the reliability of this type of device can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional circuit of an ultrasonic level meter with a switch output, and FIG. 2 is a diagram showing waveforms of each part labeled a to h in FIG. 1.
FIG. 3 is a block diagram showing the electrical configuration of the ultrasonic level meter with switch output according to the present invention, and FIG.
The figure is a diagram showing waveforms at respective locations marked with symbols .about. in FIG. 3. 2, 10... Time difference detection circuit, 6... Transmitter,
7... Receiver, 8, 9... Receiving wave shaping circuit, 11...
...Smoothing circuit, 14...Simulated received pulse generation circuit,
23... Upper limit gate circuit, 24... Flip-flop circuit, 29... Lower limit gate circuit, 30, 31
...Judgment circuit.

Claims (1)

[Claims] 1. A transmitter that emits ultrasonic pulses at a predetermined period toward a reservoir surface in a tank, a receiver that receives reflected waves of the ultrasonic pulses, and an output of the receiver. a receiving wave shaping circuit that shapes the receiving pulse into a receiving pulse; a simulated receiving pulse generating circuit that emits a simulated receiving pulse before the end of each cycle; or a simulated received pulse, and outputs a signal with a level corresponding to the time difference between them; a smoothing circuit that averages the output level of this time difference detection circuit; a level indicator to be driven; an upper limit gate circuit that allows the received wave pulse to pass only in the wave reception time range corresponding to the case where the storage surface is above the upper limit level; a determination circuit that determines that the received pulse exists in the received wave time range corresponding to the fact that the above-mentioned received pulse is present only in the received wave time range that corresponds to the case where the storage surface is below the lower limit level; A lower limit gate circuit that allows a pulse to pass and is preferentially inhibited by the output of the determination circuit, and a switching circuit that performs switching based on the output of the upper limit gate circuit and the output of the lower limit gate circuit. Features: Ultrasonic level meter with switch output.