JPS6238951A - Discrimination system for microprogram loop - Google Patents

Discrimination system for microprogram loop

Info

Publication number
JPS6238951A
JPS6238951A JP60178099A JP17809985A JPS6238951A JP S6238951 A JPS6238951 A JP S6238951A JP 60178099 A JP60178099 A JP 60178099A JP 17809985 A JP17809985 A JP 17809985A JP S6238951 A JPS6238951 A JP S6238951A
Authority
JP
Japan
Prior art keywords
timer
microprogram
executed
memory
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60178099A
Other languages
Japanese (ja)
Inventor
Koichi Kondo
弘一 近藤
Kiyoshi Takahashi
清 高橋
Norio Shimada
嶌田 典郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60178099A priority Critical patent/JPS6238951A/en
Publication of JPS6238951A publication Critical patent/JPS6238951A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To discriminate whether a microprogram is looped or not by providing a micro instruction that starts up a timer at the entrance of a path where generally the micro instruction passes through and resets it at the exit, storing the content of a memory or a register at a prescribed memory area when the timer is time over and performing an abnormal interruption in a high-order program. CONSTITUTION:When a micro program is started, first of all, an input process part 1 is executed and next, a timer 3 is started up and next, a pre-process part 2 is executed and after that, either of process parts 7a-7d is executed. After the processes of the process parts, the timer 3 is reset by a passing check part 6 and after that, a termination process part 5 is executed. For example, the microprogram is looped at the process part 7a, the timer 3 is time over. By the time over of the timer, a logging part 4 is operated, thereby the content of the memory or the register being saved at a prescribed fixed area, and after that, the occurrence of abnormality is informed to the high-order program by the abnormal interruption.

Description

【発明の詳細な説明】 〔概要〕 マイクロプログラムの通常通過する入口部分にタイマを
起動させるマイクロ命令を設け、マイクロプログラムの
通常通過する出口部分に上記タイマをリセットするマイ
クロ命令を設け、更に上記タイマがタイム・オーバした
時、上位プログラムにこの旨を割込みで通知すると共に
メモリやレジスタの内容を固定領域に格納するマイクロ
ルーチンをマイクロプログラムに設けたものである。
[Detailed Description of the Invention] [Summary] A microinstruction for activating a timer is provided at an entrance portion through which a microprogram normally passes; a microinstruction for resetting the timer is provided at an exit portion through which a microprogram normally passes; When a timeout occurs, the microprogram is provided with a microroutine that notifies the higher-level program of this fact through an interrupt and stores the contents of the memory and registers in a fixed area.

〔産業上の利用分野〕[Industrial application field]

本発明は、マイクロプログラムがループしているか否か
を判別するマイクロプログラムのループ判別方式に関す
るものである。
The present invention relates to a microprogram loop determination method for determining whether a microprogram is looping.

〔従来技術と問題点〕[Prior art and problems]

従来技術においては、マイクロプログラムがループした
場合は、判別できず、ダンマリ状態が続き暫くしてから
ループしたことが判明していた。
In the prior art, if a microprogram loops, it cannot be determined, and the program remains in a sluggish state for a while before it is discovered that the program has looped.

〔発明の目的〕[Purpose of the invention]

本発明は、このマイクロプログラムのループ状態を最小
限にすると共に、マイクロプログラムの再起動及び障害
調査を行い易くすることが出来るマイクロプログラムの
ループ判別方式を提供することを目的としている。
SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram loop determination method that can minimize the loop state of the microprogram and facilitate restarting the microprogram and investigating failures.

〔目的を達成するための手段〕[Means to achieve the purpose]

そしてそのため、本発明のマイクロプログラムのループ
判別方式は、マイクロプログラムの通常通過する入口に
タイマーを起動するマイクロ命令を設け、マイクロプロ
グラムの通常通過する出口に上記タイマーをリセットす
るマイクロ命令を設けると共に、上記タイマーがタイム
・オーバした時、メモリやレジスタの内容を所定のメモ
リ領域に格納し、上位プログラムに異常割込みをかける
マイクロルーチンをマイクロプログラム中に設けること
を特徴とするものである。
Therefore, the microprogram loop determination method of the present invention provides a microinstruction for activating a timer at an entrance through which the microprogram normally passes, and a microinstruction for resetting the timer at an exit through which the microprogram normally passes. The present invention is characterized in that a microroutine is provided in the microprogram to store the contents of the memory or register in a predetermined memory area and issue an abnormal interrupt to the higher-level program when the timer times out.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を図面を参照しつつ説明する。図は本発明
の1実施例構成を示す図である。図において、1は入力
処理部、2は前処理部、3はタイマー、4はロギング部
、5は終結処理部、6は通過チェック部、7aないし7
dは処理部、8は基本制御部分、9はループ・チェック
部分、10は処理部分を示している。基本制御部分8は
部分1ないし6から構成され、ループ・チェック部分9
は部分3,4.6から構成され、処理部分は部分7aな
いし7dから構成されている。
Hereinafter, the present invention will be explained with reference to the drawings. The figure is a diagram showing the configuration of one embodiment of the present invention. In the figure, 1 is an input processing section, 2 is a preprocessing section, 3 is a timer, 4 is a logging section, 5 is a final processing section, 6 is a passage check section, and 7a to 7
d indicates a processing section, 8 a basic control section, 9 a loop check section, and 10 a processing section. The basic control section 8 consists of sections 1 to 6, and includes a loop check section 9.
consists of sections 3, 4.6, and the processing section consists of sections 7a to 7d.

上位プログラムの機械語命令はマイクロプログラムによ
って実行される。マイクロプログラムが起動されると、
まず入力処理部1が実行され、次にタイマー3が起動さ
れ、次に前処理部2が実行され、次に処理部7aないし
7dの中の1個が実行される。処理部による処理が行わ
れた後、il通過チェック6によりタイマー3がリセッ
トされ、次いで終結処理部5が実行される。例えば処理
部7aでマイクロプログラムがループすると、タイマー
3がタイム・オーバする。タイマー3がタイム・オーバ
すると、ロギング部4が働き、これにより、メモリやレ
ジスタの内容が所定の固定領域にセーブされ、しかる後
に異常割込みにより異常発生が上位プログラムに通知さ
れる。
The machine language instructions of the higher-level program are executed by the microprogram. When the microprogram is started,
First, the input processing section 1 is executed, then the timer 3 is started, then the preprocessing section 2 is executed, and then one of the processing sections 7a to 7d is executed. After the processing by the processing section is performed, the timer 3 is reset by the il passage check 6, and then the finalization processing section 5 is executed. For example, when the microprogram loops in the processing section 7a, the timer 3 times out. When the timer 3 times out, the logging unit 4 operates, thereby saving the contents of the memory and registers in a predetermined fixed area, and then notifying the higher-level program of the occurrence of the abnormality by an abnormality interrupt.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明によれば、 fat  マイクロプログラムがループしたことを速や
かにオペレータ等に通知できること、 fbl  ループ時のメモリ内容及びレジスタ類等の障
害調査に必要な情報をロギング出来ること、(C1ルー
プ 判別しているため、ループしたときの判別時間が短くな
り、即座にオペレータ等に通知することが出来、マイク
ロプログラムの再起動等の復旧を素早く出来ること、 等の顕著な効果を奏し得る。
As is clear from the above description, according to the present invention, it is possible to promptly notify an operator etc. that the fat microprogram has looped, and to log information necessary for fault investigation such as memory contents and registers during the fbl loop. (Because C1 loops are identified, the time it takes to determine when a loop occurs is shortened, operators, etc. can be notified immediately, and recovery such as restarting the microprogram can be quickly performed.) It can be effective.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の1実施例構成を示す図である。 ■・・・人力処理部、2・・・前処理部、3・・・タイ
マー、4・・・ロギング部、5・・・終結処理部、6・
・・通過チェック部、7aないし7d・・・処理部、8
・・・基本制御部分、9・・・ループ・チェック部分、
10・・・処理部分。
The figure is a diagram showing the configuration of one embodiment of the present invention. ■...Human processing unit, 2...Preprocessing unit, 3...Timer, 4...Logging unit, 5...Final processing unit, 6...
... Passage check section, 7a to 7d... Processing section, 8
...Basic control part, 9...Loop check part,
10...Processing part.

Claims (1)

【特許請求の範囲】[Claims] マイクロプログラムの通常通過する入口にタイマーを起
動するマイクロ命令を設け、マイクロプログラムの通常
通過する出口に上記タイマーをリセットするマイクロ命
令を設けると共に、上記タイマーがタイム・オーバした
時、メモリやレジスタの内容を所定のメモリ領域に格納
し、上位プログラムに異常割込みをかけるマイクロルー
チンをマイクロプログラム中に設けることを特徴とする
マイクロプログラムのループ判別方式。
A microinstruction to start a timer is provided at the entrance through which the microprogram normally passes, a microinstruction to reset the timer is provided at the exit through which the microprogram normally passes, and when the timer times out, the contents of the memory and registers are 1. A loop determination method for a microprogram, characterized in that a microroutine is provided in the microprogram for storing the code in a predetermined memory area and issuing an abnormal interrupt to a higher-level program.
JP60178099A 1985-08-13 1985-08-13 Discrimination system for microprogram loop Pending JPS6238951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60178099A JPS6238951A (en) 1985-08-13 1985-08-13 Discrimination system for microprogram loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60178099A JPS6238951A (en) 1985-08-13 1985-08-13 Discrimination system for microprogram loop

Publications (1)

Publication Number Publication Date
JPS6238951A true JPS6238951A (en) 1987-02-19

Family

ID=16042622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60178099A Pending JPS6238951A (en) 1985-08-13 1985-08-13 Discrimination system for microprogram loop

Country Status (1)

Country Link
JP (1) JPS6238951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151942A (en) * 1988-12-02 1990-06-11 Nec Corp System for collecting cpu using state at the time of generating cpu loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151942A (en) * 1988-12-02 1990-06-11 Nec Corp System for collecting cpu using state at the time of generating cpu loop

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