JPS6238885B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation signal amplification circuit for amplifying a pulse width modulation signal used in an output circuit of a stereo reproduction device, and more particularly, to a pulse width modulation signal amplification circuit for amplifying a pulse width modulation signal used in an output circuit of a stereo reproduction device, and more particularly, to This is designed to improve distortion.

Conventionally, a pulse width modulation signal amplification circuit as shown in FIG. 1 has been used in the output circuit of a stereo reproduction device. That is, in FIG. 1, 1 indicates an audio signal input terminal to which an audio signal is supplied, and the audio signal supplied to this audio signal input terminal 1 is supplied to a pulse width modulation circuit 2. In 2,
The carrier wave signal is pulse width modulated by this input audio signal. The pulse width modulation signal of the audio signal obtained at the output side of the pulse width modulation circuit 2 is supplied to the bases of the npn type transistor 3 and the pnp type transistor 4, respectively. The respective emitters of the transistors 3 and 4 are connected to each other, and the connection point of the respective emitters of the transistors 3 and 4 is connected to a resistor 5.
, and the collector of the transistor 3 is connected to the cathodes of the diodes 6 and 7, respectively.
The anode of this diode 6 is connected to the base of a pnp transistor 8, and the base of this transistor 8 is connected to a positive DC voltage Vcc through a resistor 9.
The emitter of this transistor 8 is connected to the power supply terminal 10, and the anode of the diode 7 is connected to the collector of the transistor 8. Further, the collector of the transistor 4 is connected to the anodes of diodes 11 and 12, and the cathode of the diode 11 is connected to the base of an NPN transistor 13, and the base of the transistor 13 is connected to a negative DC voltage through a resistor 14. -Vcc is connected to the power supply terminal 15, and the emitter of this transistor 13 is connected to the power supply terminal 15, and the cathode of the diode 12 is connected to the collector of the transistor 13, and the collector of this transistor 13 is connected to the cathode of the diode 16. The anode of this diode 16 is connected to the collector of the transistor 8. The collector of this transistor 8 is connected to the base of an npn transistor 17 constituting one switching element, and the collector of the transistor 13 is connected to the base of a pnp transistor 18 constituting the other switching element.
The emitters of transistors 7 and 18 are connected to each other, the collector of transistor 17 is connected to power supply terminal 10 to which positive DC voltage Vcc is supplied, and the collector of transistor 18 is connected to power supply terminal 10 to which negative DC voltage -Vcc is supplied. Connected to terminal 15 and also connected to transistor 1
The connection points of the respective emitters 7 and 18 are connected to the anode of the return current processing diode 19 and the cathode of the return current processing diode 20, and the cathode of this diode 19 is connected to the power supply terminal 10, and the diode 20 The anodes of the transistors 17 and 18 are connected to the power supply terminal 15, and the connection points of the respective emitters of the transistors 17 and 18 are grounded through a low pass filter 21 consisting of a coil 21a and a capacitor 21b and a load resistor such as a speaker 22.

In FIG. 1, when a pulse width modulation signal as shown in FIG. 2A obtained at the output side of the pulse width modulation circuit 2 is supplied to the bases of transistors 3 and 4, a switching element is formed. A similar pulse width modulation signal is supplied to the bases of transistors 17 and 18 to turn them on and off alternately. Since the amplified signal is obtained and the amplified pulse width modulated signal is supplied to the speaker 22 via the reduction pass filter 21, the reproduced sound of the audio signal supplied from the speaker 22 to the audio signal input terminal 1 is can be obtained.

However, in FIG. 1, if the pulse width modulation signals supplied to the bases of transistors 17 and 18 are as shown in FIG. 2A, for example, transistor 17, return current processing diode 19, and transistor 18 and the return current processing diode 20, the currents I ₁ , I ₂ ,
I ₃ and I ₄ are as shown in FIG. 2 B, C, D and E, respectively, and the return current handling diode 19
When the current _I2 is flowing through the output voltage, that is, the voltage Vo obtained at the connection point of the respective emitters of the transistors 17 and 18, the level is Vcc + Vf (Vf is the forward voltage drop of the diode) as shown in Figure 2G. ), and when the current _I1 is flowing through the transistor 17, the output voltage Vo becomes Vcc-Vs (Vs is the saturation voltage between the collector and emitter of the transistor) as shown in FIG. 2G, and this return current When the current _I4 is flowing through the processing diode 20, the output voltage Vo is − as shown in FIG. 2G.
When the current _I3 is flowing through the transistor 18, the output voltage Vo becomes -Vcc+Vs as shown in FIG. 2G, and the waveform of the output voltage Vo has a nonlinear step in the amplitude direction. This nonlinear waveform of the output voltage Vo in the amplitude direction causes distortion in the signal supplied to the load resistor, such as the speaker 22, and causes distortion in the output audio signal. FIG. 2F shows the current I ₀ flowing into the load resistor 22 from the connection point of the emitters of the transistors 17 and 18, respectively.

In view of this, the present invention provides an output voltage as described above.
This is intended to improve the distortion of the output signal based on the nonlinearity of the Vo waveform in the amplitude direction.

Hereinafter, one embodiment of the pulse width modulation signal amplification circuit of the present invention will be explained with reference to FIG. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, the connection points of the emitters of the transistors 17 and 18 constituting the switching element are connected to the anode of the return current processing diode 19 and the cathode of the return current processing diode 20, respectively. is connected via a capacitor 23 to the power supply terminal 10 to which a positive DC voltage Vcc is supplied, and the anode of the diode 20 is connected via a capacitor 24 to a power supply terminal 15 to which a negative DC voltage -Vcc is supplied. Further, 25 indicates a square wave signal oscillation circuit that generates a 20kHz square wave signal, and the output signal of this square wave oscillation circuit 25 is supplied to the primary winding 26a of the transformer 26, and the secondary winding of this transformer 26 npn constituting a switching element at one end of the line 26b
It is connected to the base of the transistor 27a, and the other end of the secondary winding 26b is connected to the base of the transistor 27a.
This transistor 27 is connected to the emitter of 7a.
Connect the collector of a to diode 19 and capacitor 2
Connect to connection point 3. Also, this transformer 26 has 2
A tertiary winding 26c is provided, which is wound so as to obtain an output signal having a phase opposite to that of the secondary winding 26b, and one end of this tertiary winding 26c constitutes a switching element.
It is connected to the base of the npn transistor 27b, and the other end of the tertiary winding 26c is connected to the base of the transistor 27b.
7b, and this transistor 27
Connect the emitter of b to diode 20 and capacitor 2.
Connect to connection point 4. Also, the emitter of the transistor 27a is connected to the collector of the transistor 27b, and the connection point between the emitter of the transistor 27a and the collector of the transistor 27b is connected to the transformer 2.
It is grounded through the primary winding 28a of No.8. In this case, the secondary winding 26b and the tertiary winding 26 of the transformer 26
The transistors 27a and 27b are turned on and off alternately by the output signal of the square wave signal oscillation circuit 25, since the transistors 27a and 27b are wound so that signals having opposite phases to each other can be obtained. Also, one end of the secondary winding 28b of this transformer 28 is grounded, and the other end of this secondary winding 28b is connected to the anode of the diode 29 and the cathode of the diode 30, respectively, and the cathode of the diode 29 is connected to the power supply terminal 10. At the same time, the anode of this diode 30 is connected to the power supply terminal 15. In this case, the collector-emitter saturation voltage of each of the transistors 17 and 18 is Vs, the forward drop voltage of each of the diodes 19, 20, 29, and 30 is Vf, and the transistors 27a and 27
Since b can be used with a small current capacity, the saturation voltage between the collector and emitter is extremely small and can be ignored, and when the number of turns of the primary winding 28a of the transformer 28 is
N ₁ , and when the number of turns of the secondary winding 28b is N ₂ , N ₂ /N ₁ ≒Vcc+Vf/Vcc-(Vf+V
s). Also in this case transformer 2
The ground side of the primary winding 28a of No. 8 is set as the cool side, and one end of the secondary winding 28b, that is, the ground side is set as the hot side. The rest of the structure is the same as in FIG. 1.

Since the present invention is constructed as described above, a pulse width modulation signal as shown in FIG. At this time, this pulse width modulation signal is supplied to the respective bases of transistors 17 and 18 constituting the switching element, turns these transistors 17 and 18 on and off alternately, and connects the emits of these transistors 17 and 18 to the connection point of each emitter. An amplified pulse width modulated signal is obtained, and this amplified pulse width modulated signal is supplied to the speaker 22 via the low-pass filter 21, so that it is supplied from the speaker 22 to the audio signal input terminal 1. You can obtain the reproduced sound of the audio signal.

Further, when a pulse width modulation signal as shown in FIG. 2A is supplied to the bases of the transistors 17 and 18, the transistor 1
7. Return current processing diode 19, transistor 18 and return current processing diode 2
0 as shown in Figure 2 B, C, D and E, respectively.
I ₁ , I ₂ , I ₃ and I ₄ flow. In this case, when the resistance value of each of the transistors 27a and 27b when turned on is set to zero (the saturation voltage is zero), the voltage at the connection point b between the diode 19 and the capacitor 23 is
When the transistor 27a is on at Vcc-(Vf+Vs), this connection point d between the emitter of the transistor 27a and the collector of the transistor 27b is
A voltage of Vcc−(Vf+Vs) is generated, and the transformer 28
A voltage of _-N2 / _N1 (Vcc-Vf-Vs)=-Vcc-Vf is generated at the connection point e between the secondary winding 28b and the diodes 29 and 30. Therefore, since the voltage drop across the diode 30 is Vf, when the voltage at point b attempts to rise further, this diode 30 turns on and current flows in the direction of the power supply terminal 15 to which the negative DC voltage -Vcc is supplied. Therefore, the output voltage at the connection point a of the emitters of transistors 17 and 18 is
When Vo is about to rise above Vcc-Vs, the return current processing diode 19 is turned on, and the charge associated with this rise is returned to the negative power supply terminal 15.

Also, when the voltage at the connection point c between the diode 20 and the capacitor 24 is -Vcc+(Vf+Vs) and the transistor 27b is on, the voltage at the point d is -Vcc+(Vf+
A voltage of −N ₂ /N ₁ (−Vcc+Vf+Vs)=Vcc+Vf is generated at point e. Therefore, since the voltage drop across diode 29 is Vf, when the voltage at point c is about to drop further, diode 29 turns on and current flows in the direction of power supply terminal 10 to which positive DC voltage Vcc is supplied. The output voltage Vo at the connection point a of the emitters of each of transistors 17 and 18 is −Vcc.
When the voltage is about to drop below +Vs, the return current processing diode 20 turns on, and the charge related to this drop is returned to the positive power supply terminal 10.

Therefore, when the transistors 27a and 27b are turned on and off alternately and the above operations are repeated in sequence, b
The voltage at the point always maintains Vcc-(Vf+Vs), and c
The voltage at the point will always remain -Vcc+(Vf+Vs). Therefore, the amplitude of the output voltage Vo when the current _I2 is flowing through the diode 19 is also equal to the amplitude Vcc-Vs when the current _I1 is flowing through the transistor 17, as shown in FIG.
The amplitude of the output voltage Vo when the current I ₄ is flowing through the transistor 18 is also as shown in FIG _.
The amplitude is equal to -Vcc+Vs when is flowing, and the amplitude direction of the output signal is linear.

Therefore, according to the present invention, it is possible to improve the distortion of the output signal due to the nonlinearity of the output voltage Vo waveform in the amplitude direction.

Further, FIGS. 4 and 5 respectively show other embodiments of the present invention. In the example in FIG. 3, the switching circuit consisting of transistors 17 and 18 constituting the switching element is configured as an emitter-follower switching circuit, but in FIG. 4, it is configured as a collector-follower switching circuit. , FIG. 5 shows an example of a drain follower switching circuit configuration.

That is, in FIG. 4, the collector of transistor 3 is connected to the bases of NPN transistor 31 and PNP transistor 32, and the connection point of the bases of transistors 31 and 32 is connected to the power supply via resistor 33. The collector of the transistor 31 is connected to the power supply terminal 10, and the emitters of the transistors 31 and 32 are connected to each other, and the connection point of these emitters is connected to the base of the pnp transistor 17a constituting the switching element. The collector of the transistor 32 is connected to the power supply terminal 10 via the bias setting battery 34, and the collector of the transistor 4 is connected to the bases of the NPN transistor 35 and the PNP transistor 36, respectively. 35 and 3
6 is connected to the power supply terminal 15 via a resistor 37, the collector of the transistor 35 is connected to the power supply terminal 15 via a bias setting battery 38, and the husbands of the transistors 35 and 36 are connected to each other. Connect the emitters of the emitters to each other, connect the connection point of the emitters to the base of the npn transistor 18a that constitutes the switching element, and connect the transistor 3.
6 is connected to the power supply terminal 15, and the connection point of the bases of transistors 35 and 36 is connected to 2.
A series circuit of diodes 39 and 40 is connected to a connection point between the bases of transistors 31 and 32, and a connection point between diodes 39 and 40 is connected to a connection point between the collectors of transistors 17a and 18a. Connect this transistor 1
The connection point of each collector of 7a and 18a is connected to the connection point of return current processing diodes 19 and 20, and the connection point of this collector is connected to a load resistor 22 via a low-pass filter 21, The emitter of the transistor 17a is connected to the power supply terminal 10, and the emitter of the transistor 18a is connected to the power supply terminal 15, and the other configuration is the same as that shown in FIG. 4 shows a configuration in which the switching circuit in the example shown in FIG. 3 is configured as a collector follower switching circuit, and it is noted that this example in FIG. It's easy to understand.

FIG. 5 also shows that the collector of the transistor 3 is connected to the cathodes of diodes 41 and 42, respectively, and the anode of this diode 41 is connected to the bases of an npn type transistor 43 and a pnp type transistor 44, respectively. and 4
4 are connected to the power supply terminal 10 via a resistor 45, the collector of the transistor 43 is connected to the power supply terminal 10, and the anode of the diode 42 is connected to the collector of the transistor 44. The collector of is connected to the power supply terminal 10 via a bias setting battery 46, and the emitters of transistors 43 and 44 are connected to each other, and this connection point is connected to the gate of a field effect transistor 47 constituting a switching element. Connecting. Further, the collector of transistor 4 is connected to the anodes of diodes 48 and 49, respectively.
The cathode of this diode 48 is connected to the bases of an npn transistor 50 and a pnp transistor 51, and the connection point of the bases of the transistors 50 and 51 is connected to the power supply terminal 15 via a resistor 52, Further, the collector of the transistor 51 is connected to the power supply terminal 15, the cathode of the diode 49 is connected to the collector of the transistor 50, and the collector of this transistor 50 is connected to the power supply terminal 15 via the battery 53 for bias setting. The emitters of the transistors 50 and 51 are connected to each other, and the connection point of the emitters is connected to the gate of the field effect transistor 54. The sources of the field effect transistors 47 and 54 are connected to the power supply terminals 10 and 15, respectively,
The drain of the field effect transistor 47 is connected to the drain of the field effect transistor 54 through a series circuit of diodes 55 and 56, and the connection point between the diodes 55 and 56 is connected to the connection point between the return current processing diodes 19 and 20. At the same time, the connection point between the diodes 55 and 56 is connected to the load resistor 22 via the low-pass filter 21. The rest of the structure is the same as that shown in FIG.

5 shows a configuration in which the switching circuit in the above-mentioned example in FIG. 3 is configured as a drain follower switching circuit, and it is noted that this example in FIG. 5 has the same effect as in the example in FIG. 3. It's easy to understand. However, in this example in FIG. 5, when the saturation voltage of the field effect transistors 47 and 54 is Vs, the output point when the current _I1 is flowing through the field effect transistor 47, that is, the connection point a of the diodes 55 and 56. The output voltage at point a is Vcc-(Vs+2Vf), and the output voltage at point a when current _I3 is flowing through the field effect transistor 54 is -Vcc+(Vs+2Vf).
2Vf), so the voltage at points b and c is Vcc-(Vs
The number of turns N ₁ of the primary winding 28a of the transformer 28 and the number of turns N ₂ of the secondary winding 28b of the transformer 28 are selected so that the voltages are +2Vf) and -Vcc+(Vs+2Vf).

It goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations can be adopted without departing from the gist of the present invention.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional pulse width modulation signal amplification circuit, Fig. 2 is a diagram for explaining the present invention, and Fig. 3 shows an embodiment of the pulse width modulation signal amplification circuit of the present invention. The block diagram, FIG. 4, and FIG. 5 are block diagrams showing other embodiments of the present invention, respectively. 1 is an audio input terminal, 2 is a pulse width modulation circuit, 1
0 is the power supply terminal to which positive DC voltage Vcc is supplied, 1
5 is a power supply terminal to which negative DC voltage -Vcc is supplied;
17, 18, 27a and 27b are transistors, 19, 20, 29 and 30 are diodes, 23 and 24 are capacitors, 25 is a square wave signal oscillation circuit, and 26 and 28 are transformers.

Claims (1)

[Claims] 1. It has a series circuit of first and second switching elements that are turned on and off alternately by a pulse width modulation signal, one end and the other end of the series circuit are connected to positive and negative DC power sources, respectively, and the first and second switching elements are The connection point of the second switching element is connected to the positive DC power supply through a series circuit of a first return current processing diode and a first capacitor, and the connection point of the first and second switching elements is connected to the first return current processing diode and the first capacitor. connected to the negative DC power supply through a series circuit of a return current processing diode No. 2 and a second capacitor;
The connection point between the first and second switching elements is connected to the load via a low-pass filter, and the connection point between the first return current processing diode and the first capacitor is alternately connected at a predetermined frequency. Connect to the connection point of the second return current processing diode and the second capacitor through a series circuit of third and fourth switching elements that turn on and off, and connect the third and fourth switching elements. Connect the point to one end of the primary winding of the transformer, and
The other end of the secondary winding and the other end of the secondary winding of the transformer are respectively grounded, one end of the secondary winding is connected to the anode of the third diode and the cathode of the fourth diode, respectively. A pulse width modulation signal amplification circuit characterized in that the cathode of the third diode is connected to the positive DC power supply, and the anode of the fourth diode is connected to the negative DC power supply.