JPS6236555B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch with a game having a liquid crystal display device.

Conventionally, it has been almost impossible to add games to electronic watches due to the limited number of display pixels of the display device of electronic watches, or it has been limited to extremely simple games.

An object of the present invention is to provide an electronic timepiece that also serves as a part of the display device of the electronic timepiece and enables a game of competing for the time to hit a target by adding relatively simple display pixels and a simple electronic circuit. That's true.

The present invention is an electronic watch having a liquid crystal display device, in which a plurality of target pixels of almost the same shape are arranged in the display device, and the time the attached switch button is pressed is measured. It has a circuit that improves accuracy, displays the result using target pixels, and also has a circuit that changes the hit pattern depending on the timing at which the switch button is pressed. In order to add more specificity and make the game more interesting, the target pixels are in the shape of 10 bowling pins, and some of the pixels normally used to display time are used to display the trajectory of the bowl. .

FIG. 1 shows a schematic diagram of an electronic timepiece with a game according to the present invention, and the figure shows an example in which target pixels are represented in the shape of bowling pins, and a game is being executed. This is the display just before some of the ten pins 10 disappear when you release your finger from the switch button A11 at the final stage of the bowl shot. Switch button B12 is pressed to reset the game, and switch button C13 is used to switch between time display and game display. Display 14, 15, 1
6,17 represents the trajectory of the bowl, 17,1
6, 15, 14 are lit up.

Figures 2a and 2b show display pixels of the present invention. A pixel is an overlapping portion of transparent electrodes located on both sides of a liquid crystal layer of a display device. The electrode configuration differs depending on the driving method, such as the adoption of multiplex driving, and is not the essential content of the present invention, so explanations and illustrations will be omitted. A is an example in which hours, minutes, and bowling pins are displayed, and b is an example in which hours, minutes, seconds, and bowling pins are displayed.

Normally, in order to display the time, oscillation, frequency division, timekeeping,
The circuit configuration of the drive etc. is a well-known technical matter, and the explanation thereof will be omitted. FIG. 3 is a circuit diagram for implementing game logic related to the basic content of the present invention.
FIG. 4 is a timing chart of important signals.

By pressing the switch button A11, the switch terminal 31 changes from a low potential (earth) to a high potential (VDD), that is, from 0 to 1, and as long as the signal SEN is 1, it is input to the data of the flip-flop 32, and is input to the frequency divider circuit. Basic square wave signal formed
The timing is adjusted to 32Hz and becomes the signal SWA. The signal SWA and the basic square wave signal 64Hz are passed through an AND gate 33 to an 8-bit up counter 3.
4 clock signal CKU. i.e. signal
CKU is only available while pressing switch button A.
This is the clock signal CKU that counts 64Hz pulses. The specified time for the game is set at 2 seconds. In other words, the "strike" in bowling is switch button A.
If you press for just 2 seconds, it will appear. The output bits a ₇ , a ₆ , ..., a ₀ of the counter 34 are 2.
Expressed in base notation, (01111111) and (10000000) are considered strikes, and each time the number differs by 1, the number of fallen pins decreases by 10 x 1/16. The most significant output bit _a7 and other output bits are converted into bits through an exclusive OR gate 35, and are set to _b6 , . . . , _b0 . The converted bits are 2
Expressed in base notation, (1111111) is a strike, and the probability of falling decreases as (1111110), (1111101), etc., (1110000) is 10 × 1/16, and below (1101111), the probability is 0, that is, completely It becomes a "garter".

Bit b ₆ , ..., Ob ₀ is clock latch 36
It latches when the switch signal SWA becomes 0, that is, when the switch button A11 is released. The latched bit signal is c ₆ , ..., c ₀
shall be. The lower 4 bit signals c ₃ , c ₂ , c ₁ , c ₀ are preset into a 4 bit down counter 37 .
The preset signal SAQ is a pulse-like signal immediately after pressing the switch. Upper 3 bits c ₆ ,
1 only when c ₅ and c ₄ are all 1 and signal SEN is 0
A signal CEN is generated by the AND gate 38, and this is ANDed with an inverted signal of 32 Hz to obtain the clock signal CKD of the counter 37.
If any of the upper three bits c ₆ , c ₅ , and c ₄ is not 1, it becomes a "garter" and the signal CEN is not generated. Therefore, if it is not a "garter", the 4-bit down counter 37 starts counting down,
In the case of "Garter", there is no down count.

On the other hand, the reference signals of 16 Hz, 8 Hz, 4 Hz, and 2 Hz are latched in the latch 39 by the pulse signal SAP that is output when the switch button A is pressed. As you can see from Figure 4, the signal SAP is 0 at both 64Hz and 32Hz.
It becomes pulse-like when , but at this time, 16Hz, 8
Hz, 4Hz, and 2Hz each have a 1/2 probability of being 1 or 0, and are determined in various ways depending on the timing at which the switch button is pressed. Output h ₃ of latch 39,
There are 16 combinations of h ₂ , h ₁ , and h ₀ . This changes the hit pattern.

The exclusive OR circuit 47 performs an exclusive OR operation between the output bits d ₃ , d ₂ , d ₁ , d ₀ of the down counter 37 and the pattern signals h ₃ , h ₂ , h ₁ , h ₀ of the clock clutch 39. The signals e ₃ , e ₂ , e ₁ ,
form e ₀ . Here, the 4-bit down counter 37 sequentially counts down from the preset value described above to 0 based on the 32Hz signal, and for each countdown, the current d ₃ , d ₂ , d ₁ , d ₀ and h ₃ , h ₂ ,
e ₃ , e ₂ , _{e 1 and e 0} determined by h 1 and h 0 are output, and the output of the decoder 40 is stored in one of the corresponding latches 41.

For example, if the preset value meant 10, the counter output would be 10, 9, 8, 7, etc.
Decrease the value from 1 to 0 and change the pin position one by one each time. Output of exclusive OR gate 47
It is determined by the decoder 40 based on e ₀ , e ₁ , e ₂ , and e ₃ , and its output is input to the reset terminal of the corresponding latch 41 to store the reset state. The position of the pin where the reset display disappears is 4.
Even if the bitdown counter values are the same, h ₃ ,
Since the values of h ₂ , h ₁ , and h ₀ are different for each game,
The values of e ₃ , e ₂ , e ₁ , and e ₀ have different patterns depending on the game, and if h ₃ and h ₂ are 1 and h ₂ and h ₀ are 0, then each countdown of the down counter 37 e ₃ , e ₂ , e ₁ , e ₀ are 6, 5, 4, 11, 10, 9,
There are 11 values, sequentially 8, 15, 14, 13, and 12.
The e signal is input to a decoder 40 which converts the 4 bits into 16 independent signals and outputs signals f ₀ , . . . , f ₁₅ corresponding to the selection of the bowling pin pixels.

The reset latch 41 is 10, same as the number of pins.
Each of them outputs a signal PN ₀ , PN ₁ , . . . , PN ₉ corresponding to the pixel selection of the pin. but,
There are 16 outputs of the decoder 40, so among them
Use 10 and leave the remaining 6 unused. In the example in Figure 3, f ₀ →PN0, f ₁ →PN1, f ₃ →PN2, f ₄ →PN
3, f ₆ → PN4, f ₇ → PN5, f ₉ → PN6, f ₁₁ → PN
7, f ₁₃ → PN8, f ₁₅ → PN9, but there is no particular necessity. In the previous example, the value of the 4-bit down counter meant 10, and the e outputs were 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 in sequence. Of these, there is no output from 5, 10, 8, 14, and 12, so PN3, 4, 6, 7, 8, and 9
The latches 41 corresponding to the six pins in total are reset and the pin display disappears. The number of pins that fall in this way is 4 bit down counter 37
The value of , that is, depends on the operation time of the switch,
Terminals 2, 5, 8, 10, 12 of decoder 40,
When the output corresponds to 14, the latch 41 is not reset depending on the output, so the pin does not fall, and a chance factor is taken into account. Also, the position of the pin that falls changes from game to game.

The inhibit input of the decoder 40 has a signal
Input the signal CKI obtained by NANDing the signal P32 which is shifted by 1/4 period of 32Hz from CEN. As a result, immediately before the down count, CKI becomes 0 and a specific f signal corresponding to the e signal becomes 1, and one of the corresponding latches 41 is reset each time.
When CEN is 0, that is, when it is "garter"
CKI becomes 1, no f signal is generated, and none of the pins disappear.

The down counter 37 starts counting down from a preset value and stops when it reaches (0000).
Since the NOR gate 42 outputs bit signals d ₃ , d ₂ , d ₁ , d ₀ , the signal STP becomes 1 only when (0000).
Output. Signal STP is D flip-flop 43
input into the signal, it becomes a delayed pulse signal, and the signal
A signal RES is formed by ORing with SWB. This signal RES resets the up counter 34, sets the reset latch 44, and sets the signal SEN to 1. This signal SEN is reset by the signal SAQ, so when it is 1, it specifies whether the bowl can be shot or is being shot, and when it is 0, it specifies the time when the pin collapses and disappears. signal
The inverted signal of SEN is one of the inputs of AND gate 38.
Therefore, the down counter 37 is (0000)
The count is stopped in the state, and at that time the decoder 4
0 inhibit state.

When the switch button B12 is pressed, the switch terminal 45 changes from 0 to 1, the signal SWB is set to 1, the latches 41 and 44 are set, and all pins are set up and displayed, making it possible to shoot.

A circuit 46 that ANDs the signal SWA and the 1 Hz and 2 Hz reference signals or their inverted signals forms a signal for selecting the trajectory of the bowl,
Signals TS ₁ , TS ₂ , TS ₃ , and TS ₄ are selection signals, which correspond to the g segments of each numerical display digit of the 8-figure segment display.

As described above, the present invention can realize a game in which the accuracy of a hit is determined by the time it takes to press a switch button using a relatively simple circuit, a few switch buttons, and a simple display element. Furthermore, when the game is likened to bowling, the pattern of the pins disappearing can be changed randomly to include a chance element, making the game even more interesting.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the invention. FIG. 2 shows a display pixel of the present invention. FIG. 3 is a circuit diagram for game logic of the present invention.
Figure 4 is a timing chart of important signals related to Figure 3. 11... Switch button A, 12... Switch button B, 13... Switch button C, 10... Bowling pin display, 14, 15, 16, 17... Bowl trajectory display. 34...8 bit up counter,
36...Clock clutch, 37...4 bit down counter, 40...Decoder, 41...Set reset latch.

Claims (1)

[Claims] 1. In an electronic timepiece using a liquid crystal display device having a multi-digit 8-shaped segment for time display, the liquid crystal display device has a plurality of target pixels 10, and the center horizontal segment of the 8-shaped segment has a plurality of target pixels 10. moving object pixels 14-17, the external operating member 11, an operating signal from the external operating member and a first clock signal, and outputs the first clock signal while the operating signal is present. Up counter 3 that counts and measures operation time
4. A plurality of first bits into which the most significant bit signal and each bit signal of the up counter are respectively input.
exclusive OR circuit 35, the plurality of first
A down counter 37 inputs the value of the lower bit of the output of the exclusive OR circuit and counts down the input value by a second clock signal, and a down counter 37 inputs a plurality of third clock signals and operates from the external operation member. a first latch 3 for latching the state of said plurality of third clock signals in response to a signal;
9. The signal from the down counter and the first
a plurality of second exclusive OR circuits 47 each receiving signals from the latches; a decoder 4 that sequentially forms lighting signals corresponding to pixels according to the down count of the down counter;
0, provided corresponding to each output of the decoder,
A second latch 41 sequentially latches each lighting output input from the decoder and supplies a lighting driving signal to each pixel serving as the remaining target, and a fourth clock signal and an operating signal from the operating member. An electronic timepiece with a game, comprising a gate circuit 46 that inputs and sequentially supplies drive signals to the plurality of moving object pixels.