JPS6236183B2 - - Google Patents
Info
- Publication number
- JPS6236183B2 JPS6236183B2 JP54156154A JP15615479A JPS6236183B2 JP S6236183 B2 JPS6236183 B2 JP S6236183B2 JP 54156154 A JP54156154 A JP 54156154A JP 15615479 A JP15615479 A JP 15615479A JP S6236183 B2 JPS6236183 B2 JP S6236183B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- amplifier
- under test
- switch
- device under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 29
- 238000005259 measurement Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Description
【発明の詳細な説明】
本発明は試験装置に係り、特に半導体集積回路
等の試験を行うための電圧印加電流測定回路に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test device, and more particularly to a voltage applied current measuring circuit for testing semiconductor integrated circuits and the like.
一般に、半導体集積回路等の電気的特性試験・
測定においては各端子の直流特性を測定する必要
があり、このために試験装置は電圧印加電流測定
回路を内蔵している。 Generally, electrical property testing and testing of semiconductor integrated circuits, etc.
In the measurement, it is necessary to measure the DC characteristics of each terminal, and for this purpose the test device has a built-in voltage applied current measurement circuit.
本発明はこの電圧印加電流測定回路の改善を目
的としている。 The present invention aims to improve this voltage applied current measuring circuit.
試験装置を内蔵する従来の電圧印加電流測定回
路のブロツク図を第１図に示す。同図において１
は演算増幅器、２は演算増幅器によつて構成され
る電圧フオロア、３は被測定物、４，５はスイツ
チを示し、動作を説明すれば以下のようになる。
端子６に電圧0Vが加えられている状態で、スイ
ツチ４および５を閉じ、被測定物３と接続し、ス
イツチ４および５の閉動作が完全に安定するに充
分な時間、待つた後端子６に電圧Eiを加えると
あらかじめ設定された抵抗値R2，R3によつて決
まる電圧Eoが被測定物３に印加される。電圧フ
オロア２の入力抵抗は非常に大きいため、被測定
物３に流れる電流はすべて、あらかじめ設定され
た抵抗R1を流れる。従つて抵抗R1の電圧降下を
測定すれば被測定物３に流れる電流が求まる。 A block diagram of a conventional voltage applied current measuring circuit with a built-in test device is shown in FIG. In the same figure, 1
2 is an operational amplifier, 2 is a voltage follower constituted by the operational amplifier, 3 is an object to be measured, and 4 and 5 are switches.The operation will be explained as follows.
With a voltage of 0V applied to terminal 6, close switches 4 and 5, connect the device under test 3, wait a sufficient time for the closing operation of switches 4 and 5 to become completely stable, and then close switches 4 and 5. When voltage Ei is applied to , a voltage Eo determined by preset resistance values R 2 and R 3 is applied to the object to be measured 3 . Since the input resistance of the voltage follower 2 is very large, all the current flowing through the device under test 3 flows through the preset resistance R 1 . Therefore, by measuring the voltage drop across the resistor R1 , the current flowing through the object to be measured 3 can be determined.
しかしながら従来の回路においてはスイツチ４
および５を閉じた瞬間は、端子６の入力電圧が
0Vなので、被測定物３には0Vが印加されるた
め、被測定物３の測定端子が、比較的低抵抗で被
測定物の電源に接続されているような場合、非常
に大きな電流が被測定物に流れることになり、ま
たこの大きな電流に対して回路の応答が追従でき
ないような場合、過渡的に異常電圧が被測定物に
印加されることになり、結局被測定物が破壊され
てしまうことになる。 However, in the conventional circuit, switch 4
At the moment when and 5 are closed, the input voltage at terminal 6 is
Since 0V is applied to the device under test 3, if the measurement terminal of the device under test 3 is connected to the power source of the device under test with a relatively low resistance, a very large current will be applied to the device under test 3. If the circuit response is unable to follow this large current, a transient abnormal voltage will be applied to the device under test, which may eventually destroy the device. It will end up being put away.
本発明は前記欠点を改良した試験装置を提供す
ることを目的としたものである。 The object of the present invention is to provide a test device that improves the above-mentioned drawbacks.
以下本発明について図面を参照しながら詳細に
説明する。第２図は本発明の一実施例を示すブロ
ツク図である。同図において、１，７は演算増幅
器、２は演算増幅器によつて構成される電圧フオ
ロア、３は被測定物、４，５はスイツチ、８は半
導体スイツチを示す。動作を説明すれば以下のよ
うになる。所定の電圧Eiを端子６に加え、半導
体スイツチ８を閉じ（オンし）、スイツチ５を閉
じると電圧フオロア２の出力電圧は被測定物３の
測定端子の出力電圧Exとなり、この電圧Exと演
算増幅器１の出力電圧の差電圧が演算増幅器７に
より増幅されて抵抗R4を介して演算増幅器１に
入力に帰還されることにより、演算増幅器１の出
力電圧は被測定物の出力電圧Exと等しくなる。
次いで、スイツチ４を閉じると演算増幅器１の出
力電圧は被測定物３の出力電圧と等しいので、抵
抗R1には電流が流れない。次いで半導体スイツ
チ８を開く（オフする）と、端子６の入力電圧
Eiに対し、抵抗値R2，R3によつて決まる電圧Eo
が被測定物３に印加されることになり、そこで抵
抗R1に流れる電流による電圧降下を測定すれ
ば、被測定物３に流れる電流が求まる。 The present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, 1 and 7 are operational amplifiers, 2 is a voltage follower constituted by the operational amplifier, 3 is an object to be measured, 4 and 5 are switches, and 8 is a semiconductor switch. The operation is explained as follows. When a predetermined voltage Ei is applied to the terminal 6, the semiconductor switch 8 is closed (turned on), and the switch 5 is closed, the output voltage of the voltage follower 2 becomes the output voltage Ex of the measurement terminal of the device under test 3, and is calculated with this voltage Ex. The differential voltage between the output voltages of the amplifier 1 is amplified by the operational amplifier 7 and fed back to the input of the operational amplifier 1 via the resistor R4 , so that the output voltage of the operational amplifier 1 is equal to the output voltage Ex of the object under test. Become.
Next, when the switch 4 is closed, the output voltage of the operational amplifier 1 becomes equal to the output voltage of the device under test 3, so no current flows through the resistor R1 . Next, when semiconductor switch 8 is opened (turned off), the input voltage at terminal 6
For Ei, the voltage Eo determined by the resistance values R 2 and R 3
is applied to the object under test 3, and by measuring the voltage drop due to the current flowing through the resistor R1 , the current flowing through the object under test 3 can be determined.
以上説明したように被測定物には被測定物の出
力電圧でもつて、すなわち電流の流れない状態で
接続された後、所定の電圧が印加されるので、瞬
間的に異常電流が被測定物に流れることもなく、
また異常電圧が加わることもなく安定な電流測定
が可能となる。 As explained above, after the device under test is connected with the output voltage of the device under test, that is, with no current flowing, a predetermined voltage is applied, so an abnormal current momentarily flows into the device under test. without flowing,
Furthermore, stable current measurement is possible without applying abnormal voltage.
本発明によれば被測定物に電圧を印加し電流を
測定するにあたつて、被測定物に害を与えること
もなく、まして破壊することもなく安定な測定が
可能となり、その効果は著しい。 According to the present invention, when applying voltage to an object to be measured and measuring current, it is possible to perform stable measurement without harming the object to be measured, much less destroying it, and the effect is remarkable. .
第１図は従来の電圧印加電流測定回路を示すブ
ロツク図、第２図は本発明の一実施例を示すブロ
ツク図である。
図において、１…演算増幅器、２…演算増幅器
によつて構成される電圧フオロア、３…被測定
物、４，５…スイツチ、６…入力端子、７…演算
増幅器、８…半導体スイツチ。
FIG. 1 is a block diagram showing a conventional voltage applied current measuring circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1... operational amplifier, 2... voltage follower constituted by an operational amplifier, 3... object to be measured, 4, 5... switch, 6... input terminal, 7... operational amplifier, 8... semiconductor switch.
Claims (1)
定回路を備えた試験装置において、該被測定物に
接続された第１のスイツチが、任意に設定された
抵抗を介して第１の増幅器の出力に接続され、か
つ該被測定物に接続された第２のスイツチが第２
の増幅器の入力に接続されており、先に前記第２
のスイツチを閉じ、該被測定物の電位を前記第２
の増幅器によつて検出し、前記第１の増幅器の出
力電圧と前記第２の増幅器の出力電圧の差電圧を
第３の増幅器を通して、前記第１の増幅器の入力
に帰還することにより、前記第１の増幅器の出力
電圧を前記被測定物の電位と同電位にする手段
と、前記第１のスイツチを閉じ、次いで前記第３
の増幅器による前記第１の増幅器の入力への帰還
を切り離すことにより、所定の電圧を該被測定物
に印加し電流を検出する手段とを含むことを特徴
とする試験装置。1. In a test device equipped with a voltage applied current measurement circuit for testing a device under test, a first switch connected to the device under test controls a first amplifier via an arbitrarily set resistance. a second switch connected to the output and connected to the device under test;
is connected to the input of the second amplifier.
The second switch is closed, and the potential of the object to be measured is changed to the second one.
The voltage difference between the output voltage of the first amplifier and the output voltage of the second amplifier is fed back to the input of the first amplifier through a third amplifier. means for making the output voltage of the first amplifier the same potential as the potential of the object to be measured; closing the first switch; and then closing the third switch;
1. A test apparatus comprising means for applying a predetermined voltage to the object under test and detecting a current by cutting off feedback from the amplifier to the input of the first amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15615479A JPS5679267A (en) | 1979-11-30 | 1979-11-30 | Tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15615479A JPS5679267A (en) | 1979-11-30 | 1979-11-30 | Tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5679267A JPS5679267A (en) | 1981-06-29 |
| JPS6236183B2 true JPS6236183B2 (en) | 1987-08-05 |
Family
ID=15621522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15615479A Granted JPS5679267A (en) | 1979-11-30 | 1979-11-30 | Tester |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5679267A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000310672A (en) * | 1999-04-28 | 2000-11-07 | Fujitsu Ltd | Semiconductor device |
-
1979
- 1979-11-30 JP JP15615479A patent/JPS5679267A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5679267A (en) | 1981-06-29 |
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