JPS6235700B2 - - Google Patents
Info
- Publication number
- JPS6235700B2 JPS6235700B2 JP18200182A JP18200182A JPS6235700B2 JP S6235700 B2 JPS6235700 B2 JP S6235700B2 JP 18200182 A JP18200182 A JP 18200182A JP 18200182 A JP18200182 A JP 18200182A JP S6235700 B2 JPS6235700 B2 JP S6235700B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- input
- execution control
- history
- arithmetic processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 claims description 31
- 238000013500 data storage Methods 0.000 claims description 10
- 238000004088 simulation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 230000001419 dependent effect Effects 0.000 claims description 3
- 230000015654 memory Effects 0.000 description 27
- 238000010586 diagram Methods 0.000 description 16
- 238000004364 calculation method Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009365 direct transmission Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57182001A JPS5971554A (ja) | 1982-10-15 | 1982-10-15 | デイジタル回路シミユレ−シヨン装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57182001A JPS5971554A (ja) | 1982-10-15 | 1982-10-15 | デイジタル回路シミユレ−シヨン装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5971554A JPS5971554A (ja) | 1984-04-23 |
JPS6235700B2 true JPS6235700B2 (de) | 1987-08-03 |
Family
ID=16110582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57182001A Granted JPS5971554A (ja) | 1982-10-15 | 1982-10-15 | デイジタル回路シミユレ−シヨン装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5971554A (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63316140A (ja) * | 1987-06-18 | 1988-12-23 | Matsushita Electric Ind Co Ltd | 論理シミュレ−ション装置 |
-
1982
- 1982-10-15 JP JP57182001A patent/JPS5971554A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5971554A (ja) | 1984-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4787061A (en) | Dual delay mode pipelined logic simulator | |
EP0701713B1 (de) | Feldprogrammierbare logische vorrichtung mit dynamischer verbindungsanordnung an einen dynamischen logischen kern | |
EP0054243A2 (de) | Speichersteuervorrichtung | |
JPH0122652B2 (de) | ||
JP2000516418A (ja) | 再構成可能な演算システム | |
US5832251A (en) | Emulation device | |
US4584642A (en) | Logic simulation apparatus | |
JPH05205005A (ja) | ロジック・シミュレーション・マシン用ホスト・インタフェース | |
JPS58501560A (ja) | マイクロプロセツサ | |
US20140089548A1 (en) | Systems, Methods, and Articles of Manufacture To Stream Data | |
US7480611B2 (en) | Method and apparatus to increase the usable memory capacity of a logic simulation hardware emulator/accelerator | |
US7827023B2 (en) | Method and apparatus for increasing the efficiency of an emulation engine | |
JPS6235700B2 (de) | ||
US7636817B1 (en) | Methods and apparatus for allowing simultaneous memory accesses in a programmable chip system | |
JP3431025B2 (ja) | データ転送システム | |
US5603023A (en) | Processor circuit for heapsorting | |
JP3212709B2 (ja) | ロジックシミュレーション装置 | |
US5734900A (en) | Information handling system including efficient power on initialization | |
JPS6235699B2 (de) | ||
US6510480B1 (en) | Data transfer circuit and data processing method using data transfer circuit for handling interruption processing | |
US7809861B1 (en) | System memory map decoder logic | |
US8966124B1 (en) | Systems, methods, and articles of manufacture to stream data | |
KR920009450B1 (ko) | 컴퓨터의 버스 싸이클 콘트롤러 | |
JPH05266124A (ja) | 論理回路シミュレーション用回路素子ライブラリの作成方法 | |
JP3357693B2 (ja) | エミュレーションメモリのマッピング回路及びエミュレーションシステム |