JPS6235576A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a D.FET having target characteristics by ion implantation into a partial region of a current passage of the D.FET larger than the desired drain current value to reduce the drain current value of the D.FET. CONSTITUTION:A GaAs substrate 1 having D.FET of a drain current value larger than the desired drain current value, a resist 6 is coated on the substrate 1, and a part of the resist 6 on an N-type conductive layer 2 is partly removed to form a hole 7. Then, 12C is ion implanted to a part of the layer 2 under the conditions of 160keV of implanting energy and 2.5X10<11>does/cm<2> from the hole 7, part of the layer 2 is increased in the resistance, and the resist 6 is removed. According to this method, only the drain current can be reduced at the ratio to the gate width of the hole 7 without varying other FET characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for adjusting the drain current value of a normally-on field effect transistor (hereinafter referred to as FET) formed on a compound semiconductor substrate. It is something.

(Prior Art) A conventional FET manufacturing method is described in the literature, Institute of Electronics and Communication Engineers Technical Research Report ED81-49. p, 85. -92. As described in this document, logic circuits such as inverters generally use normally-on type deregression mode FETs (hereinafter referred to as D-F'ETs).
Marioff type enhancement mode FET (hereinafter referred to as E
-FET) in a logic circuit.
-FET has its date electrode and source electrode connected and is used as a constant current source.

Here, the saturated drain current (hereinafter referred to as ID) is the threshold voltage (hereinafter referred to as vT) and ID = K (V, -VT),
(■o:)f'-t voltage, K: proportionality constant) Therefore, when a D-FET is used as a constant current source in a logic circuit, =: The relationship KVT2 holds true.

-Here, K is a proportionality constant determined by dart length, dart width, electron mobility, channel thickness, etc., and is usually constant, so in the FET manufacturing process, ID is controlled by controlling vT.

(Problems to be Solved by the Invention) However, even with the method described above, variations in the characteristics of compound semiconductor substrates and variations in conditions in the manufacturing process are unavoidable, so it is difficult to maintain circuit design standards for all substrates. It is difficult to form V with good reproducibility, and if the ID of the load D-FET becomes large, the current consumption becomes large and the noise margin becomes small, which may prevent logic operation. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the drain current value of a D-FET and provide a D-FET with desired characteristics.

(Means for Solving the Problem) The present invention provides a plurality of Ds on each of a plurality of compound semiconductor substrates.
-FET is formed, the drain current value of this D-F'ET is measured, and a substrate having a D-FET with a drain current value larger than a desired drain current value is selected. - A high resistance region is formed by implanting ions into a part of the current path of the FET.

(Function) As explained above, in the present invention, by implanting ions into a part of the current path of the D-FET, a high resistance region is formed and the drain current value is adjusted. A high resistance region can be formed without the occurrence of defects and annealing. In this high resistance region, the drain current can be reduced by the ratio of the high resistance region of the current path. Therefore, D −FE
In the step of forming T, if the drain current value is small, the present invention is used to form a D-FET with the desired characteristics.
can be formed.

(Example) FIGS. 1(a) and 1(b) are sectional views of an element for detailed explanation of the present invention. Hereinafter, embodiments will be described with reference to the drawings.

As shown in Figure 1(a), first, Ga
An n-type conductive layer 2 which is a current path formed by implanting donor ions and annealing /I/ on an As substrate 1, a dirt electrode 3 which forms a Schottky barrier, and a source electrode 4 and a drain electrode 5 which form ohmic contact are formed. Especially p D-F
Form ET. Similarly, a plurality of D-FETs are formed on other substrates (not shown).

Next, the drain current value of a predetermined D-FET formed on the GaAs substrate 1 is measured using a globe needle or the like.
A GaAs substrate 1 having T is selected.

Next, as shown in FIG. 1(b), a resist 6 is deposited on the surface of the selected GaAs substrate 1, and a portion of the resist 6 on the n-type conductive layer 2 is removed using lithography to form an open lower layer. Form. Next, from the open lower part, 12C was implanted at an energy of 160 keV and a dosage of 2.5 x 1011 doe.
Ions are implanted into a part of the n-type conductive layer 2 under conditions of s/2, and due to the effects of implanted ions damage, etc.
A part of the mold conductive layer 2 is made to have a high resistance, and the resist 6 is removed.

As described above, according to the embodiment of the present invention, only the drain current can be reduced by the ratio to the open lower dirt width without changing other FET characteristics.

In the embodiment of the present invention, the GaAs substrate 1 is used as the substrate, but other compound semiconductor substrates may be used, and although C is used as the implanted ion, other implanted ions may be used. . Further, the ion implantation conditions may be such that the implantation energy is sufficient to penetrate the n-type conductive layer 2, for example, the implantation energy is approximately 20 keV or more, and the implantation amount is 1.
011does High resistance can be achieved if it is 7cm2 or more,
The conditions are not strict.

(Effects of the Invention) As described above in detail, according to the present invention, D-FE
After forming the T, high resistance is applied to a part of the current path without deteriorating the D-FET characteristics other than the drain current value.
It becomes possible to reduce the drain current by the ratio of the high resistance region to the current path. Therefore, D
- In the FET formation step, even if the drain current value is large, the present invention can be used to form an FET with desired characteristics.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are plan views of elements for detailed explanation of the present invention. 1...GaAs substrate, 2...n-type conductive layer, 3...gate electrode, 4...source electrode, 5...drain electrode, 6...resist, 7...opening patent Applicant: Oki Electric Industry Co., Ltd. (Invention System) Figure 1

Claims (1)

[Claims] A step of forming a plurality of normally-on field effect transistors on each of a plurality of compound semiconductor substrates, and measuring a drain current value of the field effect transistor to determine whether the drain current value is larger than a desired drain current value. The method comprises the steps of: selecting the substrate having a field effect transistor; and forming a high resistance region by implanting ions into a partial region of the current path of the normally-on field effect transistor in the selected substrate. A method for manufacturing a semiconductor device, characterized in that: