JPS6235315B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to an automatic frequency adjustment device used in color television receivers, etc., and in particular, it is equipped with a frequency adjustment function using a phase lock loop (PLL) and a frequency adjustment function using automatic frequency tuning (AFT). It is related to the device.

Some television receivers use a PLL frequency synthesizer system. The television receiver shown in Figure 1 has two reception methods: a PLL frequency synthesizer method, and an automatic tuning reception method using an AFT loop once a signal is received in PLL mode (if an intermediate frequency signal is received). This is an example of a television receiver that has two modes: AFT mode. 1 is an antenna, and the output of this antenna is introduced into a high frequency amplification circuit 2. The output of this amplifier circuit 2 is applied to a mixing circuit 3, mixed with the output of the voltage controlled oscillation circuit 11, and converted into an intermediate frequency signal. This signal is amplified by the intermediate frequency amplification circuit 4 and applied to the audio intermediate frequency amplification circuit 6 and the video intermediate frequency amplification circuit 5. The output of the intermediate frequency amplifier circuit 4 is applied to the AFT circuit 8. This circuit 8 detects the deviation of the intermediate frequency signal by FM detection, and applies a detection voltage to the AFT superimposition circuit 9. This AFT superimposition circuit 9
Now, we will create an automatic frequency tuning voltage, which will create a voltage according to the above-mentioned deviation, and add this to the control terminal of the voltage-controlled oscillation circuit 11 to control the oscillation frequency so that the receiver can always receive stable reception. maintain the condition.

When a channel is specified by the keyboard switch device 16, the specified data is applied to the signal conversion circuit 12 via the shift register 14.
As a result, data corresponding to the designated channel is set in the variable frequency divider 13 as a frequency division ratio. This variable frequency divider 13 includes the voltage controlled oscillation circuit 11
The frequency of the output is frequency-converted to a video intermediate frequency, and the frequency-divided output is applied to the phase comparator 18. Since the output of the reference oscillator 25 is also applied to the phase comparator 18, an output voltage corresponding to the phase difference between the two signals can be obtained. This phase difference voltage passes through a low-pass filter 19 and then a gate circuit 20.
added to the control end of the voltage controlled oscillation circuit 11.
A PLL loop is formed. This oscillation circuit 1
The oscillation frequency of 1 is varied according to the frequency division ratio,
The specified channel can now be received.

The receiving frequency range due to the above PLL operation is narrow, and proper receiving operation may not be obtained. As described above, when the PLL operation cannot perform the optimal channel selection operation, it is common to obtain a stable channel selection operation by coexisting the AFT operation in addition to the PLL operation.

Therefore, when selecting a channel, PLL operation and
The desired channel selection operation is performed by switching between AFT operation and AFT operation. That is, when the switch device 24 switches to the PLL mode, the output of the NAND circuit 21 for determining mode switching becomes high level. As a result, the gate of the PLL gate circuit 20 is opened,
PLL operation becomes possible. In this case, the output high level of the NAND circuit 21 is also applied to the AFT defect circuit 10, inhibiting the AFT loop so that it does not operate.

By the above operation, the PLL frequency synthesizer reception method can be brought into a reception state of a desired channel.

However, in recent years, oscillator devices for video games and the like have been developed, and users sometimes play games while receiving the oscillators on a television receiver and watching the game screen. The video carrier frequencies from these devices are different from those from general broadcast stations and may have large frequency fluctuations. In such a case, since good image quality cannot be obtained using only PLL mode, a reception method using automatic tuning using an AFT loop may be considered.

If the AFT loop is also to be used in this way, the switch device 24 is switched to the AFT mode. When this switch device is switched, one input of the NAND circuit 21 is always at a high level.

Therefore, the output of the NAND circuit 21 is controlled by the high or low level of the output of the signal detection circuit 7 that determines the presence or absence of a video signal, and the PLL or AFT mode can be switched.
The signal detection circuit 7 uses horizontal flyback pulses to detect the presence or absence of a video carrier. This signal detection circuit 7 derives a detection voltage when both comparison signals are present, and this voltage signal is applied to the input terminal of the NAND circuit 21 via the delay circuit 23. Therefore, when the detection voltage of the signal detection circuit 7 is present (when a video signal is detected), both input signals of the NAND circuit 21 are at a low level, so that the gate circuit 20 is connected to the low-pass filter 19. While blocking the output of PLL and inhibiting PLL operation, the AFT loop becomes operational.

Now, if the switch device 24 is switched to the AFT mode and the signal detection circuit 7 detects the horizontal flyback pulse and the horizontal synchronization signal, the AFT loop will continue to operate. However, as described above, variations in oscillation frequency may occur in video games and the like. In such a case, the signal detection circuit 7 does not detect the periodic signal in the video signal, and the output of the NAND circuit 21 becomes high level. Since this state is equivalent to the state of switching to PLL mode, a PLL synthesizer reception operation is performed. Therefore, even if the AFT mode is set, if the frequency fluctuation of the video carrier of the signal is large, the device may not operate in the AFT mode.

If you switch to AFT mode like this,
First, a channel selection operation corresponding to the channel specified on the keyboard is performed using the PLL synthesizer method, and then, when the reception state is reached and a voltage is obtained from the signal detection circuit 7, the operation is switched to the AFT loop operation and automatic tuning is performed. However, when the tuning shifts and the output of the signal detection circuit 7 disappears, the state switches to the PLL system tuning adjustment state, and when the reception state returns, the AFT loop cannot operate again, and the PLL has a narrow frequency pull-in range.
Since only motion is obtained, the video carrier frequency cannot be pulled in.

By the way, the signal detection circuit 7 is configured as shown in FIG. 2, and charges the capacitor C3 and turns on _{the transistor Q3 only} during the period when the horizontal flyback pulse E _P and the horizontal synchronizing signal H _P are in phase. By doing so, the presence or absence of a synchronization signal is detected, and the presence or absence of a video signal is detected. That is, in FIG.
1 and 32 are applied with a horizontal flyback pulse F _P and a horizontal synchronization pulse H _P as shown in FIGS. 3a and 3b, respectively. If the horizontal flyback pulse F _P and the horizontal synchronization pulse H _P are in phase, the transistor Q ₁ ,
Q ₂ becomes conductive and capacitor C ₃ is charged as shown in Figure 3c, which causes the transistor to
The base potential of Q ₃ is set depending on the presence or absence of a synchronization signal. In other words, there is a synchronization signal and each pulse H _P ,
If F _P is in phase, transistor Q ₃ is on as shown in FIG. 3d. (Fig. 3c shows the base potential of the transistor _Q3 , and Fig. 3d shows the emitter voltage of the transistor _Q3 .

If we pay attention to the synchronization signal waveform here, it may change as shown in signals 4a, 4b, and 4c shown in FIG. 4. In other words, when the reception center frequency determined by reception in PLL mode and the input frequency from the antenna match, the synchronization signal waveform will be as shown in 4a in Figure 4, but if the input frequency deviates to the higher side. Due to the characteristics of the , tuner, and video intermediate frequency circuit, the high-frequency components of the signal are eliminated, resulting in a synchronizing signal waveform like 4c shown in FIG. Further, when the input frequency shifts to a lower side, the low-frequency component of the signal disappears, resulting in a synchronization signal waveform as shown in 4b in FIG. 4, which becomes a noise signal. Therefore, if the frequency shifts to the higher side, the signal detection circuit that detects the presence or absence of the synchronization signal becomes inoperable, resulting in a narrow frequency pull-in range.
It is no longer possible to switch from PLL operation to AFT loop operation with a wide frequency pull-in range. In other words, A.F.T.
The loop pull-in range is determined by the operating range of the signal detection circuit 7. Normally, fluctuations in the transmission frequency of video games, CATV, etc. are required to be around ±1MHz of the center frequency during PLL, so if the video carrier frequency of the transmission signal shifts, the pull-in operation will not be performed and it will correspond normally. I can't select a station.

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide an automatic frequency adjustment device capable of expanding the AFT pull-in range by substantially expanding the pull-in range of the video carrier in AFT mode. It is something.

Embodiments of the present invention will be described below with reference to FIGS. 5 to 8. That is, in addition to the configuration shown in FIG. 1, the present invention is provided with an AFT signal detection circuit 29 shown in FIG. 5, and the signal detection circuit 7 is controlled by the output of this circuit. ,
Components common to those in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted. That is, as shown in Figure 5,
The AFT signal detection circuit 29 detects the presence or absence of a signal present in the AFT superimposition circuit 9, and uses as input information a signal indicating the presence or absence of a video signal which is the output of the NAND circuit 21.
It controls the operation timing of the

A specific example of the above AFT signal detection circuit 29 and its peripheral circuits will be explained with reference to FIG. That is, 30 is an input terminal to which the output of the NAND circuit 21 is applied via an inverter. This input terminal is connected to the base of a transistor 33 via a resistor 31. The base of this transistor 33 is connected to the reference potential end via the resistor 32, and the emitter is also connected to the reference potential end. Further, the collector of this transistor 33 is connected to a power supply terminal 35 via a resistor 34, and a transistor 36
connected to the base of. This transistor 3
Emitter 6 is connected to the reference potential terminal, and resistor 3
7 and 38. The resistor 37
The other end of the resistor 38 is connected to the emitter of the transistor 40, and the other end of the resistor 38 is connected to the emitter of the transistor 47. the transistor 40
The emitter is connected to the power supply terminal 65 via the resistor 39, and the collector is connected to the collector of the transistor 41. Further, the transistor 40
The base of is connected to a power supply end 65 through a series circuit of a reverse diode 43 and a resistor 45, and is also connected to the collector of a transistor 56 through a resistor 56. The emitter of the transistor 41 is connected to a reference potential terminal via a resistor 42, the base is connected to the base of a transistor 48, and the collector is connected to the DC voltage output terminal of the gate circuit 20. The emitter of the transistor 48 is connected to a reference potential terminal via a resistor 49, and the collector is connected to the base of the self-transistor and to the collector of the transistor 47. The emitter of this transistor 47 is a resistor 46
The base is connected to the power supply terminal 65 through a reverse diode 50 and a resistor 51.
5, and also connected to one end of the resistor 54 and the base of the transistor 66. The other end of the resistor 54 is connected to the collector of a transistor 55. The emitter of this transistor 55 is connected to the emitter of a transistor 56 and also to a reference potential terminal via a resistor 53. Further, the bases of the transistors 55 and 56 are connected to the cathodes of diodes 57 and 58, respectively, and are connected to the resistors 5 and 56, respectively.
9 and 60 to the AFT voltage output terminal. The anodes of the diodes 57 and 58 are commonly connected to the common emitters of the transistors 55 and 56. Note that the AFT voltage output terminals are connected to a reference potential terminal via capacitors 61 and 62, respectively.

The emitter of the transistor 66 is connected to the power supply terminal 65 via the resistor 64, and the collector is connected to the resistor 67.
It is connected to the base of the transistor 71, and further connected to the collector of the transistor 68. This transistor 68
The emitter is connected to the reference potential terminal, and the base is connected to the reference potential terminal via a resistor 69 and to the input terminal 30 via a resistor 70.

The emitter of the transistor 71 is connected to a reference potential terminal, and the collector is connected to one end of a resistor 72. The other end of the resistor 72 is connected to the capacitor 7.
3 to a reference potential terminal, a resistor 74 to a power supply terminal 81, and a cathode of a diode 75. The anode of this diode 75 is connected to a power supply terminal 81 via a resistor 76, and also to the collector of a transistor 82 and one end of a resistor 77. The other end of this resistor 77 is connected to the base of a transistor 79 and also to a power supply end 81 via a capacitor 78 . The emitter of the transistor 79 is connected to a power supply terminal 81, and the collector is connected to a reference potential terminal via a resistor 80.
It is led out to the signal detection output terminal.

The emitter of the transistor 82 is connected to the collector of a transistor 86, and the base is connected to a resistor 83.
is connected to the reference potential terminal via the resistor 8.
4 to the flyback pulse introduction end 85. The emitter of the transistor 86 is connected to the reference potential terminal via a resistor 87, and the base is connected to the reference potential terminal via a resistor 88 and a capacitor 89 in parallel, and horizontally via a resistor 90 and a capacitor 91 in series. Synchronous signal input terminal 9
Connected to 2.

Next, the gate circuit 20 will be explained. This circuit is, for example, a field effect transistor (hereinafter referred to as a field effect transistor).
This FET9 is composed of 95 etc.
The gate of transistor 5 is connected to the power supply terminal via a resistor 96 and to the collector of a transistor 97. A resistor 98 is connected between the base and emitter of this transistor 97, and the emitter is connected to the power source 9.
9 to the reference potential terminal, and its base is connected to the input terminal 30 via a resistor 100.

The present invention is constructed as described above, and its operation will be explained next.

The operation achieved by the present invention substantially expands the AFT pull-in range and substantially eliminates the frequency deviation of the video carrier relative to the reference frequency in the reference oscillator 25 even when switching PLL modes. To stably pull in a video carrier within a frequency range even when the weather changes, and to stably receive a video signal.

In general, the frequency pull-in characteristic of the video carrier due to AFT operation is that when the IF frequency shifts to a higher frequency, it is artificially pulled into the audio carrier.
The pull-in range on the high frequency side of the IF frequency is narrowed. This is the reason why conventional equipment cannot perform AFT.
Even when operated in this mode, there was a problem in that a normal video signal could not be obtained if there was a shift in the video carrier frequency such that the IF frequency shifted to a higher frequency.

To solve this problem, the present invention uses the AFT pull-in range as the detection range for the presence or absence of a synchronization signal.
The pull-in range of the video carrier is expanded to a frequency range that is substantially the sum of the frequency range in which the AFT signal can be detected by the AFT signal detection circuit.

This operation of expanding the pull-in range of the video carrier can be obtained substantially in both the PLL mode and the AFT mode.

That is, even if the voltage-controlled oscillation circuit 11 constituting the local oscillator is in the PLL mode, which is locked to a predetermined narrow frequency range, if the frequency deviates from the frequency pull-in range of the mode, it is essentially forced to shift to the AFT mode. As a result, the pull-in frequency range is expanded regardless of the frequency deviation of the video carrier.

First, in FIGS. 5 and 6, when the switch device 24 is set to PLL mode, the reception state of the specified channel can be determined by specifying a channel from the keyboard device 16, as explained in FIG. Become. In addition, in the PLL mode, the AFT defect circuit 10 operates to prohibit superimposition of the tuning voltage by the AFT superimposition circuit 9 on the tuning voltage. In the PLL mode, the switch device 24 is at a low level, and the output of the NAND circuit 21 is at a high level. That is, in PLL mode, the level of terminal 30 is initially at low level due to the inverter, and the AFT
The transistor 33 of the defective circuit 10 is turned off and the transistor 36 is turned on. When the transistor 36 of the AFT defect circuit 10 is turned on, the transistors 41 and 48 of the AFT superimposition circuit 9 forming the current mirror circuit are turned off, and the current flowing through these transistors due to the operation of the AFT superimposition circuit 9 flows to the transistor 36. . Therefore, the AFT voltage from the collector of the transistor 41 of the transistor AFT superimposing circuit 9 is not supplied to the voltage controlled oscillation circuit 11, and the AFT defect circuit 10 performs the AFT defect operation.

In this case, a PLL loop shown by a dashed line in Fig. 6 is formed, and the video carrier of the received video signal is
An automatic frequency adjustment operation is performed to pull in the output voltage of the phase comparator 18 at the pull-in center frequency ₀ of the PLL in accordance with the terminal voltage of the capacitor 101, which serves as a voltage hold circuit.

In the above PLL operation, if the frequency shift of the carrier of the received video signal becomes large with respect to the pull-in center frequency ₀ of the PLL loop, the video signal cannot be received normally.

However, according to the present invention, by the operation described below, the pull-in range of the video carrier is substantially expanded even in the PLL mode, and when the carrier frequency shift of the received video signal exceeds the PLL pull-in range, The video signal can be received normally even if

This operation will be explained with reference to the AFT pull-in characteristic shown in FIG.

In Fig. 7, a shows the frequency characteristics of a signal detection circuit that detects the presence or absence of a video carrier by determining _the presence or absence of a horizontal synchronization signal. The presence or absence of a carrier is detected. Further, FIG. 1B shows the output frequency characteristics of the AFT circuit 8, which is constituted by a so-called peak differential detection circuit that performs differential peak detection on, for example, a video intermediate frequency signal.
As you can see in the figure, AFT-1 is a differential output,
Both AFT-2 center frequencies are around ₀ (±
0.5 MHz), the output level becomes a predetermined DC level, and signals of positive and negative levels with respect to the DC level are output in a band of -3 to -0.5 MHz and a band around +0.5 MHz to 1.5 MHz. Here, the reason why the characteristics are made gentle in the high frequency region with respect to the video carrier frequency ₀ , which is the center frequency, is that there is an audio carrier in the high frequency region with respect to the above ₀ , so that it is not mistakenly drawn in as a video carrier. This is to ensure that. Next, c in the same figure shows the AFT signal detection circuit 29.
It is a characteristic diagram showing the frequency characteristics of the AFT signal detection circuit 29 that detects the presence or absence of a signal, and shows the frequency characteristics in which the high frequency range is expanded with respect to the center frequency ₀ shown in figure c, and the frequency characteristic shown in figure a. The operation of the AFT signal detection circuit 29 makes it possible to pull in the video carrier within the expanded frequency characteristic shown in d of the same figure.

In this way, in the PLL mode, the gate circuit 20
The transistor 97 is turned off, the FET 95 is turned on, and the oscillation frequency of the voltage-controlled oscillation circuit 11 is controlled by the output of the phase comparator 18. As a result, automatic frequency adjustment operation is performed by PLL operation. In this case, since the video carrier has been detected, the terminal 92 is supplied with a separated positive pulse (the third pulse).
b), the transistor 79 is in the on state. Therefore, the collector of the output transistor 79 of the signal detection circuit 7 maintains a high level. Further, the transistors 82 and 86 are turned on at the timing of a synchronization signal synchronized with the flyback pulse, and the pulse generated thereby (FIG. 3b) is repeatedly charged and discharged between the capacitor 78 and the transistor 79. The base voltage has a waveform as shown in FIG. 3c. Therefore, the transistor 79
is always on when a synchronizing signal is detected, and the output of the signal detection circuit 7 is at a high level during the period when the synchronizing signal in the video signal is detected.

The collector voltage of the transistor 82 (FIG. 3c) of the signal detection circuit 7 is also applied to the diode 75, which remains off when the synchronization signal is detected.

In other words, during PLL operation, the video carrier is set to ₀ at the reference frequency only to the extent that the synchronization signal is detected.
When there is no frequency deviation with respect to, the potential on the collector side of the transistor 79 of the signal detection circuit,
Both collector side potentials of the transistor 36 are at a high level.

Here, looking at the operation of the AFT signal detection circuit 29 during PLL operation, the voltage level of the terminal 30 is set to low level, and the AFT
Since the transistor 36 of the defect circuit 10 is turned on, the transistor 40 of the AFT superimposition circuit 9,
47 is off, and transistors 66, 68, 71
Both remain off. This state is maintained as long as the frequency deviation of the received video carrier is approximately ±0.5 MHz, since the output of the AFT circuit 8 is at a low level.

That is, as long as the frequency deviation of the video carrier remains within a range in which a synchronizing signal can be detected, the above-mentioned state is maintained, and automatic frequency adjustment by PLL operation is performed in PLL mode.

Depending on the setting of the resistance values of the resistors 37 and 38, during PLL operation, when the frequency deviation of the arriving signal is large and the output level of the AFT circuit 8 becomes large, the transistors 40, 47, and 66 are turned on and the AFT is activated. It can be made to perform an action.

Next, the operation of AFT mode will be explained.

When the frequency deviation of the video carrier is relatively large, such as in video games or CATV broadcasting, AFT
mode.

In the AFT mode, the switch device 24 is set to a high level. In such an AFT mode, the frequency shift of the received video carrier is relatively large, so it generally exceeds the range that can be pulled in in the PLL mode.

For this reason, it is desirable to substantially expand the frequency pull-in range. In order to widen this pull-in frequency range, the function of determining the presence or absence of a video carrier by the signal detection circuit 7, which has the function of determining the presence or absence of a synchronization signal, is utilized.

In addition, since the frequency deviation in AFT mode is relatively large, it is necessary to operate in PLL mode at the initial stage of AFT operation, and then perform AFT operation in order to perform automatic frequency adjustment stably. It is necessary to satisfy both this requirement and the expansion of the pull-in frequency range.

The operation in the AFT mode, which operates to satisfy such conditions, will be explained with reference to FIG. 8.

In FIG. 8, a shows the switching state of the switch device 24; in the PLL mode, the low level;
In AFT mode, it is set to high level. Figure b shows the presence or absence of received broadcast waves. Further, FIG. 3C shows the output level of the NAND circuit 21, which shows that even if the switch device 24 is shifted from the PLL mode to the AFT mode, it will be delayed by the operation of the delay circuit 23. In addition, d in the same figure shows the output of the signal detection circuit 7 which has a function of detecting the presence or absence of a synchronization signal, and e in the same figure shows the output of the AFT signal detection circuit 2.
9 shows the output status.

Now, switch the switch device 24 from PLL mode.
Suppose you switch to AFT mode. Such switching is performed when the received signal has a frequency deviation that exceeds the pull-in range of the received video signal frequency in the PLL mode.

When the switch device 24 is set to a high level, the output level of the NAND circuit 21 changes in accordance with the output of the signal detection circuit 7 obtained via the delay circuit 23. However, due to the delay operation of the delay circuit 23 and the operation of the AFT signal detection circuit 29, which will be described later, the switch device 24 is switched off at time _t0 .
Even when switching to the AFT mode, the output state of the NAND circuit 21 changes at time _td . The operation of holding the output of the NAND circuit 21 for a predetermined period of time regardless of the switching of the switch device 24 is related to the expansion of the reception frequency pull-in frequency range as shown in the frequency characteristics shown in FIG. 7d.

Switching to AFT mode is based on the assumption that no received video signal is obtained, and in this case, the signal detection circuit 7 does not receive a synchronizing signal, so the output level of the signal detection circuit 7 is at a low level. . In other words, the output level of the signal detection circuit 7 is at a low level immediately before switching to the AFT mode, and therefore the switch device 24 is switched to the AFT mode.
When the mode is switched, the NAND circuit 21 maintains a high level.

At this time, the output of the NAND circuit 21 is inverted by the inverter, the transistor 97 of the gate circuit 20 is turned off, the FET 95 is kept turned on, and the PLL loop is maintained.

On the other hand, the transistor 33 of the AFT defect circuit 10 is off, and the transistor 36 is off.
is turned on and the AFT day-to-day state is maintained initially when switching from PLL mode to AFT mode. In this AFT defect state, as described above, the transistor 36 is on, the transistors 41 and 48 forming the current mirror circuit in the AFT superimposition circuit 9 are off, and the transistors 66, 68, and 71 of the AFT signal detection circuit 29 are all turned off. It's off.

Therefore, even when switching from PLL mode to AFT mode, due to the delay operation by the delay circuit 23,
AFT day-to-day operation continues and PLL operation is maintained.

If there is a deviation in the video signal frequency of the received video signal to the extent that it exceeds the frequency pull-in range of the received video signal due to PLL operation, for example, if the video intermediate frequency shifts to the audio carrier side, then the AFT
The output level of the differential outputs AFT-1 and AFT-2 in the circuit 8 becomes large, and the transistor 55 or 56 of the AFT superimposing circuit 9 is turned on. (Note that when these transistors are turned on, the transistor 40 or 47 starts to be turned on, and the flow begins to flow to the transistor 41 or 48 of the AFT superimposing circuit 9.) At this time, the transistor 68 of the AFT signal detection circuit 29 is turned off; Transistors 66, 71
is in the on state, so the signals AFT-1 and AFT-2 are transmitted to the signal detection circuit 7 side via the AFT signal detection circuit 29. Here, the above AFT circuit 8
When the AFT output level exceeds a level of 2V _F (V _F is the PN junction diode voltage and the voltage between the base and emitter of transistors 55 and 56), the output level of the AFT signal detection circuit 29 exceeds the diode 75 of the signal detection circuit 7. Turn on. This diode 75
When turned on, the output of AFT circuit 8 is used.
Due to the operation of the AFT superimposition circuit 9, the output of the AFT signal detection circuit 29 is applied to the signal detection circuit 7. Moreover, if the horizontal synchronization signal is obtained, the signal detection circuit 7
The frequency band characteristics of the signal detection circuit 7, to which a bias voltage is applied to bias the transistors 82 and 86 to detect the presence or absence of a horizontal synchronizing signal in the received video signal, are as shown in FIG. 7d and shown in FIG. 7a. Wider than the band. In other words, if the center frequency of the intermediate frequency of the received video signal shifts to the audio carrier side,
Or, on the contrary, even in the case of deviation, it is possible to stably draw in the video signal. This pull-in frequency expansion operation is performed after the diode 75 of the signal detection circuit 7 is turned on, and then the AFT signal detection circuit 29
continues for the time τ during which it is detected that the AFT signal is above a predetermined level (Fig. 8e).

This operation allows you to switch from PLL mode to AFT.
An operation to expand the frequency pull-in range when switching to the mode is performed.

When the output level of the signal detection circuit 7 becomes high level due to the frequency pull-in range expansion operation by the AFT signal detection circuit 29, the output of the NAND circuit 21 becomes low level, the transistor 97 of the gate circuit 20 is turned on, and the FET 95 is turned on. turns off
The PLL loop is cut off and the mode shifts to AFT mode.
At this time, the transistor 33 of the AFT defect circuit 10 is turned on, and the transistor 36 is turned off.
AFT dayfeet is canceled and AFT operation becomes available.

As a result, when switching from the PLL mode to the AFT mode, the PLL mode operation is maintained for a certain period of time, and the receiving frequency pull-in range is expanded to provide a stable automatic frequency adjustment function.

As described above, according to the automatic frequency adjustment device according to the present invention, a stable automatic frequency adjustment function can be obtained during the transition from PLL mode to AFT mode, and the pull-in frequency band can be expanded.

Note that even in the AFT mode itself, the retraction range can be expanded by the above-described operation.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of a conventional automatic frequency adjustment device, Fig. 2 is a circuit diagram of the signal detection circuit of Fig. 1, and Figs. 3 a to d are shown to explain the operation of the circuit of Fig. 2. 4 is a diagram showing an example of the output waveform of the signal detection circuit, FIG. 5 is a configuration explanatory diagram showing an embodiment of the automatic frequency adjustment device of the present invention, and FIG. 6 is a diagram showing the configuration of an embodiment of the automatic frequency adjustment device of the present invention. FIGS. 7a to 7d are characteristic diagrams showing the characteristics of each block of the inventive device, and FIGS. 8a to 8e are
7 is a signal waveform diagram of each part of the circuit of FIG. 6. FIG. 2...High frequency amplification circuit, 3...Mixing circuit, 4...Intermediate frequency amplification circuit, 7...Signal detection circuit, 8...AFT circuit, 9...AFT superimposition circuit, 10...AFT defective circuit, 11...Voltage controlled oscillation circuit, 20 ...Gate circuit, 24...Switch device, 29...AFT signal detection circuit.

Claims (1)

[Scope of Claims] 1. In an automatic frequency adjustment device that has a function of either PLL mode or AFT mode for received video signals, a switch device that determines in which mode the received video signal is to be operated; With local oscillator output as input,
a frequency mixing circuit that frequency-converts a received signal to an intermediate frequency; a voltage-controlled oscillation circuit that constitutes the local oscillator; and a phase comparator that performs a phase comparison between the output of the voltage-controlled oscillation circuit and the output of a reference oscillator; a voltage hold circuit provided on the output end side of the phase comparator to hold the output voltage of the output of the phase comparator and apply it to the voltage controlled oscillation circuit as a control voltage; the voltage hold circuit and the phase comparator; and
A gate circuit that connects in PLL mode to perform PLL operation, and an AFT that performs AFT detection on the received video signal.
an AFT voltage weight circuit for applying a signal obtained by the AFT circuit to the voltage hold circuit; a signal detection circuit for detecting the presence or absence of the signal in a received video signal; AFT performs a logic operation on the output of the delay circuit provided on the output side and the output of the delay circuit and the output of the switch device, and performs a defect operation on the AFT voltage weight circuit according to the logic value obtained by this logic operation. Dayfeet circuit,
and a logic circuit for controlling the gate circuit, which is controlled by the output of the logic circuit, and when the switch device is switched from the PLL mode to the AFT mode, the AFT circuit output is discriminated and the AFT voltage is applied to the signal detection circuit. is applied to maintain the PLL mode within the delay time of the delay circuit regardless of the mode switching of the output logic value of the logic circuit.
An automatic frequency adjustment device characterized by comprising an AFT signal detection circuit.