JPS6235289U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a timepiece according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the main part of FIG. 1. Figure 3~
FIG. 5 is a time chart showing the operation of the circuit of FIG. 2. FIG. 6 is a sectional view of essential parts of a timepiece according to another embodiment of the present invention. 15, 17... Operation end detection circuit, 18... Memory circuit, 20, 22... Double operation detection circuit, 24, 26
...Gate circuit.

Claims (1)

[Claims for Utility Model Registration] (1) A timepiece having at least two time adjustment switches that can adjust only the corresponding time display digit of the time measured by the counter and the time measured by the counter; For each correction switch,
a double operation detection circuit that detects that another correction switch is operated while the said switch is being operated; an operation completion detection circuit that detects that the operation of said time correction switch is completed; and said double operation. The clock is supplied to the counter by the single operation of the time adjustment switch until the detection circuit detects the double operation and the operation end detection circuit detects that the operation of the other time adjustment switch is completed. 1. A timepiece correction device comprising a gate circuit that supplies a correction signal that is different from the correction signal that is used. (2) Utility Model Registration Claim 1, wherein the counter is constituted by an up-down counter capable of addition and subtraction, and the gate circuit sends an addition correction signal to the up input of the counter when the time correction switch is operated alone. a first gate that supplies
a second supplying a subtraction correction signal to the down input of the counter when the time correction switches are operated simultaneously;
A clock correction device consisting of a gate and a gate. (3) In the scope of the utility model registration claim described in paragraph 1, when the gate circuit simultaneously operates the first gate that supplies a single correction signal to the counter when the time correction switch is operated alone, and the time correction switch. and a second gate circuit for supplying a fast forward correction signal to the counter.