JPH0286276U - - Google Patents

Info

Publication number
JPH0286276U
JPH0286276U JP1988165260U JP16526088U JPH0286276U JP H0286276 U JPH0286276 U JP H0286276U JP 1988165260 U JP1988165260 U JP 1988165260U JP 16526088 U JP16526088 U JP 16526088U JP H0286276 U JPH0286276 U JP H0286276U
Authority
JP
Japan
Prior art keywords
display
channel
display device
volume setting
timer means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988165260U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988165260U priority Critical patent/JPH0286276U/ja
Publication of JPH0286276U publication Critical patent/JPH0286276U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例の要部回路ブロツク図
、第2図は本考案の実施例の処理手順を示すフロ
ーチヤート図、第3図は本考案の実施例の回路構
成図、第4図は本考案の実施例の7セグメントL
ED数字表示器の表示例を示す図、第5図は本考
案の実施例のマイコン出力信号波形を示す図、第
6図は本考案の実施例のセグメントデータとCH
数字表示との関係を示す図、第7図は本考案の実
施例のセグメントデータと音量設定位置表示との
関係を示す図である。 1……マイクロコンピユータ、2……チユーナ
ー、3……7セグメント数字表示器、4……操作
キー、5……D/Aコンバータ、6……ボリユー
ム回路、7……トランジスタ。
Fig. 1 is a main circuit block diagram of an embodiment of the present invention, Fig. 2 is a flowchart showing the processing procedure of an embodiment of the present invention, Fig. 3 is a circuit configuration diagram of an embodiment of the present invention, and Fig. 4 is a circuit block diagram of an embodiment of the present invention. The figure shows a 7-segment L of an embodiment of the present invention.
FIG. 5 is a diagram showing a display example of the ED numerical display, FIG. 5 is a diagram showing the microcomputer output signal waveform of the embodiment of the present invention, and FIG. 6 is a diagram showing the segment data and CH of the embodiment of the present invention.
FIG. 7 is a diagram showing the relationship between the segment data and the volume setting position display according to the embodiment of the present invention. 1...Microcomputer, 2...Tuner, 3...7 segment numeric display, 4...Operation keys, 5...D/A converter, 6...Volume circuit, 7...Transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 現在選局中のチヤンネルを表示するセグメント
数字表示器を用いたチヤンネル表示装置において
、音量加減操作に応じて計時を開始するタイマー
手段と、上記タイマー手段が計時する一定時間、
上記セグメント数字表示器において音量設定に応
じた数のセグメントを点灯することにより音量設
定状態を表示する表示手段とを備えたことを特徴
とするチヤンネル表示装置。
In a channel display device using a segment numeric display that displays a currently selected channel, a timer means starts measuring time in response to a volume adjustment operation, and a certain period of time measured by the timer means;
A channel display device comprising display means for displaying a volume setting state by lighting up a number of segments corresponding to the volume setting in the segment numeric display.
JP1988165260U 1988-12-21 1988-12-21 Pending JPH0286276U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988165260U JPH0286276U (en) 1988-12-21 1988-12-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988165260U JPH0286276U (en) 1988-12-21 1988-12-21

Publications (1)

Publication Number Publication Date
JPH0286276U true JPH0286276U (en) 1990-07-09

Family

ID=31451583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988165260U Pending JPH0286276U (en) 1988-12-21 1988-12-21

Country Status (1)

Country Link
JP (1) JPH0286276U (en)

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