JPS6235266B2 - - Google Patents

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Publication number
JPS6235266B2
JPS6235266B2 JP55090837A JP9083780A JPS6235266B2 JP S6235266 B2 JPS6235266 B2 JP S6235266B2 JP 55090837 A JP55090837 A JP 55090837A JP 9083780 A JP9083780 A JP 9083780A JP S6235266 B2 JPS6235266 B2 JP S6235266B2
Authority
JP
Japan
Prior art keywords
film
sio
silicon nitride
sample
nitrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55090837A
Other languages
Japanese (ja)
Other versions
JPS5715425A (en
Inventor
Kazuo Kajiwara
Tetsunosuke Yanada
Takanori Hayafuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP9083780A priority Critical patent/JPS5715425A/en
Publication of JPS5715425A publication Critical patent/JPS5715425A/en
Publication of JPS6235266B2 publication Critical patent/JPS6235266B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は半導体窒化物層の形成方法に関するも
のである。 VLSI(超大規模集積回路)の開発は、夫々の
素子の寸法サイズを縮小することにより著しい速
さで進められている。このVLSIにおける縦方向
のサイズは横方向のサイズと同様に考慮されなけ
ればならないが、近い将来は、MOS型トランジ
スタのゲート絶縁膜の厚みとして、シヨートチヤ
ンネル効果を除去して、Vthを安定化させる等の
ために100Å程度の値が要求される。しかしなが
ら、このようにゲート酸化膜としてのSiO2膜を
薄くすると、次の点で不都合な問題を生じてしま
う。 (1) 100ÅのSiO2膜ではリン処理等の安定化処理
ができないので、汚染防止のためのマスク作用
がなく、保護膜又は安定化膜として役立たな
い。 (2) 膜厚が薄いので、ピンホールや膜厚の不均一
さが顕著となり、製造技術上の問題が残る。 (3) SiO2膜とゲート電極との反応によつてゲー
ト酸化膜の厚さが更に減少し、トンネル効果の
ためにゲート電極と半導体基板との間が導通し
てしまう。 こうした状況下で、半導体業界ではSiO2膜に
代わるゲート絶縁膜を模索しているが、現在のと
ころ適切な材料が見出されていない。他方Si3N4
膜は、CVD法による場合にはメモリ作用が生じ
るのでメモリトランジスタとして使用されている
が、これはその膜質が良くないからである。ま
た、Siを直接窒化することによりSi3N4膜を形成
する方法があるが、実用的温度と時間では、得ら
れるSi3N4の膜厚はせいぜい50Å程度にしかなら
ず、上述した欠点を回避し得ない。 Si3N4等の窒化シリコン(SixNy)はSiO2膜に代
わるゲート絶縁膜としての有力候補であるが、上
記のように、特にその製造方法に難があり、実用
化されるには至つていない。 本発明は、比較的低温、短時間で容易に窒化シ
リコン膜を形成する方法を提供するものである。
即ち、本発明は、半導体基体上の酸化膜に鉄イオ
ンを導入する工程と、前記酸化膜を窒素含有気体
(ここで「含有」とは、窒素100%の場合の他、窒
素を一成分とする混合ガス、更には窒素化合物の
ガスをも意味している。)に接触させながら熱処
理を行い、これによつて前記酸化膜の所定領域を
窒化物に変換させる工程とを有することを特徴と
する半導体窒化物層の形成方法に係るものであ
る。 以下、本発明の実施例を図面に付き述べる。 まず第1A図のように、シリコンウエハ1の表
面上に熱酸化又はCVD処理によつてSiO2膜2を
2000Åの厚さに成長させた。 次に第1B図のように、100KeVのFe+イオン
3を1×1016cm-2のドーズ量でSiO2膜2中に注入
した。この注入条件では、Fe+イオンの飛程RP
は570Åであり、そのイオン全量がSiO2膜2中に
留められる。 次に、N2ガス雰囲気中において1200℃で所定
時間熱処理した。しかる後、ウエハ表面をX線マ
イクロアナライザにより分析したところ、SiO2
膜2が窒化シリコン膜4(第1C図)に変換され
ていることが分かつた。 具体的な実験データを次に説明すると、上記の
方法に基いて5種類のサンプルを作成した。 試料1:N2中で1時間アニールしたもの。 試料2:N2中で3時間アニールしたもの。 試料3:試料1をHFで10分間エツチングしたも
の。 試料4:試料2をHFで10分間エツチングしたも
の。 試料5:熱酸化SiO2膜形成後、Fe+イオンを注入
しないでN2中、1200℃で3時間アニールした
もの。 この結果、試料1及び2の膜表面には白色状偏
析物の形成が観察され、この偏析物はエツチング
によつてもなお残存していることが試料3及び4
によつて確認された。ところが、試料5のように
Fe+をイオン注入しないでアニールを行つても、
SiO2膜表面は何ら変化していないことが確認さ
れた。そこで、各試料表面の正常箇所(偏析物な
し)及び偏析物形成箇所について、Fe、Si、O
等の元素濃度を電子プローブマイクロアナリシス
(EPMA)法で測定したところ、下記表―1及び
表―2に示すデータが得られた。
The present invention relates to a method of forming a semiconductor nitride layer. The development of VLSI (Very Large Scale Integrated Circuits) is proceeding at a remarkable pace due to the reduction in the dimensional size of each device. The vertical size in VLSI must be considered in the same way as the horizontal size, but in the near future, the thickness of the gate insulating film of MOS transistors will be used to eliminate the short channel effect and stabilize Vth. A value of about 100 Å is required for the purpose of increasing the However, when the SiO 2 film as the gate oxide film is made thinner in this manner, the following disadvantages arise. (1) Since a 100 Å SiO 2 film cannot be subjected to stabilization treatment such as phosphorus treatment, it has no masking effect to prevent contamination and is not useful as a protective film or a stabilizing film. (2) Since the film is thin, pinholes and non-uniformity in film thickness become noticeable, and problems in manufacturing technology remain. (3) The thickness of the gate oxide film further decreases due to the reaction between the SiO 2 film and the gate electrode, and conduction occurs between the gate electrode and the semiconductor substrate due to the tunnel effect. Under these circumstances, the semiconductor industry is searching for a gate insulating film to replace the SiO 2 film, but so far no suitable material has been found. On the other hand Si 3 N 4
The film is used as a memory transistor because it produces a memory effect when using the CVD method, but this is because the film quality is not good. In addition, there is a method of forming a Si 3 N 4 film by directly nitriding Si, but at practical temperatures and times, the thickness of the Si 3 N 4 film obtained is only about 50 Å at most, making it difficult to avoid the above-mentioned drawbacks. I can't. Silicon nitride (Si x N y ) such as Si 3 N 4 is a promising candidate as a gate insulating film to replace SiO 2 film, but as mentioned above, there are difficulties in its manufacturing method, and it has not been put into practical use. has not been reached yet. The present invention provides a method for easily forming a silicon nitride film at a relatively low temperature and in a short time.
That is, the present invention includes a step of introducing iron ions into an oxide film on a semiconductor substrate, and a step of injecting the oxide film with a nitrogen-containing gas (here, "containing" means not only 100% nitrogen but also nitrogen as one component). (This also means a gas mixture of nitrogen compounds. The present invention relates to a method for forming a semiconductor nitride layer. Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1A, a SiO 2 film 2 is formed on the surface of a silicon wafer 1 by thermal oxidation or CVD treatment.
It was grown to a thickness of 2000 Å. Next, as shown in FIG. 1B, 100 KeV Fe + ions 3 were implanted into the SiO 2 film 2 at a dose of 1×10 16 cm −2 . Under these implantation conditions, the range R P of Fe + ions is
is 570 Å, and all of the ions are retained in the SiO 2 film 2. Next, heat treatment was performed at 1200° C. for a predetermined time in an N 2 gas atmosphere. Afterwards, when the wafer surface was analyzed using an X-ray microanalyzer, it was found that SiO 2
It was found that the film 2 had been converted into a silicon nitride film 4 (FIG. 1C). Specific experimental data will be explained next. Five types of samples were created based on the above method. Sample 1: Annealed in N 2 for 1 hour. Sample 2: Annealed in N2 for 3 hours. Sample 3: Sample 1 etched with HF for 10 minutes. Sample 4: Sample 2 etched with HF for 10 minutes. Sample 5: After forming a thermally oxidized SiO 2 film, it was annealed for 3 hours at 1200°C in N 2 without implanting Fe + ions. As a result, the formation of white segregated substances was observed on the film surfaces of Samples 1 and 2, and it was found that these segregated substances still remained even after etching in Samples 3 and 2.
confirmed by. However, like sample 5
Even if annealing is performed without Fe + ion implantation,
It was confirmed that the SiO 2 film surface did not change at all. Therefore, Fe, Si, O
When the concentration of these elements was measured using the electron probe microanalysis (EPMA) method, the data shown in Tables 1 and 2 below were obtained.

【表】【table】

【表】【table】

【表】 これらのデータから次のことが分る。 (1) 試料1及び2の膜表面は殆ど全部窒化シリコ
ンに変成しているが、Feイオン注入しない試
料5ではN2中でのアニールに拘らず窒化シリ
コンに全く変成していない。このことから、
Fe+を注入したことによつて、SiO2→窒化シリ
コン(例えばSi3N4)への変態点が下降し、1200
℃でも窒化反応が進行するものと推定される。
なお、1時間N2中アニールでは窒化シリコン
が厚く成長する(試料1)が、3時間アニール
(試料2)では窒化シリコン膜上に更にSiO2
(この酸素はN2中に混入したO2分子による)が
成長したものとなつている。 (2) 試料3及び4のようにHFエツチングを施せ
ば、正常箇所は膜が除去されてSiウエハ表面が
露出するが、偏析物はなお残存している。この
偏析物はいずれも窒化シリコンであり、微量C
(これは熱処理炉に含まれるカーボンによる)、
O、Feを含んでいる。しかし組成的には、試
料1及び2と同様であるとみなせるので、偏析
箇所は膜厚が大きく、エツチングでは完全に除
去しきれずに残つたものと考えられる。 以上のように、Fe+の注入によつてSiO2→窒化
シリコンへの変換が十分に可能である。特に試料
3及び4のように、偏析箇所でのFe濃度が正常
箇所の4倍程度も高くなつていることをみれば、
このFeの偏析が窒化シリコンへの反応を促進し
たものと考えられる。これは、打込まれたFe原
子による窒化反応の触媒作用が生じているが、或
いは窒化膜形成核が生じていること等が原因であ
ると思われる。なお、後述のように、Fe+の注入
量と窒化生膜成速度との間には相関関係があり、
1015cm-2オーダー以上のドーズ量では窒化反応が
著しく促進されることが分つた。また、Siウエハ
の結晶面方位が(111)の場合には、窒化反応が
非常に早く進行することも分つている。 上述の例において、窒化シリコン膜4の膜厚は
1500Åを越えていたが、SiO2膜2がすべて窒化
シリコン膜に変換されたとしてもその膜厚は1250
Å程度にしかならないことを考慮すると、シリコ
ン1表面が250Å程度だけ直接窒化されたことに
なる。これは従来の概念からみて驚異的なことで
ある。今日迄、シリコン表面を直接窒化して得ら
れた窒化膜は、窒素ラジカルの拡散速度に制限が
あることから、せいぜい100Åの膜厚にすぎない
が、本例によれば100Å以上の膜厚の窒化膜は容
易に形成できることになる。 この場合、Fe+3をマスク利用下に注入するこ
とにより、或いはイオンビーム・リソグラフイー
で注入することにより、選択的に注入領域を形成
できる。従つて、任意の場所を選択的に窒化する
ことができる。 上述のように、SiO2を効果的に窒化シリコン
に変換できるために、SiO2に代用し得る窒化シ
リコン膜を確実に形成することができる。この窒
化シリコン膜として100Å程度と薄いものから
1500Å程度と厚いものまで任意に形成でき、また
保護安定化作用がよく、ピンホールや膜厚均一性
の面でも優れたものが得られてVLSIのゲート絶
縁膜に好適となる他、絶縁膜としての一般の特性
も良好である。また膜質的にも良質であり、形成
容易な窒化シリコン膜を提供できる。 但、Fe+又はFe原子は通常、半導体素子では有
害な作用を有することがあるが、この場合にはこ
れ迄種々考慮されてきたゲツタリング処理(ウエ
ハ裏面のリンドープによるゲツタリング、ウエハ
表面に塩素含有ガスを流して塩化鉄として除去す
る方法)によつて、プロセス最終段階でFeを除
去すればよい。 上述の例ではアニール時に窒素を使用したが、
これに代えて、NH3やN2H4等の窒素を一成分と
するガスを使用してもよい。また、SiO2膜が薄
くて例えば100Å程度の場合には、この膜中にイ
オン注入することは低加速条件下でも難しいの
で、第1B図のイオン注入に代えてFe+を含むガ
ス(例えばFeCl2を含む窒素)を流すことによ
り、SiO2膜中にFe+を注入又はドープするように
してもよい。また、使用可能な半導体基体はSiウ
エハでなくGeウエハなどの他の半導体基体であ
つてもよく、要はその半導体基体ウエハにSiO2
等の酸化物膜を有するものであればよい。 次に、第1図の工程において、上述した各イオ
ン種を様々なドーズ量でSiO2膜中に注入した
後、アニールした場合の結果を下記表―3に示
す。
[Table] From these data, the following can be found. (1) The film surfaces of Samples 1 and 2 are almost entirely transformed into silicon nitride, but in Sample 5, in which Fe ions are not implanted, no transformation into silicon nitride occurs at all despite annealing in N 2 . From this,
By implanting Fe + , the transformation point of SiO 2 → silicon nitride (for example, Si 3 N 4 ) is lowered, and the transformation point is lowered to 1200
It is presumed that the nitriding reaction proceeds even at ℃.
Note that when annealing in N 2 for 1 hour, silicon nitride grows thickly (Sample 1), but when annealing for 3 hours (Sample 2), an SiO 2 film is formed on the silicon nitride film (this oxygen is mixed with O 2 in N 2 ). (by molecules) has grown. (2) If HF etching is performed as in Samples 3 and 4, the film is removed from the normal areas and the Si wafer surface is exposed, but the segregated substances still remain. All of these segregated substances are silicon nitride, with a trace amount of C.
(This is due to the carbon contained in the heat treatment furnace)
Contains O and Fe. However, since it can be considered that the composition is the same as Samples 1 and 2, it is considered that the film thickness was large in the segregated area and that it was not completely removed by etching and remained. As described above, it is fully possible to convert SiO 2 to silicon nitride by implanting Fe + . Especially if you look at samples 3 and 4, where the Fe concentration in the segregated areas is about four times higher than in the normal areas,
It is thought that this Fe segregation promoted the reaction to silicon nitride. This is thought to be caused by the catalytic action of the nitriding reaction by the implanted Fe atoms, or by the formation of nitride film formation nuclei. As will be explained later, there is a correlation between the amount of Fe + implanted and the rate of nitride biofilm formation.
It was found that the nitriding reaction was significantly accelerated at a dose on the order of 10 15 cm -2 or more. It is also known that the nitriding reaction proceeds very quickly when the crystal plane orientation of the Si wafer is (111). In the above example, the thickness of the silicon nitride film 4 is
The film thickness exceeded 1500 Å, but even if all SiO 2 film 2 were converted to silicon nitride film, the film thickness would be 1250 Å.
Considering that the thickness is only about 250 Å, this means that the silicon 1 surface is directly nitrided by about 250 Å. This is surprising from the perspective of conventional concepts. To date, the nitride films obtained by directly nitriding the silicon surface are only 100 Å thick at most due to the limited diffusion rate of nitrogen radicals, but according to this example, the nitride films obtained by directly nitriding the silicon surface are only 100 Å thick. This means that the nitride film can be easily formed. In this case, the implanted region can be selectively formed by implanting Fe + 3 using a mask or by ion beam lithography. Therefore, any location can be selectively nitrided. As described above, since SiO 2 can be effectively converted into silicon nitride, a silicon nitride film that can be substituted for SiO 2 can be reliably formed. This silicon nitride film can be as thin as about 100 Å.
It can be formed as thick as about 1500 Å, has a good protection and stabilization effect, and has excellent pinhole and film thickness uniformity, making it suitable for VLSI gate insulating films and as an insulating film. Its general properties are also good. Furthermore, it is possible to provide a silicon nitride film that has good film quality and is easy to form. However, Fe + or Fe atoms usually have a harmful effect on semiconductor devices, but in this case, various gettering treatments have been considered (gettering by phosphorus doping on the back side of the wafer, chlorine-containing gas on the front side of the wafer, etc.). Fe can be removed at the final stage of the process by a method in which Fe is removed as iron chloride by flowing iron chloride. In the example above, nitrogen was used during annealing, but
Instead, a gas containing nitrogen as one component, such as NH 3 or N 2 H 4 , may be used. Furthermore, if the SiO 2 film is thin, for example about 100 Å, it is difficult to implant ions into this film even under low acceleration conditions. Fe + may be injected or doped into the SiO 2 film by flowing nitrogen (containing nitrogen 2 ). Furthermore, the semiconductor substrate that can be used may be other semiconductor substrates such as Ge wafers instead of Si wafers, and in short, SiO 2 is added to the semiconductor substrate wafer.
Any material having an oxide film such as the like may be used. Next, in the process shown in FIG. 1, the above-mentioned ion species were implanted into the SiO 2 film at various doses and then annealed. The results are shown in Table 3 below.

【表】【table】

【表】【table】 【図面の簡単な説明】[Brief explanation of the drawing]

第1A図〜第1C図は本発明の一実施例による
方法を順次示す断面図である。 なお図面に用いた符号において、1……Siウエ
ハ、2……SiO2膜、3……Fe+、4……窒化シリ
コン膜である。
1A to 1C are cross-sectional views sequentially illustrating a method according to an embodiment of the present invention. In the symbols used in the drawings, 1...Si wafer, 2...SiO 2 film, 3...Fe + , 4... silicon nitride film.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基体上の酸化膜に鉄イオンを導入する
工程と、前記酸化膜を窒素含有気体に接触させな
がら熱処理を行い、これによつて前記酸化膜の所
定領域を窒化物に変換させる工程とを有すること
を特徴とする半導体窒化物層の形成方法。
1. A step of introducing iron ions into an oxide film on a semiconductor substrate, and a step of heat-treating the oxide film while bringing it into contact with a nitrogen-containing gas, thereby converting a predetermined region of the oxide film into nitride. A method for forming a semiconductor nitride layer, comprising:
JP9083780A 1980-07-03 1980-07-03 Method for forming semiconductor nitride layer Granted JPS5715425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9083780A JPS5715425A (en) 1980-07-03 1980-07-03 Method for forming semiconductor nitride layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9083780A JPS5715425A (en) 1980-07-03 1980-07-03 Method for forming semiconductor nitride layer

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP19190786A Division JPS6263433A (en) 1986-08-16 1986-08-16 Method for forming semiconductor nitride layer

Publications (2)

Publication Number Publication Date
JPS5715425A JPS5715425A (en) 1982-01-26
JPS6235266B2 true JPS6235266B2 (en) 1987-07-31

Family

ID=14009692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9083780A Granted JPS5715425A (en) 1980-07-03 1980-07-03 Method for forming semiconductor nitride layer

Country Status (1)

Country Link
JP (1) JPS5715425A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54161327A (en) * 1978-03-23 1979-12-20 Bolex Int Sa Camera

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54161327A (en) * 1978-03-23 1979-12-20 Bolex Int Sa Camera

Also Published As

Publication number Publication date
JPS5715425A (en) 1982-01-26

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