JPS623521A - Analog signal selecting device - Google Patents

Abstract

PURPOSE:To reduce crosstalk because of a signal not selected passing a parasitic capacitor by applying logarithmic conversion to plural analog input signals and outputting the selected signal only while being subject to inverse logarithmic conversion. CONSTITUTION:A differential voltage VdA is inputted to transistors (TRs) Q11 and Q12 and a voltage drop in response to the collector current of the TR Q11 is produced between the base and emitter of the TR Q13. The voltage drop is logarithmic compression of the voltage VdA. The voltage drop is impressed to a TR Q15. This is applied also to TRs Q14, Q16. A signal applying logarithmic compression to a differential input voltage VdB is inputted similarly to TRs Q25, Q26. When a high and a low level signal are inputted respectively to a selection signal terminals 1, 2, a current flows between the collector and emitter of the TRs Q15, Q16 but no current flows to the TRs Q25, Q26. As a result, the signal inputted to the TRs Q15, Q16 is subject to inverse logarithmic conversion and a collector current flows to resistors R101, R102, but no collector current of the TRs Q25, Q26 flows. Thus, the current flowing to the resistor is not affected by parasitic capacitors C25, C26.

Description

[Detailed description of the invention] Technical field.

The present invention relates to an analog signal selection device that selects and outputs one analog signal from a plurality of analog signals.

BACKGROUND ART A conventional analog signal selection device applies a plurality of input signals to the bases of a plurality of transistors, connects the emitters of these plurality of transistors to a plurality of switching transistors, and turns on the switching transistors by a selection signal. , one of the multiple transistors is selected and turned on by turning it off, and the output signal is the voltage drop caused by the collector current flowing through the common load resistance according to the input signal applied to the base of the selected transistor. There was something that was configured to appear as.

However, in such a device, when the input signal is high frequency, the input signal applied to the base of the transistor is transmitted between the base and collector of the transistor, even though the unselected transistors are turned off. The current flows through the parasitic capacitance to the common load resistance on the collector side. Therefore, the voltage drop caused by this current is superimposed on the voltage drop caused by the collector current of the selected transistor and becomes an output, resulting in a drawback that crosstalk occurs.

OBJECTS It is an object of the present invention to provide an analog signal selection device that eliminates the drawbacks of the prior art and can prevent the occurrence of crosstalk even in the case of high-frequency input signals.

According to the present invention, an analog signal selection device that selects and outputs one analog signal from a plurality of analog input signals includes:
Logarithmic conversion means for logarithmically converting each of the plurality of analog signals to produce a logarithmically compressed signal; antilogarithmically converting means for respectively antilogarithmically converting each of the logarithmically compressed signals to produce an output signal linear with the analog input signal; and a plurality of antilogarithms. a selection means for selecting and operating one anti-logarithmic conversion means from the conversion means, logarithmically converting each of the plurality of analog input signals to obtain a logarithmically compressed signal, and antilogarithmically converting the selected logarithmically compressed signal. This is what is output.

DESCRIPTION OF EMBODIMENTS Next, embodiments of an analog signal selection device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a particular embodiment of the analog signal selection device according to the invention has input terminals 11.12 connected to the bases of transistors Qll and Q12, respectively, and input terminals 21.22 connected to the bases of transistors Q21 and Q22. each connected.

The collector of transistor Qll is connected to the emitter of transistor Q13, the collector of transistor Q12 is connected to the emitter of transistor Q14, and the bases of transistors Q13 and Q14 are connected to a constant bias power supply v1.
The collectors of transistors Q13 and Q14 are respectively connected to a constant DC power supply v3. transistor Q
The emitter of ll is connected to the transistor Q through the resistor R11.
The emitter of No. 12 is connected to a constant current source I via a resistor R12.

The collector of transistor Q21 is connected to the emitter of transistor Q23, the collector of transistor Q22 is connected to the emitter of transistor Q24, and the bases of transistors Q23 and Q24 are connected to a constant bias power supply v2.
The collectors of transistors Q23 and Q24 are respectively connected to a constant DC power supply v3. transistor Q
The emitter of 21 is connected to the transistor Q via the resistor R21.
The emitter of 22 is connected to a constant current source I2 via a resistor R22.

The emitter of transistor Q13 is connected to the base of transistor Q15, and the emitter of transistor Q14 is connected to the base of transistor QlB.

The collector of the transistor Q15 is connected to the output terminal 101 and also to the DC power supply 3 via the resistor R101, and the collector of the transistor Q1B is connected to the output terminal 102.
is connected to the DC power supply ■3 through the resistor R102.
It is connected to the.

Emitter of transistor Q15 and transistor Q1
The emitter of B is connected to the collector of transistor Q1.

The emitter of transistor Q23 is connected to the base of transistor Q25, and the emitter of transistor Q24 is connected to the base of transistor 92B.

The collector of the transistor Q25 is connected to the output terminal 1o1 and also to the DC power supply ■3 via the resistor R101, and the collector of the transistor Q2G is connected to the output terminal 102.
is connected to the DC power supply V3 via the resistor R102.
It is connected to the.

Emitter of transistor Q25 and transistor Q2
The emitter of El is connected to the collector of transistor Q2.

Selection signal terminals 1.2 are connected to the base of the transistor Q1 and the base of the transistor Q2, respectively, so that a high level signal is input to one of the selection signal terminals 1.2, and a low level signal is input to the other. It has become.

The emitter of transistor Q1 and the emitter of transistor Q2 are connected to constant current source I3.

Next, the operation of this embodiment will be explained.

Transistors Q'11 and Q12 from input terminals 11 and 12
A differential input voltage 'VdA is input to the base of the . The differential input voltage VdA is input from an analog signal source 13 connected to input terminals 11.12.

A signal current proportional to the differential input voltage VdA flows between the collector and emitter of the transistor Qll and between the collector and emitter of the transistor Q12, but the sum of these currents flows into the constant current source 1 and becomes constant. There is. Therefore, when the differential input voltage VdA=O, the current flowing between the collector and emitter of the transistor Qll and the current flowing between the collector and emitter of the transistor Q12 are equal, and each becomes one half of the current flowing through the constant current source 11, If the differential input voltage VdA is 0, the current flowing between the collector and emitter of the transistor Qll and the current flowing between the collector and emitter of the transistor Q12 will be the current flowing to the constant current source 11 depending on the magnitude of the differential input voltage VdA. will be divided proportionally.

A constant bias power supply v is connected to the base of transistor Q13.
1 is applied, the emitter current of the transistor Q13 is equal to the collector current of the transistor Qll, and a voltage drop occurs between the base and emitter of the transistor Q13 in accordance with the emitter current of the transistor Q13. This voltage drop is obtained by logarithmically compressing the emitter current of transistor Q13, and ultimately results in logarithmically compressing the differential input voltage VdA. This voltage drop is applied to the base of transistor Q15.

Similarly, a constant bias power supply v1 is applied to the base of the transistor Q14, and the emitter current of the transistor Q14 is equal to the collector current of the transistor Q12. A voltage drop occurs. This voltage drop is obtained by logarithmically compressing the emitter current of transistor Q14, and ultimately results in logarithmically compressing the differential input voltage VdA. This voltage drop is applied to the base of transistor Q1B.

Therefore, a signal obtained by logarithmically compressing the differential input voltage VdA is input to the bases of transistors Q15 and QlB, respectively.

Through a similar operation, signals obtained by logarithmically compressing the differential input voltage VdB are input to the bases of transistors Q25 and Q2B, respectively.

Now, select signal terminal 1 has a high level signal, select signal terminal 2
When a low level signal is input to the base of transistor Q1, a high level signal is input to the base of transistor Q1, and a high level signal is input to the base of transistor Q2.
Since a low level signal is input to the base of the transistor Q1, the transistor Q1 is turned on and the transistor Q2 is turned off.

Therefore, current flows between collector and emitter in transistors Q15 and Qlli due to a logarithmic compression signal according to the differential input voltage VdA inputted from the base, but in transistors Q25 and Q2B, a logarithmic compression signal according to the differential input voltage VdB is input as the base. No current flows between collector and emitter even if input from

As a result, the signals input to the bases of transistors Q15 and QlB are inverse logarithmically transformed, and the signals input to the bases of transistors Q15 and QlB are
The collector current of QIEi flows through resistors R101 and R102, respectively, but transistor Q25
The signals input to the bases of transistors Q15 and Q2G are not antilogarithmically transformed, and the collector currents of transistors Q25 and Q2B do not flow. The signal input to the bases of transistors Q15 and QlB is a logarithmically compressed signal corresponding to the differential input voltage VdA, so the current flowing through resistors R101 and R102 is the same as the differential input voltage. It has a linear relationship with voltage VdA, and the voltage drop of this current due to resistors R101 and R102 becomes a differential output voltage and is output to output terminals 101 and 102.

Next, a low level signal is applied to the selection signal terminal l, and a low level signal is applied to the selection signal terminal 2.
When a high level signal is input to the transistor Q1, the transistor Ql is turned off and the transistor Q2 is turned on.

Therefore, current flows between the collector and emitter of transistors Q25 and Q2B due to the logarithmic compression signal input from the base, but no current flows between the collector and emitter of transistors Q15 and Q1G even when the logarithm compression signal is input from the base.

As a result, the collector currents of transistors Q25 and Q2B, which are obtained by antilogarithmically converting the signals inputted to the bases of transistors Q25 and Q2B, flow through resistors R101 and R102, and the signals inputted to the bases of transistors Q15 and QlB are antilogarithmically converted. No conversion occurs, and the collector currents of transistors Q15 and Ql,8 do not flow.

Therefore, the current flowing through resistors R101 and R102 is obtained by anti-logarithmically transforming the signals input to the bases of transistors Q25 and Q2B, and
Since the signals input to the bases of 25 and Q2B are logarithmically compressed signals corresponding to the differential input voltage VdB, the current flowing through the resistors R101 and R102 is the differential input voltage VdB, ! : A linear relationship exists, and the voltage drop of this current due to the resistors Rlot and R102 is outputted to the output terminals 101 and 102 as a differential output voltage.

The effects of this embodiment will be explained in comparison with the conventional example. A conventional device is shown in FIG. 2. In the conventional example shown in FIG.
Transistor Q15 as it is without logarithmically converting B.
, QlB and the bases of transistors Q25 and Q26.

For example, when a high-level signal is input to selection signal terminal l and a low-level signal is input to selection signal terminal 2, and transistor Ql is on and transistor Q2 is off, between the collectors and emitters of transistors Q25 and Q2B. However, there is a parasitic capacitance c25 between the base and collector of transistor Q25, and transistor Q25 has a parasitic capacitance between the base and collector.
Since there is a parasitic capacitance C2G between the base and collector of transistors Q25 and Q2B, if the input signals Bl and B2 applied to the bases of transistors Q25 and Q2B are high-frequency signals, this signal current is caused by the parasitic capacitances C25 and C2B. Since the current flows through the resistors RIOI and R102, respectively, there is a drawback that crosstalk occurs.

In the embodiment of the invention shown in FIG. 1, in a similar case, what is applied to the bases of transistors Q25, Q2fi is a logarithmically compressed signal responsive to the differential input voltage VdB. When this logarithm compression signal is a high frequency signal, this signal current passes through parasitic capacitances C25 and C2B existing between the bases and collectors of transistors Q25 and Q2G, and flows to resistors RIOI and R102. However, the resistances RIOI and R10 pass through these parasitic capacitances C25 and C2B.
2, the signal current flowing through the differential input voltage Vd
Since it is a signal obtained by logarithmically compressing the signal corresponding to B, the resistance R
1ot, since almost no voltage amplitude due to this appears across R102, there is little crosstalk.

That is, the signals input to the bases of transistors Q15 and Q1G(7) cause resistors RIOI and R102 to
The current flowing through is the signal input to the bases of transistors Q15 and QlB that is anti-logarithmically transformed, so
Passing through the parasitic capacitances C25 and C2B, the resistors R101 and R1
The voltage amplitude is sufficiently large compared to the current flowing through 02.

Therefore, the output voltage appearing at the output terminals 101 and 102 is the resistance RIOI of this anti-logarithmically transformed current,
The voltage drop due to R102 is dominant, and the parasitic capacitance C2
5. Almost no current caused by the current passing through C2B and flowing into the resistors R101 and R102 appears. Moreover, this output voltage maintains a linear relationship with respect to the signal corresponding to the differential input voltage VdA.

Note that even when a low level signal is input to the selection signal terminal 1 and a high level signal is input to the selection signal terminal 2, and the transistor Q1 is turned off and the transistor Q2 is turned on, in the conventional example shown in FIG. The signals applied to the bases of transistors Q15 and Ql6 pass through the parasitic capacitances C15 and C1B and flow to the resistors RIOI and R102, causing crosstalk, but in the embodiment shown in FIG.
Since the signal applied to the base of lB is a logarithmically converted signal, it passes through the parasitic capacitances C15 and C1B and is connected to the resistor R1.
01 and R102, there are few cases of crosstalk.
It is possible to reduce the

According to this embodiment, even if the signal applied to the transistor that is turned off by the selection signal passes through the parasitic capacitance of the transistor, the signal passing through is a logarithmically transformed signal of the input signal. , hardly appears in the output, so crosstalk can be reduced in the selection of analog signals.

Effects As described above, in the present invention, in selecting an analog signal,
After logarithmically transforming a plurality of input signals, only the selected signals are inversely logarithmically transformed and output. therefore,
Crosstalk caused by unselected signals passing through the parasitic capacitance h' can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a specific embodiment of an analog signal selection device according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional analog signal selection device. Explanation of symbols of main parts 1.2 , , , , , , selection signal terminals 11, 12 .
21.22. , , input terminals 101 , 102 ,
, , , , , , output terminal Q1. Q2. ．． ．． ．． ．．
．． ．． ) transistors Q13, Q14. Q15, QlB,
transistors Q23, Q24, Q25, Q2B,) transistors RIOI, R102,..., resistors Vl, V2. ．． ．． ．． ．． ．． ．． Bias power supply 11, I2. I
3. Constant current source patent applicant: Fuji Photo Film Co., Ltd. Agent: Takao Katori

Claims (1)

[Claims] 1. An analog signal selection device that selects and outputs one analog signal from a plurality of analog input signals, the device further comprising: logarithmically converting each of the plurality of analog signals into a logarithmically compressed signal. a logarithmic conversion means; an antilogarithmic conversion means for respectively performing antilogarithmic conversion on the logarithm compression signal to obtain an output signal linear with the analog input signal; and selecting one antilogarithmic conversion means from the plurality of antilogarithmic conversion means. What is claimed is: 1. An analog signal selection device comprising: a selection means operated by a user, logarithmically converts each of a plurality of analog input signals to obtain a logarithmically compressed signal, and outputs the selected logarithmically compressed signal after inverse logarithmically converting the signal.