JPS623465B2 - - Google Patents
Info
- Publication number
- JPS623465B2 JPS623465B2 JP56148091A JP14809181A JPS623465B2 JP S623465 B2 JPS623465 B2 JP S623465B2 JP 56148091 A JP56148091 A JP 56148091A JP 14809181 A JP14809181 A JP 14809181A JP S623465 B2 JPS623465 B2 JP S623465B2
- Authority
- JP
- Japan
- Prior art keywords
- abnormality
- circuit
- abnormality processing
- processing device
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 claims description 40
- 230000005856 abnormality Effects 0.000 claims description 33
- 238000003672 processing method Methods 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Hardware Redundancy (AREA)
- Debugging And Monitoring (AREA)
Description
【発明の詳細な説明】
本発明は異常処理方式に係り、特に複数の処理
装置の中の現用処理装置が異常状態を発生した場
合切換え使用する異常処理方式の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality processing method, and more particularly to an improvement in an abnormality processing method that is switched and used when an abnormal state occurs in a current processing device among a plurality of processing devices.
処理装置と入出力装置とが接続され入出力装置
により情報を入出力して処理装置を駆動し情報の
授受を行うシステムにおいて、何らかの理由によ
り処理装置に異常が発生した場合に別の処理装置
に入出力装置を切換え接続を行い業務処理を遂行
する方法が現在用いられている。これは処理装置
に発生した異常信号により切換え動作を行う異常
処理回路が作動することにより行われるのであ
る。従来の方式を第１図に示す。処理装置１に異
常が発生すると異常信号が異常処理回路２を作動
しスイツチ２−１を切換えて入出力装置３と処理
装置４を接続する。勿論異常処理回路２に問題が
なければ前記異常信号により所要の切換えが行わ
れるが異常信号が発生した場合にこの異常処理回
路に障害があれば切換えが行われずに現用システ
ムがそのまま使用されシステム・ダウンと認識さ
れるという欠点があつた。 In a system in which a processing device and an input/output device are connected and the input/output device inputs and outputs information to drive the processing device and exchange information, if an abnormality occurs in the processing device for some reason, it is possible to transfer information to another processing device. Currently, a method is used to perform business processing by switching and connecting input/output devices. This is done by activating an abnormality processing circuit that performs a switching operation in response to an abnormality signal generated in the processing device. The conventional method is shown in FIG. When an abnormality occurs in the processing device 1, an abnormality signal activates the abnormality processing circuit 2, switches the switch 2-1, and connects the input/output device 3 and the processing device 4. Of course, if there is no problem in the abnormality processing circuit 2, the required switching will be performed by the abnormality signal, but if an abnormality signal is generated and there is a fault in this abnormality processing circuit, the current system will be used as is without switching. The drawback was that it was perceived as being down.
本発明は以上の欠点に鑑みなされたものにし
て、本発明は現用システム運用中に異常処理回路
の動作を確認し異常処理回路障害によるシステ
ム・ダウンを防止する異常処理方式を提供するこ
とを目的とするものである。本発明を略説する
と、本発明は異常処理回路にパトロール機能を備
え、現用システム運用中に異常処理回路の動作を
確認するようにしたことを特徴とするものであ
る。 The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide an abnormality processing method that checks the operation of an abnormality processing circuit during operation of a current system and prevents system down due to failure of the abnormality processing circuit. That is. Briefly explaining the present invention, the present invention is characterized in that the abnormality processing circuit is equipped with a patrol function, and the operation of the abnormality processing circuit is checked during operation of the current system.
以下図を用いて本発明を実施するのに好ましい
具体例について詳細に説明する。第２図は本発明
の異常処理方式を示す要部ブロツク図であり、第
１図と同一箇所は同符号を用いる。５は異常処理
回路であり、異常処理回路５はオア回路５−１と
スイツチ制御回路５−２とスイツチ５−３，５−
４とで構成されている。オア回路５−１に処理装
置１の異常信号S1とパトロール信号S2とが入力さ
れ、更に各この信号S1，S2は分岐されスイツチ制
御回路５−２に入力される。オア回路５−１の出
力及び異常信号S1とパトロール信号S2とがスイツ
チ制御回路５−２に入力される。スイツチ制御回
路５−２はそれぞれの接点５−３，５−４の切換
え動作を行う。更に接点５−３及び５−４は通常
時Ａ側に接続されている。スイツチ制御回路５−
２はアンド回路５−５と５−６及び接点駆動回路
５−７と５−８を内蔵している。以上の構成の動
作について説明する。処理装置１が接点５−３を
介し入出力装置３と接続され運用されているとき
にパトロール信号S2を印加するとオア回路５−１
を介した信号とパトロール信号S2がアンド回路５
−６に印加され出力し接点駆動回路５−８を駆動
し接点５−４はＢ側に接続され処理装置４が接点
５−４のＢを介しＣ端子に接続される。従つてＣ
端子側にて接続の完了したことを確認出来ること
となる。即ちこの確認は処理装置４が接続された
ことは勿論、異常処理回路５が正常に動作してい
ることも確認していることとなる。処理装置１側
にて異常が発生すると異常処理回路５が前記説明
したと同じように動作を行い接点５−３をＢ側に
切換える。従つて入出力装置３は処理装置４と接
続されることとなる。尚、オア回路５−１とアン
ド回路５−５と５−６とは異常信号S1及びパトロ
ール信号S2以外の信号で接点５−３，５−４の切
換えを防止する役目を果す。通常運用中にパトロ
ール信号S2を印加しておけば常に切換系の確認が
行われることとなる。以上の説明は通常運用を処
理装置１として説明したが回路を変更すれば通常
運用を処理装置４として使用しても何ら支障され
ることのないのは勿論である。 Preferred specific examples for carrying out the present invention will be described in detail below with reference to the drawings. FIG. 2 is a main part block diagram showing the abnormality handling method of the present invention, and the same parts as in FIG. 1 are denoted by the same reference numerals. 5 is an abnormality processing circuit, and the abnormality processing circuit 5 includes an OR circuit 5-1, a switch control circuit 5-2, and switches 5-3, 5-.
It consists of 4. The abnormal signal S1 and the patrol signal S2 of the processing device 1 are input to the OR circuit 5-1, and each of the signals S1 and S2 is further branched and input to the switch control circuit 5-2. The output of the OR circuit 5-1, the abnormal signal S1 , and the patrol signal S2 are input to the switch control circuit 5-2. The switch control circuit 5-2 performs switching operations of the respective contacts 5-3 and 5-4. Further, contacts 5-3 and 5-4 are normally connected to the A side. Switch control circuit 5-
2 incorporates AND circuits 5-5 and 5-6 and contact drive circuits 5-7 and 5-8. The operation of the above configuration will be explained. When the processing device 1 is connected to the input/output device 3 through the contact 5-3 and is in operation, when the patrol signal S2 is applied, the OR circuit 5-1 is activated.
The signal via S2 and the patrol signal S2 are connected to AND circuit 5
-6 is applied and output to drive the contact drive circuit 5-8, the contact 5-4 is connected to the B side, and the processing device 4 is connected to the C terminal via the B of the contact 5-4. Therefore C
This allows you to confirm that the connection has been completed on the terminal side. That is, this confirmation not only confirms that the processing device 4 is connected, but also confirms that the abnormality processing circuit 5 is operating normally. When an abnormality occurs on the processing device 1 side, the abnormality processing circuit 5 operates in the same manner as described above and switches the contact 5-3 to the B side. Therefore, the input/output device 3 will be connected to the processing device 4. The OR circuit 5-1 and the AND circuits 5-5 and 5-6 serve to prevent the contacts 5-3 and 5-4 from being switched by signals other than the abnormal signal S1 and the patrol signal S2 . If the patrol signal S2 is applied during normal operation, the switching system will always be checked. Although the above description has been made using the processing device 1 in normal operation, it is of course possible to use the processing device 4 in normal operation without any problem if the circuit is changed.
以上の説明より明らかなように本発明は現用シ
ステム運用中に異常処理回路の動作を確認し、異
常処理回路の障害によるシステム・ダウンを防止
する異常処理方式となり、本発明を電子計算機シ
ステムに適用すれば電子計算機運用上の障害減少
上きわめて利点の多いものとなる。 As is clear from the above explanation, the present invention is an abnormality processing method that checks the operation of the abnormality processing circuit during operation of the current system and prevents system down due to failure of the abnormality processing circuit, and the present invention is applied to a computer system. If this is done, it will be extremely advantageous in terms of reducing problems in computer operation.
第１図は従来の方式を示すブロツク図、第２図
は本発明の異常処理方式を示す要部ブロツク図で
ある。
図において、１と４は処理装置、２と５は異常
処理回路、３は入出力装置を示す。
FIG. 1 is a block diagram showing a conventional method, and FIG. 2 is a main part block diagram showing an abnormality handling method according to the present invention. In the figure, 1 and 4 are processing units, 2 and 5 are abnormality processing circuits, and 3 is an input/output device.
Claims (1)
切換え接続されるシステムの運用中の該処理装置
に異常状態が発生したる際他の処理装置に切換え
動作を行う異常処理回路による異常処理方式にお
いて、該異常処理回路にパトロール機能を備え、
現用システム運用中に前記パトロール機能により
該異常処理回路の動作を確認するようにしたこと
を特徴とする異常処理方式。1. In an abnormality processing method using an abnormality processing circuit that switches to another processing device when an abnormal state occurs in a processing device during operation of a system in which each of a plurality of processing devices and an input/output device are switched and connected. , the abnormality processing circuit is equipped with a patrol function,
An abnormality processing method characterized in that the operation of the abnormality processing circuit is checked by the patrol function during operation of the current system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148091A JPS5850050A (en) | 1981-09-18 | 1981-09-18 | Processing system for abnormality |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148091A JPS5850050A (en) | 1981-09-18 | 1981-09-18 | Processing system for abnormality |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5850050A JPS5850050A (en) | 1983-03-24 |
| JPS623465B2 true JPS623465B2 (en) | 1987-01-24 |
Family
ID=15445031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56148091A Granted JPS5850050A (en) | 1981-09-18 | 1981-09-18 | Processing system for abnormality |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850050A (en) |
-
1981
- 1981-09-18 JP JP56148091A patent/JPS5850050A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5850050A (en) | 1983-03-24 |
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