JPH01147913A - Matrix switch - Google Patents

Abstract

PURPOSE:To avoid the occurrence of a fault in an excellent way by changing the connection of a data transfer section having no fault through the use of a standby input line or a standby output line if an input line and an output line or a data transfer section is faulty. CONSTITUTION:If the input line 1 or a 1st data transfer section 3 is faulty, 1st fault detection section 11 detects it and informs it to an input line select control section 9. The select control section 9 reconnects the external signal input line to a standby input line 4 in place of the input line 1, uses a 2nd data transfer section 7 in place of the 1st data transfer section 3 and connects it to the output line. If the output line 2 is faulty, a 2nd fault detection section 12 detects it and informs it to the output line select control section 10. The select control section 10 reconnects the external signal output line to the standby output line 5 in place of the output line 2 and the input lien 1 is connected to the standby output line 5 by using a 2nd data transfer section 6.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a matrix switch in which input lines and output lines are arranged in a grid pattern and the input lines and output lines are connected by a data transfer section at the intersection of the input lines, the output lines, The purpose of this is to provide a matrix switch that can immediately avoid a failure when the data transfer section becomes a failure.In addition to providing a backup input line and a backup output line, the intersection of the backup input line and the output line and the backup output line are also provided. and the input line, and an input line selection control unit that switches the input line to the backup input line when a failure is notified, and a data transfer unit that switches the input line to the backup input line when a failure is notified, and a data transfer unit that switches the input line to the backup input line when a failure is notified. an output line selection control section that detects a fault in the input line and the data transfer section and notifies the input line selection control section; The configuration includes a fault detection section that notifies the selection control section.

[Industrial application field]

The present invention is an improvement of a matrix switch used in nodes of high-speed packet communication networks, etc., in which input lines and output lines are arranged in a grid pattern, and the input lines and output lines are connected by a data transfer section at the intersection of Meng. Regarding.

In the above-mentioned matrix switch, it is desirable that if a failure occurs in the input line, output line, or data transfer section, the failure can be immediately avoided.

[Conventional technology]

A conventional example will be explained below using figures.

FIG. 5 is a block diagram of a conventional matrix switch used in a packet communication node.

The matrix switch 75 has input lines 1-1°1-2,
The output lines 2-1, 2-2 are arranged in a grid pattern, and data transfer units 50', 51', and 53' are located at the intersections thereof.

54' is provided, and the input data from the input line 1-1 is sent to the output line 2-1 via the data transfer section 50'', and the input data from the input line 1-1 is sent to the output line 2-1 via the data transfer section 51'.
2, and also sends the input data from the input line 1-2 to the output line 2-1 via the data transfer section 53',
In addition, the output line 2-2 is connected via the data transfer section 54°.
Exchange operations can be performed by sending it to .

To explain the operation in the case of FIG. 5 used in a packet communication node, the input packet transfer control unit, for example 40, monitors the presence or absence of a packet in the reception buffer 70 to which a terminal or line is connected, When the existence of the packet is confirmed, the packet is extracted and the address is analyzed. For example, if it is destined for a terminal connected beyond the sending buffer 72,
The packet is transferred to the data transfer unit 50°.

On the other hand, the output packet transfer control unit 42, for example, monitors the presence or absence of packets in the data transfer units 50', 53', and when the presence of the packet is confirmed, extracts the packet, analyzes the address, and sends the packet to the end of the transmission buffer 72, for example. If the packet is for a connected terminal, the packet is transferred to the transmission buffer 72.

In this way, the packet exchange operation is performed.

[Problem that the invention seeks to solve]

However, conventional matrix switches have the problem that if an input line, an output line, or a data transfer section becomes faulty, the fault cannot be recovered unless it is corrected, and the system is interrupted until the fault is completed.

An object of the present invention is to provide a matrix switch that can immediately avoid a failure when an input line, an output line, or a data transfer section becomes a failure.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, the input line 1 and the output L'A 2 are arranged in a grid pattern, and the input line 1. In the matrix switch that connects the output lines 2, a preliminary input line 4 and a preliminary output line 5 are provided, and the intersection of the preliminary input line 4 and the output line 2 and the intersection of the preliminary output line 5 and the input line 1 are provided. A second data transfer section 6.7 is provided at the intersection.

Further, an input line selection control section 9 switches the input line 1 to the auxiliary input line 4 when a failure is notified, and an output line selection control section 10 switches the output line 2 to the auxiliary output line 5 when a failure is notified. establish.

Additionally, a first fault detection section 11 detects a fault in the input line 1 and the first data transfer section 3, and notifies the human power line selection control section 9 of the fault in the output line 2. The configuration includes a second fault detection section 12 that notifies the selection control section 10.

[For production]

According to the present invention, when the input line 1 or the first data transfer unit 3 becomes a failure, the first failure detection unit 11 detects this,
This is notified to the input line selection control section 9, and the input line selection control section 9 connects the external signal input line to the preliminary input line 4 instead of the input line l, and uses the first data transfer section 3. First, the second data transfer section 7 is used to connect to the output line 2.

If the output ￥a2 becomes a failure, the second failure detection unit 12 detects this and notifies the output line selection control unit 10, and the output line selection control unit 10 changes the external signal output line to the output line 2. Instead, connect it to the spare output line 5, and connect it to the input line 1.
is connected to the spare output line 5 using the second data transfer section 6.

Therefore, input line 1. Output line 2. When the first data transfer unit 3 becomes a failure, the failure is immediately avoided.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of a matrix switch when used in a packet communication node according to an embodiment of the present invention, FIG. 3 is a block diagram of a data transfer section in the case of FIG. 2, and FIG. FIG. 3 is a diagram illustrating an example of a failure avoidance method in the case of the above.

The difference between FIG. 2 and FIG. 5 is that the preliminary input line 4. A preliminary output line 5, an input line selection control section 9, an output line selection control section 10, parity addition sections 20 to 22, parity error detection sections 35 to 37, OR circuits 23 to 34, and data transfer sections 52, 55 to 58 are provided. , the data transfer units 50 to 58 are arranged as shown in FIG.

The operation will be explained below, focusing on this different point.

As shown in FIG. 3, the data transfer units 50 to 58 include a parity error detection unit 60. Memory 61. The parity error detection unit 60 detects a fault in the input line, the parity error detection unit 62 detects a fault in the memory 61, and when the fault is detected, the OR circuit 6
It is designed to be output to the outside via 3.

Note that the memory 61 is for data transfer and has been provided in the past.

At the entrances of the input lines t-t and 1-2° of the matrix switch and the preliminary input line 4, parity adding units 20 to 22 are provided, respectively, where parity is added to the data and transmitted. 50 to 58, if an error is detected by the parity error detection unit 60 shown in FIG. ).

Data transfer units 50 to 52 connected to input line 1-1
The faults detected in the input line selection control unit 9 are notified via the OR circuits 23 and 24, and the faults detected in the data transfer units 53 to 55 connected to the input lines 1-2 are
The input line selection control unit 9 is notified via the OR circuits 25 and 26, and failures detected in the data transfer units 56 to 58 connected to the auxiliary input line 4 are notified to the OR circuits 30 and 31.
The input line selection control unit 9 is notified via.

Also, a data transfer section 50.5 connected to the output line 2-1
The fault detected in 3.56 is notified to the output line selection control unit 10 via the OR circuit 27.32, and the output line 2-
A failure detected in the data transfer units 51, 54, 57 connected to the auxiliary output line 5 is notified to the output line select control unit IO via the OR circuit 28, 33, and the failure detected in the data transfer units 51, 54, 57 connected to A fault detected in the sections 52, 55, 58 is notified to the output line selection control section 10 via the OR circuit 29, 34.

If an error is detected by the parity error detection units 35, 36, and 37, the output lines 2-1, 2-2, and the backup output line 5 are faulty, and the output line selection control unit 10 is notified of this fact. Ru.

The input line selection control section 9 is a changeover switch SWI.

SW2. When switching the input cotton 1-1 to the auxiliary input line 4, set the changeover switches SW1 and sw3 to the dotted line side, and when switching the input line 1-2 to the auxiliary input line 4, set the changeover switch SW2 to the dotted line side.゜SW3 is on the dashed-dotted line side.

The output line selection control section 10 includes a selector switch SW4. S
W5. It has SW6, and when switching the output line 2-good 1 to the spare input line 5, use the changeover switch SW.
4. When setting SW6 to the dotted line side and switching the output line 2-2 to the ridge preliminary input line 5, switch SW5.
SW6 is on the dashed-dotted line side.

In addition, an input line selection control section 9 and an output line selection control section 10
The lines are connected by busy/idle signal lines 80 and 81, and are set to be idle when not switched to the backup line, and set to busy when switched.

Therefore, using FIG. 4, input lines and data transfer section.

Failure avoidance in the case of a failure in the output line will be explained.

As shown in (A), if the input line, for example 1-2, is at fault, fault information is input from the OR circuit 25 in FIG. However, since the busy/idle signal line 80 is idle, the output line select control unit 10
does not operate, and the input line select control unit 9 connects the external signal line to the auxiliary input line 4 instead of the input line 1-2 to avoid the failure, and sets the busy/idle signal line 80 to busy. .

As shown in (B), if the output line, for example 2-2, is faulty, the parity error detection unit 36 in FIG.
Since the signal is input to the output line selection control section 10, the output line selection control section 10 switches the output line 2-2 to the spare output line 5 to avoid a failure, and makes the busy/idle signal line 81 busy.

As shown in (C), if there is a failure in the data transfer unit, for example 53, the failure information is input from the OR circuit 25 in FIG. However, since the busy/idle signal line 8o is idle, the output line select control unit 1O does not operate, and the input line select control unit 9 connects the external signal line to the input line 1-2. Instead, the spare input line 4 is connected to avoid the failure and the busy/idle signal line 80 is made busy.

In this state, if the data transfer section 57 becomes faulty as shown in (D), fault information is input from the OR circuit 30 in FIG. It is input to the line selection control section IO.

At this time, the busy/idle signal line 80 is busy, so the output line select control section 10 switches the output line 2-2 to the spare output line 5 to avoid the failure, and makes the busy/idle signal line 81 busy.

When both the busy and idle signal lines 80 and 81 become busy, switching is no longer performed.

As mentioned above, when the input line or the output line is switched to the auxiliary input line 4 or the auxiliary output line 5, this information G is notified to the input packet transfer control unit 40.41, and for example, the input line 1-1
is switched to the spare input line 4, the input packet transfer control section 40 causes the packet to be transferred to the data transfer section 50.51 to be transferred to the data transfer section 56.57, and the packet to be transferred to the data transfer section 50.53. The packets to be transferred are transferred to data transfer units 52 and 55.

As explained above, the matrix switch shown in FIG.

In this case, a single failure can be completely avoided, and depending on the failure, even a double failure can be avoided.

Of course, failures can be avoided in the same manner even in the case of a bus matrix switch as a matrix switch.

〔Effect of the invention〕

As explained in detail above, according to the present invention, a single failure of the input line, output line, and data transfer unit can be immediately and completely avoided.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a matrix switch when used in a packet communication node according to an embodiment of the present invention, and Fig. 3 is a data transfer unit in the case of Fig. 2. FIG. 4 is a diagram showing an example of a failure avoidance method in the case of FIG. 2, and FIG. 5 is a block diagram of a matrix switch when used in a conventional packet communication node. In the figure, 1.1-1.1-2 is a human power line, an evening transfer section, 4 is a preliminary input line, 5 is a preliminary output line, 9 is a human power line selection control section, 10 is an output line selection control section, 11. 12 is a failure detection section, 20-22 is a parity addition section, 23-34.63 is an OR circuit, 35-37, 60.62 is a parity error detection section, 40
．． 41.40' and 41' are input packet transfer control units, 42.43 is an output packet transfer control unit, 80.81 is a busy/idle signal line, and SWI to SW6 are changeover switches. Early 1 Go to figure ＼ 5

Claims (1)

[Claims] An input line (1) and an output line (2) are arranged in a grid, and the first data transfer unit (3) at the intersection point transfers the input line (1) to the input line (1).
In a matrix switch that connects output lines (2), a preliminary input line (4) and a preliminary output line (5) are provided, and the intersection of the preliminary input line (4) and the output line (2) and the A second data transfer unit (6, 7) is provided at the intersection of the auxiliary output line (5) and the input line (1), and when a failure is notified, the input line (1) is connected to the auxiliary input line (1). 4) and an output line selection control unit (10) that switches the output line (2) to the backup output line (5) when a fault is notified, and furthermore, the input line (1) and the first data transfer unit (3), and notifies the input line selection control unit (9) of the first failure detection unit (11) and the output line (2). A matrix switch characterized in that a second fault detection section (12) is provided for detecting and notifying the output line selection control section (10).