JPS6233552B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to the configuration of a timepiece equipped with a plurality of electromechanical transducers, for example, a plurality of pulse motors or a pulse motor and a sounding body, and is particularly based on the system design of an integrated circuit (hereinafter abbreviated as IC). It's a lot of things. In conventional electric clocks, a time reference signal obtained from an accurate crystal oscillator is frequency-divided, a motor is driven by this signal, the time is maintained by a mechanical counter consisting of a wheel train, and the current time is displayed by a hand. I let it happen. Recent advances in electronic technology have made it possible to incorporate electronic counters into integrated circuit chips, making it possible to create fully electronic watches. However, in terms of things other than practicality, people prefer the calm look of conventional mechanical display watches, and it has become necessary to create a new and convenient watch that maintains the appearance of mechanical display crystal watches. It's here. Convenient functions reinforced with electronic circuitry include a complete month-end uncensored calendar and an alarm. For example, the information processing for sending a calendar at the end of the month is performed electronically, and by controlling a motor dedicated to the calendar, the mechanism of the machine can be made simple and less likely to break down. In this case, it becomes necessary to further install a driver circuit that occupies a large area of the integrated circuit in order to drive the time keeping motor and the calendar motor, but according to the configuration of the present invention, the IC chip size for driving The increase will be suppressed.
Further, the present invention solves the problems of displaying an alarm sound and driving a pulse motor, as well as the problem of driving a clock equipped with a large number of sounding elements. Hereinafter, the configuration of the present invention will be explained based on the drawings. FIG. 1A is a basic block configuration diagram of the configuration of the present invention, and FIG. 1B is a conventional configuration corresponding to FIG. 1A. FIG. 2 is a block configuration diagram when this configuration is applied to a two-motor timepiece without end-of-month correction, and FIG. 3 is an embodiment of an alarm timepiece according to the present invention. FIG. 4 shows the relationship between symbols and a power amplification circuit consisting of a pair of complementary field effect transistors that is effective for realizing this configuration. FIG. 5A shows a driving method for a plurality of electromechanical transducers according to the present invention, and FIG. 5B shows a conventional driving method corresponding to FIG. 5A. Fifth
Figure C shows an example of a conventionally known system in which three coils of a phase motor are driven by three amplifiers. FIG. 6 shows an example of drive waveforms according to the present invention when two motors are driven by two series of pulses P ₁ and P ₂ respectively. FIG. 7 shows a multiplexed drive waveform synthesis circuit that synthesizes drive waveforms. FIG. 8 is another example of multiplexed drive waveforms. Figure 9 shows an example of an IC circuit when the present invention is applied to a crystal watch with an alarm, and Figures 10 A, B, C, and D show examples of IC circuits when the IC shown in Figure 9 is used in a crystal watch with an alarm. This shows an example of a system configuration. In FIGS. 1A and 1B, reference numerals 101 and 151 are time reference signal sources, which are composed of, for example, a crystal oscillation circuit. Reference numerals 102 and 152 denote time unit signal synthesis means, which is composed of, for example, a frequency dividing circuit. In some cases, a reset input terminal is provided for synchronizing the phase of the clock unit signal and the standard time. 104,12
Reference numerals 4, 154, and 174 are electromechanical converters for converting electrical energy into mechanical energy, such as pulse motors or piezoelectric buzzers. 105, 155, and 125 are mechanical display mechanisms that display information using mechanical displacement like 175. It moves and displays information in the form of sound. The difference between FIGS. 1A and 1B lies in the drive section, and due to multiplexed drives, the drive section of FIG. 1A is simpler than the conventional system of FIG. 1B. FIG. 2 is an example in which the present invention is applied to a two-motor type timepiece without month-end correction. 201 is a crystal oscillation circuit, 202 is a frequency dividing circuit, 212 is a multiplexed drive waveform synthesis circuit, 213 is a power amplification circuit, and 214 is a pulse motor 224 is also a pulse motor. 215 and 225 are gear trains, 216 and 226 are display bodies, 2
32 is a synchronization circuit that detects the daily change signal obtained from the wheel train 215 which receives the clock signal from the frequency dividing circuit 202 in synchronization with the clock pulse, and transmits the daily change information to the electrical calendar counter circuit. .
222 is a waveform shaping circuit for calendar feeding;
The shaped driving signal is sent to the multiplexing circuit 212. Reference numeral 231 includes an external operating member and a switch mechanism to set initial values of time and calendar. The wheel train 215 is directly connected to the days of the week, and sends out daily signals as electrical signals at 12:00 midnight. Calendar counting circuit 242 provides day, month, and year information.
At the end of the month, the date is fast-forwarded using the daily change signal as a starting point. For example, on the day board
Prepare a space for 40 days, and fast forward from the 28th to the 31st of the month until the 1st. During the fast-forward period from the 32nd day to the 1st, the lunar plate is moved up by the intermittent gear train mechanism and moves for one month. The moon plate is equipped with a contact mechanism that allows the month to be read by encoding it with a binary code for each month.
By moving the date board for one month, the state of the mechanical system can be made to match the electrical memory. All you have to do is read the monthly plate code and store it as monthly information. Regarding February, there are four types of February on the moon plate, such as ²⁰ , 2 ^January , 2 ^February , and ² March, and there are 15 months in a year, and regarding the feeding of the moon plate,...1 Month, 2 ^October , March...1
Month, 2 ^January , March, ...January, 2 ^February , March, January,
2 ^March , March, . . . , the three months from February ²⁰ to ^{March 23} are always skipped while being shifted sequentially. If we drive a motor to move one day's worth of date plates using eight 8 msec pulses, it will take 5 seconds to move one month's worth, or 40 days' worth, and the extra "February" will be equivalent to 3 months' worth. 15 seconds is all it takes to skip. An electric circuit controls the February skip. The initial state setting when the battery is installed is as follows. In other words, connect a capacitor and a resistor in series, connect one end of the capacitor to the power line that should be negative in the circuit, connect one end of the resistor to the power line that should also be positive, and connect the inverter circuit to the connection point of the resistor and capacitor. Connect and draw a wire from the inverter output end and the power supply of the circuit that should be positive,
Connect to the two input ends of the NAND gate circuit,
Connect an inverter to the NAND gate output terminal.
When the battery is connected to the clock, the potential of the capacitor rises after a short delay, so the output terminal of the NAND gate will see a narrow pulse fall only once when the battery is connected. A separately prepared set/reset flip-flop is set using pulses shaped and inverted by an inverter, the output of the flip-flop instructs fast-forwarding of the date plate, and when the code signal of the moon plate is detected, the flip-flop instructing the fast-forwarding is reset. Even when the watch battery is inserted, the electrical and mechanical systems can be completely synchronized automatically in 5 to 15 seconds. It also turns out that it is possible to create a complete month-end uncensored calendar that includes leap years. FIG. 3 shows an example in which the present invention is applied to a quartz watch with an alarm. 301 is a crystal oscillation circuit, 3
02 is a frequency dividing circuit, 311 is a motor shaping circuit, 3
12 is a multiplexing circuit, 313 is a power amplification circuit, 31
4 is a pulse motor, 315 is a wheel train, 316 is a time information display body consisting of a pointer and a dial, 332 is a synchronization circuit, 331 is a control unit that includes external operating members and switches and sets and corrects the time, and 342 is a counter. This circuit is a counting circuit that is necessary for improving alarm accuracy and for the snooze function and timer function, but it may be omitted. 322 is a waveform shaping circuit that creates an alarm buzzer driving waveform. 325 is a reference mechanism and is set by the control unit 331. Reference numeral 423 in FIG. 4 indicates a drive power amplifier, which in the case of a watch is often constructed from complementary field efficiency transistors. 411 is a P type transistor, 412 is an N type transistor,
Each gate and each drain are connected together to form an input end and an output end, respectively. 402,422
is an output end, and 401 and 421 are input ends. Fifth
Figure A is an example of a multiplexed drive circuit according to the present invention, in which 501, 502, 503 are power amplifiers as shown in Figure 4, 511, 512 are drive coils, 521, 52
2 is a rotor magnet. The rotor 521 is the coil 5
Driven by a potential difference (E ₁ −E ₂ ) applied to 11,
The rotor 522 is driven by the coil 512 by applying a potential difference of (E ₂ −E ₃ ). The relationship among E ₁ , E ₂ , and E ₃ and the potential differences e ₁₂ =E ₁ −E ₂ and e ₂₃ =E ₂ −E ₃ are shown in the table. FIG. 5B is an example of driving two motors using the conventional method. 531, 532, 533,
534 is a power amplifier, 541 and 542 are drive coils, and 551 and 552 are rotor magnets. Comparing Figures A and B, the amplifier 502 is replaced by the amplifier 532.
It can be seen that 533 and 533 are also used. FIG. 5C shows a conventionally known three-phase motor and its drive circuit. 599 is a rotor, 591, 592, 593 is a coil, 581, 582, 583 is a power amplifier,
571 is a drive waveform creation circuit. In FIG. 5C, there is one rotor driven and three drive coils 5.
91, 592, and 593 are connected to each other via the rotor 599 in a certain relationship, that is, by cooperating to move the rotor 599 or cooperating to stop the rotor 599. One of the purposes of multiplexed driving in the present invention is to drive multiple loads independently of each other, and there is a big difference. FIG _. 6 is an example of a waveform diagram when two motors are driven by a drive circuit such as that shown in _FIG . , shows a method for transmitting and driving the motor 2. Each motor is a pulse motor that operates with alternating pulses. FIG. 7 is a more detailed view of FIG. 5A, illustrating how a waveform such as that shown in FIG. 6 may be created. In FIG. 7, 701 and 702 are flip-flops for storing the phase of motors for alternate driving, 711, 712, 713, and 714 are gate circuits that create alternate driving pulses for each motor, and 73
1, 732, 733 are gate circuits for multiplexed waveform synthesis, and 741, 742, 743 are power amplifiers. Figure 8 is similar to Figure 6; the effect remains the same, but the waveform is devised so that the frequency at which the power amplifier is driven is lowered as much as possible, and the phase difference between the outputs of the amplifier circuit is used to alternately drive the amplifier. I tried it, so the 11th
From the figure, it can be synthesized using a decoder circuit. Figure S ₀
The symbols ˜S ₇ correspond to FIG. Here, I would like to add some information about how to create the waveform in Figure 7.
The logical formula is

【formula】

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【formula】

It looks like [Formula]. FIG. 9 is an example in which the present invention is not applied to a quartz watch with an alarm. In FIG. 9, 902 is a crystal oscillator, 904 is an oscillation amplifier, 906, 90
8 is a dynamic frequency divider circuit with a frequency division ratio of 1/5, 91
0 is a 5/8 frequency divider circuit, 908 is also a 5/8 frequency divider circuit, 91
4 is a 1/16 frequency divider circuit, 916 is a 1/128 frequency divider circuit, 9
18 is a 1/32 frequency dividing circuit. The vibrator 902 is 2 ²²
Hz resonator, the final stage output of the frequency divider circuit 918 is 1
It becomes Hz. 919 and 920 are small duty pulse shaping circuits. In the case shown in the figure, think of it as an active low pulse. , 922 is a clock pulse D _C with a duty of 1/256 created by the shaping circuit 920.
_LI becomes an active high narrow pulse through the NOR gate. P _CLI is 4096Hz.
924 is an input circuit consisting of a flip-flop, which is constantly reset by P _CLI . The connection terminal is always open and connected to a high level only when active, and when P _CLI is at a low level, the input terminal consisting of a flip-flop is in a memory state. 926,928,930,93
2 is an input terminal, 972, 974, 976, 978
is a switch. The switch is closed with active and becomes high level. 934 is a flip-flop for alarm detection, and 945 is the output terminal of the flip-flop, which receives the reset signal _PES or 60
It is reset by the minute timer signal. Allows the alarm to sound while the flip-flop is set. Reference numeral 933 is a data type flip-flop for waveform shaping noise removal, and when the terminal 932 becomes H level, it sends out an H level signal R _ES 931 in synchronization with P _CLI by a clock pulse. 940 is a flip-flop for snooze, and 943 is an output terminal of the flip-flop. Snooze input terminal 93
When 0 becomes H level, it is reset and the timer signal
It is set every 5 minutes by the low level of _SM .
Output terminal 943 of the snooze flip-flop and output terminal 9 of the alarm memory flip-flop 934.
A signal that instructs to produce sound when 45 is at low level.
_ZS is sent. Reference numeral 942 is a gate circuit that generates the sound generation instruction signal _ZS . 921 is a gate circuit for duty setting, which is combined with a flip-flop 919 to generate a narrow motor drive pulse P at 1 Hz.
Create _{an IS} . 936 is a seconds counter, which is a sexagesimal counter circuit, 938 is a quinary counter circuit that creates a signal in 5-minute units, and 947 is a decimal counter circuit that receives the 5-minute signal and creates a 60-minute signal. .
950 is a toggle flip-flop for motor phase storage, and 952 and 954 are alternate driving pulse pairs created to drive the motors.
Reference numeral 955 is a gate circuit that synthesizes signals for sounding a buzzer, and 957 sends out a signal having an opposite phase to that of the gate 955 when the buzzer is to be sounded. 944
is a buzzer sounding signal, and 946 is a reverse signal for buzzer sounding. 960, 962, 958 are power amplification circuits, 964, 968 are drive coils, 96
6 is a rotor, and 970 is a vibrating body. The signal 952 corresponds to q _{11 12} , the signal 954 corresponds to q ₁₂ , the signal 946 corresponds to q ₂₁ , and the signal 944 corresponds to q ₂₂ . 982 is the frequency dividing circuit 91
984 is a gate for changing the frequency division ratio of 0,912 from 1/8 to 5/8; 984 is a gate for converting the counter 936 into sexagenary; and 986 is a gate for converting the counting circuit 938 into quinary. FIG. 10 is a block diagram when the ICs A, B, C, and D shown in FIG. 9 are used in a watch. In FIG. 10A, 1011 is the IC shown in FIG. 9, 1012 is a mechanical component of the watch, and 10
13 is a buzzer, 1014 is a motor, and 1015 is a guide plate that rotates once every 24 hours or 12 hours and turns on the alarm switch. 1016 is a buzzer switch that stops the buzzer. Figure 10B is a double indicator type alarm clock, and the components other than the minute indicator are the first alarm clock.
Figure 0A is assumed to be the same, and common parts are omitted for clarity. 1021 is the IC, 1022 is the mechanical component of the watch, and 1025 is the hour guide.
1027 is a minute standard. For example, to set an alarm at 12:05 noon, set the hour guide to 12:00 noon and set the minute guide to +05 minutes. If the standard error in Figure 10A is ±5 minutes, it can be done within ±30 seconds depending on the minute. FIG. 10C is characterized by an alarm that is accurate to the second, and has a configuration in which the second counting circuit can be reset and the alarm is detected every minute. In Figure 10C, 1031 is IC, 103
2 is the mechanical component of the watch, 1035 is the hour indicator plate, 1
037 is a minute indicator, and 1036 is a switch for synchronizing seconds, which is used to reset the second counting circuit in IC 1031 at the exact minute. FIG. 10D is a configuration in which a snooze switch is added to the configurations of FIGS. 10A, B, and C above. 1 in Figure 10D
042 is IC, 1048 is snooze switch,
When the switch 1048 is pressed when the alarm is sounding, the sounding stops and starts again after 5 minutes. To stop the buzzer completely, switch 101 in Figure 10A.
All you have to do is prepare a switch corresponding to 6 and turn it off.

[Brief explanation of the drawing]

FIG. 1A is a block diagram of an embodiment of the drive system according to the present invention, and FIG. 1B is a drive system according to the prior art.
2 is a block diagram of an embodiment in which the present invention is applied to a clock with an uncorrected month-end calendar, FIG. 3 is a block diagram of an embodiment in which the present invention is applied to a clock with an alarm, and FIG. An example of the configuration of an amplifier, an explanatory diagram, and Fig. 5 A is an explanatory diagram of the driving principle of the present invention, Fig. 5
Fig. B is an explanatory diagram of a conventional drive, Fig. 5C is an explanatory diagram of another conventional drive, Fig. 6 is a waveform diagram of the drive, and Fig. 7 is a circuit diagram showing an example of the configuration of the drive section of the present invention. FIG. 8 is a waveform diagram of the drive according to the present invention, FIG. 9 is an example of application of the present invention to an alarm clock IC, the circuit diagram is FIG. 10A is an example of an alarm timing configuration, and the configuration diagram is FIG.
10C is a configuration diagram of the alarm clock, FIG. 10D is a configuration diagram of the alarm clock, and FIG. 11 is a state diagram of the drive according to the present invention. 101: Time reference signal source, 102: Time unit signal synthesis means, 103: Drive circuit, 104: Electromechanical converter 1, 124: Electromechanical converter 2, 10
5: Mechanical display means 1, 125: Mechanical display means 2.

Claims (1)

[Claims] 1. A time reference signal generation circuit 151, and a time measurement unit signal generation circuit 152 that divides the frequency of the signal from the time reference signal generation circuit 151 to create a time measurement unit signal _P1 .
One is a timekeeping drive circuit 153 that amplifies the timekeeping unit signal _P1 to produce a drive signal, the first electromechanical converter 154 is driven by the timekeeping drive circuit 153 and holds the time, an additional function drive circuit 173 connected to the mechanical display means 155 for displaying the clock unit signal, and an additional function drive circuit 173 for amplifying the additional function signal _P2 controlled by the additional function information from the timekeeping unit signal; In the electronic clock circuit connected to the second electromechanical converter 174 driven by the second electromechanical converter 174 and the additional function display means, the timekeeping drive circuit includes a plurality of gate circuits 731 and 73.
The additional function drive circuit 173 includes a first power amplification circuit that amplifies signals from a plurality of gate circuits 732 and 733. A second power amplification circuit consisting of a pair of inverters 742 and 743 for amplification is provided, and one inverter 742 of the pair of inverters 741 and 742 of the first power amplification circuit is connected to a pair of second power amplification circuits. An electronic timepiece circuit characterized in that it is also used as one 742 of inverters 742 and 743.