JPS6233450A - Mis semiconductor storage - Google Patents

Abstract

PURPOSE:To obtain an MIS semiconductor storage having a charge holding capacity not causing a soft error, by providing a capacity section in which the semiconductor substrate is utilized as one capacity electrode and a conductive material is utilized as the other capacity electrode, the conductive material being buried in a groove and small holes formed on the semiconductor substrate through a dielectric film provided on the surfaces of the groove and the small holes. CONSTITUTION:An MOS transistor constituting a memory cell comprises a gate electrode 2A serving also as a work line, impurity diffused layers 9A and 9B formed on a semiconductor substrate 7 to provide source and drain regions and having an opposite type of conductivity to that of the semiconductor substrate, and others. A capacity section is constructed by utilizing the semiconductor substrate 7 as one capacity electrode and utilizing polycrystalline silicon 1 as the other capacity electrode. The polycrystalline silicon 1 is buried in a groove formed along the groove pattern 5 on the semiconductor substrate 7 and in small holes 15 through a dielectric film provided on the surfaces of the groove and the small holes 15. In this manner, a memory cell having a minimum charge holding capacity not causing a soft error due to alpha rays can be formed on a small area. Further, an MIS semiconductor storage having a large capacity can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a one-transistor, one-cabinet MIS type semiconductor memory device.

[Conventional technology]

In order to realize a large-scale storage device (hereinafter referred to as a memory), it is necessary to reduce the planar area of one memory cell. However, if the size is simply reduced, the area of the memory cell capacitance section will also decrease, which increases the possibility of soft errors caused by alpha rays. To address this soft error problem, a method has been devised to reduce the planar area without reducing the area of the capacitor. In other words, it is a type in which a groove is dug in a semiconductor substrate and the side surface of the groove is used as a capacitor.

FIGS. 2(a) and 2(b) are a plan view and B-B of an example of a conventional MIS type semiconductor memory device in which a capacitive portion is formed in a groove.
FIG.

In FIGS. 2(1) and 2(b), the MOS transistor has an impurity diffusion layer 9 forming the source/drain region.
A, 9B and the gate electrode 7 which also serves as the word line 2 are used as one capacitor electrode, and the groove pattern 5 on this semiconductor substrate 7 is
The other capacitor electrode is formed with polycrystalline silicon 1 buried thereon via an insulating film 8 as a dielectric film provided on the surface of the groove formed along the groove. That is, the capacitor section is composed of a planar capacitor section on the plane of the semiconductor substrate and a side capacitor section in the groove.

[Problem that the invention seeks to solve]

In the conventional MIS semiconductor memory device formed in this manner, it has become possible to manufacture a memory with a larger capacity than the conventional MIS type semiconductor memory device that does not use grooves.

However, when a memory with a larger capacity is manufactured, the memory cell is reduced in size, and the charge retention capacitance Cs of the memory cell capacitor portion becomes smaller, which has the disadvantage that soft errors due to α rays are likely to occur again.

The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a large-capacity M
An object of the present invention is to provide an IS type semiconductor memory device.

[Means for solving problems]

The NIS semiconductor memory device of the present invention includes a memory cell consisting of a MOS transistor formed on a semiconductor substrate and a capacitor connected to the MOS transistor, and an insulator embedded to separate the memory cells. In the MIS type semiconductor memory device, the capacitor section has a semiconductor substrate as one capacitor electrode, and a dielectric film provided on the surface of the groove and the pore formed on the semiconductor substrate. The conductive material buried in these grooves and pores is connected to the other capacitor.

It is formed as a pole.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Figures (a) and (b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention.

The difference from the conventional example shown in FIGS. 2A and 2B is that a pore is formed in a planar capacitor portion on the semiconductor substrate, and a capacitor portion is also formed on the side surface of this pore.

In other words, in FIG. 1 (al, (bl), a MOS transistor constituting a memory cell is formed on a semiconductor substrate 7 and has impurity diffusion layers 9A and 9B of a conductivity type opposite to that of the semiconductor substrate, which serves as a source/drain region. The capacitor part is composed of a gate electrode 28 which also serves as a wire 2, and the capacitor part uses the semiconductor substrate 7 as one capacitor electrode, and the grooves formed along the groove pattern 5 on the semiconductor substrate 7 and the surface of the pores 15. Polycrystalline silicon 1 is formed as the other capacitor electrode, which is buried in these trenches and pores via an insulating film 8 as a dielectric film provided.

Note that 4 is an insulator buried in the trench separating memory cells, 6 is an impurity diffusion layer of the same conductivity type as the semiconductor substrate to prevent leakage between cells, and 8 is an insulator between the eyebrows. It is a membrane.

In this embodiment configured in this manner, the capacitive portion is formed mainly within the groove and the pore portion, so that the area of the capacitive portion can be made smaller than that of the conventional one.

〔Effect of the invention〕

Forming a memory cell with a minimum charge storage capacity that does not cause soft errors due to alpha rays on a much smaller plane area than a memory cell with L1μ snowφB+11odr et al. can do.

Therefore, a MIS type semiconductor memory device with a larger capacity can be obtained.

[Brief explanation of the drawing]

Figures 1 (al and b) are a plan view and a sectional view of an embodiment of the present invention, and Figures 2 (a) and (b) are conventional MIS
FIG. 2 is a plan view and a cross-sectional view of a type semiconductor memory device. 1...Polycrystalline silicon, 2...Word line, 2 people...Gate electrode, 3...Contact hole, 4...Insulation Item, 5...Groove pattern, 6...Impurity diffusion layer, 7...
Semiconductor substrate, 8... Insulating film, 8A...
Interlayer insulating film, 9A, 9B... impurity diffusion layer, 1
o...Bit line, 15...Pore. Kaya 7 Kaii 2 countries

Claims (1)

[Claims] A MOS transistor formed on a semiconductor substrate and the M
In an MIS type semiconductor memory device having a memory cell consisting of a capacitive part connected to an OS type transistor, and a trench in which an insulator is buried and separating the memory cells, the capacitive part connects the semiconductor substrate to one capacitor. A conductive material is formed as an electrode, and a conductive material buried in the grooves and pores is formed as the other capacitive electrode via a dielectric film provided on the surface of the grooves and pores formed on the semiconductor substrate. M characterized by
IS type semiconductor memory device.