JPS6232829B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a channel diagnostic method that allows channel function diagnosis and performance evaluation without sustaining input/output devices. Figure 1 shows DMA (direct memory access)
FIG. 1 is a block diagram showing the persistence system of the device, in which reference numeral 1 is the main memory. Main storage device 1 is connected to main storage control device 2 . The main storage device 1 is operated by a central processing unit (hereinafter referred to as CPU) under the control of the main storage control device 2.
3. Used for cycle stealing with selector channel 5 connected to DMA bus 4. Input/output control devices 7 and 8 are connected to the selector channel 5 through a selector bus 6, respectively. A plurality of input/output devices 9, 10... are connected to the input/output control device 7, and a plurality of input/output devices 11, 12... are connected to the input/output control device 8, respectively. In the system shown in FIG. 1, the selector channel 5 transfers data between any of the input/output devices 9 to 12 and the main memory 1 according to a channel control word stored in the main memory 1 in advance. This is mainly done. That is, the selector channel 5 is started by receiving the address where the channel control word is stored from the CPU 3 as a start command, and reads and inputs the channel control word. And selector channel 5
performs operations specified by channel control words, such as data transfer and control of input/output devices. To explain the operation of the selector channel 5 in more detail, in addition to reading the channel control word, it also decodes the channel control word, executes the channel control word (data transfer,
execution of commands), writing of input/output completion status, generation of interrupts, etc. In such a conventional selector channel 5, when checking the data transfer operation between the main storage device 1 and the input/output device via the channel, the input/output device 9 is connected to the selector bus 6 as shown in FIG.
12 had to be actually connected, which was a problem. Moreover, since data transfer is performed by connecting the main storage device 1, selector channel 5, input/output control devices 7, 8, and input/output devices 9 to 12, even if a failure occurs during data transfer, any failure will occur in any device. It was extremely difficult for the CPU 3 to determine whether this was the case. Furthermore, in many cases, both a low-speed input/output device and a high-speed input/output device are connected to the selector channel 5. It was difficult to judge whether the conditions were strict or not. The present invention has been made in view of the above circumstances, and its purpose is to provide a diagnostic method in a channel that can efficiently diagnose its own functions without connecting input/output devices. Another object of the present invention is to significantly shorten the time required to discover a fault through a reliable self-diagnosis function. Still another object of the present invention is to facilitate performance evaluation and reliability evaluation of selector channels. Hereinafter, a selector channel according to the present invention will be described as an example with reference to the drawings. Figure 2 shows selector channel 2 according to this invention.
FIG. 2 is a block diagram showing the configuration of one embodiment of the invention. In Fig. 2, 21 is a high-speed DMA bus (hereinafter referred to as high-speed bus), which is not shown in Fig. 2, but is connected to the main memory control device as shown in Fig. 1, and has multiple channels connected to it. has been done. A high-speed bus driver/receiver circuit 22 is connected to the high-speed bus 21 . This high-speed bus driver/
The memory address register 24 and the write data register 2 are sent from the receiver circuit 22 via the bus 23.
5, a read data register 26 and a device number register 27 are connected. The bus 23 is a bus through which data from the high-speed bus 21 passes, and the memory address register 24 is a register that stores a memory address to be sent to a main memory controller (not shown). The write data register 25 is a register that stores data to be sent to the main memory (not shown). Further, the read data register 26 is a register that stores data from the main storage device, and the device number register 27
is a register that stores the target device number of the channel activation command. The memory address register 24, write data register 25, and read data register 26 are each connected to an internal bus 28. This internal bus 28 is an internal bus through which memory data or selector bus data of the microcomputer passes. The microcomputer 29 is designated by the reference numeral 29, and the microcomputer 29 exchanges data with each register through an internal bus 28, and also through an activation signal line 30 to which a transfer start command signal STRF0 is sent. It is connected to the microcomputer 29 via an end signal line 32 connected to the selector bus control circuit 31 and through which the transfer end interrupt signal ETRF0 sent from the selector bus control circuit 31 passes.
The selector bus control circuit 31 receives a memory request signal.
A memory request signal line 33 through which BREQ0 passes is connected. The memory request signal line 33 is connected to a high-speed bus control circuit 42 (described later). The microcomputer 29 further exchanges data with an input/output device (not shown) through an input/output bus 34 and a selector bus driver/receiver circuit 35. selector bus 3
6 is a bus through which data and various control signals to the input/output device pass. A selector bus driver/receiver circuit 37 is connected to the selector bus 36 . Selector bus driver/receiver circuit 37 is connected to internal bus 28 . A counter 38 is also connected to this internal bus 28 . The counter 38 counts the number of transferred bytes, and its output terminal is connected to the above-mentioned selector bus control circuit 31 through a counter 0 signal line 39 through which a counter 0 signal indicating completion of transfer of a specified number of data bytes passes. There is. On the other hand, 40 is a command register, which is connected to the internal bus 28 mentioned above. This command register 40 transmits an access command to the internal bus 28, and when data is written to the command register 40 through the internal bus 28, operations such as reading from the internal bus 28 and writing to the internal bus 28 are started depending on the contents. It's becoming like that. Also, 41
is the random access memory (hereinafter referred to as RAM) of the microcomputer 29, and this RAM
41 is connected to a microcomputer 29 through an internal bus 28. Note that 42 is a high-speed bus control circuit, which is connected to the high-speed bus 21 mentioned above. Further, 43 is a simulator for performing functional diagnosis and simulation of the selector channel 20, and is connected to the selector bus 36. This simulator will be explained in detail later. Additionally, the microcomputer 29 is output with a device number output signal ADRS0 indicating that the device number is being output to the input/output device, a command output signal CMD0 indicating that a command is being output, and data as well. data available signal DAV0 indicating that data input to the selector channel 20 is requested, data request signal DR0 indicating that data input to the selector channel 20 is requested, status request signal SRQ0 indicating that equipment status is requested, and interrupts from input/output devices. Each signal line (not shown) through which an interrupt acknowledgment signal ACK0 for a request is sent to the selector bus 36 is connected. Furthermore, the microcomputer 29 receives a response signal SYNC0 returned from the input/output device in response to various control signals sent from the selector channel 20, and a response signal SYNC0 when data transfer between the selector channel 20 and the input/output device is completed. Each signal line (not shown) through which the interrupt signal ATN0 sent from the input/output device passes is connected. On the other hand, the selector bus control circuit 31 receives a status request signal SRQ0 and a data available signal.
Signal lines (not shown) through which DAV0 and data request signal DR0 are respectively sent to selector bus 36 are connected. Furthermore, the selector bus control circuit 31 receives response signals from input/output devices.
A signal line (not shown) through which SYNC0 passes, a signal line (not shown) through which a count signal CNTR0 sent to the counter 38 every time one byte of data is transferred, and data between the main storage device and the input/output device. A signal line (not shown) is connected to which a transfer end signal EDBYTE0 indicating the end of transfer is sent onto the selector bus 36. Note that each signal line of the status request signal SRQ0, each signal line of the data available signal DAV0, and each signal line of the data request signal DR0 connected to the microcomputer 29 and the selector bus control circuit 31 is connected to a corresponding OR circuit, respectively. (not shown). and the microcomputer 29 through each OR circuit.
Alternatively, each status request signal SRQ0, data available signal DAV0, and data request signal DR0 given from the selector bus control circuit 31 are sent to the selector bus 36, respectively. Next, prior to explaining the operation of FIG. 2, a general explanation of the operation of the parts related to the present invention will be given. The hardware that controls data transfer between an input/output device and the main storage device is called a channel, and the hardware that controls data transfer between one high-speed input/output device and the main storage device is called a channel. It is called a selector channel. The channel control program is a program in which input/output commands for transferring data, transferring auxiliary control information to the input/output device side, reading status information from the input/output device side, etc. are arranged like a program. That is, data transfer with the input/output device is started by a command from the main program of the CPU, and the subsequent processing is completed by the channel performing the input/output operation independently of the main program. A channel program consists of instructions called channel control words (CCW). FIG. 3 shows an embodiment of a data processing device including a selector channel according to the present invention. As is clear from this figure 3, CPU51
In order to perform input/output efficiently, the high-speed bus 5
It uses two buses: 2 and low-speed bus 53.
It consists of a main storage device 54, a bus controller 55, and an arithmetic control device 56. The high-speed bus 52 has a data width of, for example, 32 bits and can transfer information at high speed.
Main storage device 54, arithmetic and control device 56, multiplexer channel 57, selector channel 58
...is connected. Further, a low-speed bus 53 that exists independently of this high-speed bus 52 has a data width of, for example, 8 bits or 16 bits for low-speed input/output, and is connected to an arithmetic and control unit 56 and this low-speed bus 53. This is a bidirectional bus for transferring information between devices, and is similar to the input/output bus of conventional systems controlled by the arithmetic and control unit 56. The selector bus 59 controlled by the selector channel 58 has the same structure as the low-speed bus 53, and has various input/output devices (I/O
) are connected. However, only one input/output device connected to this selector bus 59 can transfer data with the main storage device 54 through the selector channel 58. FIG. 4 shows an embodiment of the CPU 51 in FIG. 3, particularly near the arithmetic and control unit. In FIG. 4, 61 is an arithmetic unit that performs various operations, 62 is a main memory that stores various programs or data, and 63 is an instruction discrimination control unit that discriminates instruction codes or instruction word lengths in the main memory 62. , 64 is a control unit that controls the operation of the microprogram according to instructions from the instruction discrimination control unit 63. Also, 65 is the general register (GR ₀ ~ GR ₁₅ )
and these 16 general registers 65 are each 16
The general register 65 is composed of bits and is used as an accumulator during various calculations, and the general register 65 can also be used as an index register. 6
6 is a program status word counter (hereinafter referred to as PSW). This is a register that displays the program execution status (disable/enable interrupts), status, etc., and includes a status section (STATUS), condition code section (CC),
It consists of a location section (LOC). Fifth
The figure shows the configuration of the PSW 66. As is clear from FIG. 5, STATUS consists of 12 bits and indicates the current state of the CPU, and the function of each bit is as shown in Table 1 below.

【table】

[Table] In addition, the condition code CC is generally set and reset each time an instruction is executed, and indicates the status of the operation result (carry, overflow, positive (large), negative (small), zero (etc.), input/output device state), 4
It consists of bits, and the meaning of each bit is as shown in Table 2 below.

[Table] Also, as other information, bits 16 and 17
is the timer, 18 to 20 are unused, 21 to 23 are the priority interrupt control mask EMASK for termination interrupts, and bits 24 to 31 are the interrupt code. When an interrupt occurs, the old PSW stores the cause of the interrupt as a code in this part. It is set by the CPU, and the types include hardware check, program check, and supervisor coil. The location LOC holds the address of the instruction currently being executed by the CPU, and when instruction execution (excluding branch instructions) is completed, the contents are changed to the address of the next instruction to be executed. . Returning to FIG. 4, 68 is an instruction register (IR) that holds the upper 16 bits of the instruction word, and the contents of this instruction register 68 determine which microprogram is executed. It is decided. Further, 69 is a buffer register (IB) for buffering this instruction word, and 70 is a 16-bit memory address register (MAR) that holds an address when reading/writing to the main memory 62. 81 is a 16-bit memory data register (MDR) that holds data read from the main memory 62 or data written to the main memory 62; 82 is a base register (BR) for base modification; BR ₁ ~ _BR7 is its configuration register. 83 is a working register (WR) used by the microprogram, 84 is an auxiliary register for calculations (QR), 85 is a destination bus, 86 is a data bus that sends the contents of each register to the calculation unit 61, and 87 is a main memory device. A data transfer bus 88 is used to transfer the contents of the buffer register 68 to the instruction discrimination control section 63, the instruction register 68, and the memory data register 81. Reference numeral 89 denotes a firmware storage section for a control memory (ROM) in which microprograms for controlling these computer systems are stored, a ROM address register RAR for specifying addresses, and a ROM data register RDR for latching data. Here, the outline of the channel control operation shown in FIG. 6 will be explained. In FIG. 6, 91 is the H bus (high-speed bus), 92 is the main memory, 93 is the CPU,
94 is a channel (CH), and 95 is an input/output device for data transfer. This input/output device 95
A channel 94 controls data transfer between the main storage device 92 and the main storage device 92 . This data transfer is started by a start command SIO from the CPU 93. Here, I will give an overview of channel control.
First, the channel control word (CCW) required for the device (input/output device) to be activated
Generates one block or multiple blocks of CCB (Channel Control Block) on the main memory 92.
Set as . And the above generated
SIO so that CCW is analyzed by hardware
Activate by command. When the CPU 93 executes the SIO command, the channel 94 is activated, and at this time, the CCB address is sent from the CPU 93 to the channel 94. CCB (channel control block) is information indicating input/output processing methods of channels and input/output devices, and is stored in the main storage device 92. After receiving the address of the CCB, the channel 94 reads the contents of the corresponding CCB from the main memory 92 and stores the service table in the channel 94.
Set to CST. Input/output processing is performed according to the contents of this service table CST.
When this input/output processing is completed, the channel 94 stores the channel status and information in the CCB on the main storage device 94.
Write input/output device status, etc., and write the CPU9
3 and sends out the CCB storage address and queue number. The CPU 93 is the main storage device 92
Write the CCB storage address within the corresponding number of the termination queue list TQL above and generate a channel termination interrupt. The program uses this interrupt to read the CCB storage address from the termination queue list TQL using a list command, and performs processing such as checking the status of channels that have finished operating and input/output devices. Note that the termination queue structure is a list structure, and there are six queues, 1 to 6.
is numbered. The queue number to be registered at the end of the operation is specified by the SIO command or CCB chain information. Also, a termination interrupt is an interrupt that occurs when data is stored in the queue, and this interrupt is a termination interrupt of the PSW.
Interrupt generation is restricted in the EMASK section. Therefore, it may occur even when a PSW change occurs. The above is the basic operation of the channel control operation. In this FIG. 6, in the main storage device 92,
IOB is an input/output buffer that temporarily stores transferred data. In addition, within the CPU 93,
IPM is an instruction processing mechanism, and TPM is a termination processing mechanism. Furthermore, CCM in the channel 94 is a channel control mechanism, and the operation of each device will be described later. By the way, the above CCB (Channel Control
There are 16 types of Blocks, which are identified by the channel command classification number of the upper 4 bits of the CCW (Channel Control Word) in the CCB. The functions and operations of channel command classification numbers 0 and 1 will be explained below as standard channel functions. First, the format of commands used in channel control will be explained. Figure 7a is the SIO instruction (StartIO), Figure 7b is the TIO instruction (TestIO)
OP is the instruction code, R ₁ is the general-purpose register of the first operand, and X _{2 is} the format of
is a part for setting the index register for second operand modification, _B2 is a base register for second operand modification, and _D2 is a part for setting the displacement of the second operand. Note that the general-purpose register specified by the first operand both shows the channel number and device number, and the second operand shows the channel control data (termination queue number and device number for SIO, and the termination queue number and device number for TIO. (channel status and device status) are stored therein. With the SIO instruction, the CPU sends the channel control data (termination queue number and CCB storage address 32) indicated by the second operand to the channel and device specified by the first operand.
transfer bits). Once this data is correctly transferred to the channel,
The V bit of the condition code CC of PSW is set to "0" or "1". If the target device is inoperable due to a malfunction or other reason,
A channel termination interrupt occurs. On the other hand, according to the TIO instruction, the CPU receives the respective statuses from the channel and device specified by the first operand, and stores them at the address indicated by the second operand. At this time, when the V bit of the condition code CC is "0", it indicates that the operation has been completed correctly, and when the V bit is "1", it indicates that the channel is not connected. Next, FIGS. 8 and 9 show an example of a CCB format and a CCW format.
The CCB is information indicating channels and input/output processing methods of input/output devices, and is stored in the main memory, and each piece of information has the following functions. (1) Command classification: Indicates that it is a selector channel. (2) Change destination device address: If there is a chain specification or device change specification, this indicates the address of the device that is the target of the next requested operation. (3) Queue specification: Specifies that a termination interrupt be issued to the CPU when the requested operation is completed.
The queue number to be registered must be known by an SIO command or a previous CCB. (4) Chain specification: After all requested operations are completed, if this bit is set, a new CCB is read from the main memory area indicated by the chain address and the requested operation is executed there. do. (5) Device change specification: Specifies that when a new operation is executed by chain specification, the device that is the target of the operation will be changed. If this specification is specified, the new device address to be operated on is shown in (6) below. (6) Equipment attribute specification: Indicates the type of bulk system that is the target of the operation request. 0...No specification 1...Disk type 2...Drum type 3...MT (magnetic tape) type 4...FDD (flexible disk drive)
Type 5...Cassette MT, Cartridge MT Type 6-15...Undefined (7) Command; Indicates the requested action. Next, device attribute specification will be described in more detail.

【table】

【table】

【table】

【table】

[Table] Next, the functions of each field in CCB will be described. (1) CCW: This has been mentioned above, so it will be omitted. (2) Start address: When transferring data between the main storage device and the bulk system, this indicates the start address of the target area on the main storage device side. (3) Number of bytes to be transferred: An operation request for data transfer, indicating the number of data to be transferred. When the requested operation is completed and the CCB is rewritten, the number of bytes actually transferred is subtracted from here. (4) Channel address, device address, channel status, device status; After completing the execution of the requested operation, the selector channel writes the channel address and device address that actually operated in this field. Also, check the status of the bulk system at this point and write them together in the channel status and device status. (5) Queue, chain address; When CCW has chain designation, next CCB
Indicates the start address where is stored. The queue number specified here indicates the queue number at which the termination interrupt should be registered when a queue is specified in the next CCB.
If this is "0", it will be registered in the last queue specified before that. (6) Auxiliary memory address: When data is transferred between the main memory and bulk, this indicates the transfer start address on the bulk side in units of sectors. Next, a description will be given of processing performed by a bulk controller (not shown) that controls bulk such as channels and magnetic tape devices. In the case of data transfer, the channel and bulk controllers provide information about the requested operation.
Get it from CCB. (1) Processing during setup of requested operation execution When a channel and bulk controller executes a new operation request, the following processing is performed. CCB storage address given by SIO instruction,
Alternatively, if a chain is in progress, a new CCB is read into the bulk controller from the main memory area indicated by the chain address of the previous CCB. The requested operation content is determined by specifying device attributes and decoding the command. The data transfer area requested by the start address and auxiliary storage address is known, and the number of data transfers specified by the number of transfer bytes is performed. (2) Processing at the end of operation If the requested operation is completed normally, or if an error occurs during transfer, the next process is performed. When the channel completes its operation, check the channel and device status and write them in the channel status and device status sections of the CCB. Furthermore, write the channel address and device address that are the target of the operation. (3) Processing by CCW After completing the processing in (1) and (2), perform the processing specified by CCW in the bulk controller. However, this is the case when it operates normally. Checks the queue specification bit, and if set, issues a termination interrupt to the CPU. If it has been reset, move on to the next process. Check the chain specification bit, and if it is set, it will be indicated in the chain address section.
Prepare to execute CCB operation requests.
If it has been reset, it waits for an operation execution request by the next SIO command. If there is a chain specification and the device change specification bit is set, the device to be operated is changed to the device indicated in the change target device address section and the next CCB operation request is executed. Note that if an error occurs during operation and the operation is terminated, a termination interrupt is unconditionally issued to the CPU and no chaining is performed. At this time, the queue to which the interrupt is issued is the queue specified last in the SIO command and the chain address in the CCB in the chain. The data processing device described above is required to have the following functions. (1) CCB specified by main program instruction
Based on the storage address, the CCB is read from the main memory 54 via the high speed bus 52 shown in FIG. (2) Decipher the device attribute specification and commands in the CCB. (3) Perform the data transfer requested by the start address and auxiliary memory address. (4) At the end of the transfer, write the CCB with the channel, device status, number of transferred bytes, start address, etc. in the CCB rewritten to the main memory. (5) Arithmetic control unit 5 along with CCB storage address
6 via the high-speed bus 52. FIG. 10 is a detailed block diagram of the selector channel. 101 in FIG. 10 is a high-speed bus (H bus), 102 is a bus through which information sent from the high-speed bus 101 passes, including channel number/equipment number,
Passes CCB storage addresses, data read from main memory, etc. Reference numeral 103 is a bus through which information sent from the channel to the high-speed bus 101 passes, including the address of the main storage device, data written to the main device, and CCB storage address in the case of an interrupt. 1
07 is a device number register (DNR) that stores the channel number and device number when activated by the SIO command. 108 is express bus 1
109 is a read data register (RDR) that temporarily stores data from 01, 109 is a write data register (WDR) that temporarily stores data to the high-speed bus 101, and 110 is a memory address register that temporarily stores the address of the main memory device. (AR), 104
is the memory bus of the microcomputer 111, 1
05 is an input/output bus of the microcomputer 111, 106 and 113 are bidirectional driver/receiver circuits, 112 is a memory (RAM) of the microcomputer 111, and 115 is a selector bus (SEL). 116 is a command register (CMD) that gives commands to access the high-speed bus 101. When data is written to the command register 116 through the memory bus 104, the data is read from the high-speed bus 101, written to the high-speed bus 101, or high-speed depending on the contents. bus 1
Starts an operation such as an interrupt to 01. Reference numeral 114 denotes a control unit (CONT) for the high-speed bus 101, which performs high-speed bus access in response to data written to the command register 116. In addition, when the high-speed bus access is completed, or when the high-speed bus 1
When the CCB storage address is sent through 01, an interrupt is issued to the microcomputer 111. Register 107, read data register 10
8, write data register 109, address register 110, memory 112, command register 1
16 is connected to the memory bus 104 of the microcomputer 111 and has a fixed address in the memory space of the microcomputer 111. The microcomputer 111 can access the above registers by accessing the memory 112. The operation is shown below. When the SIO instruction is executed, the channel number device number is temporarily placed in the device number register 107 through the high-speed bus 101, and then the CCB storage address is temporarily placed in the read data register 108 through the high-speed bus 101, and control is performed at the same time. An interrupt is sent to the microcomputer 111 from the section 114 . When the microcomputer 111 receives an interrupt, it registers the device number register 107 and the read data register 10.
8 is stored in the memory 112. continue,
Set in CCB storage address register 110. Thereafter, a high-speed bus read command is written to the command register 116. The control unit 114 is the command register 11
6 reads data from the address of the main memory specified by the address register 110 and temporarily stores it in the read data register 108;
An interrupt is applied to the microcomputer 111.
When the microcomputer 111 receives an interrupt, it transfers the contents of the read data register 108 to the memory 112. By repeating the above operations, the microcomputer 111 transfers the CCB to the memory 11.
Incorporate into 2. Next, the CCB is decoded and data is transferred between the input/output device, channel, high-speed bus, bus controller, and main memory through the selector bus by the number of data specified by the CCB to the area of the main memory specified by the CCB. Let's do this. The operation of the selector channel 20 according to the present invention will now be explained based on the detailed block diagram of FIG. First, the microcomputer 29
The start address of the main memory device specified by CCB is transferred to the internal bus 28 in the memory address register 24.
Set it through. Thereafter, the number of transferred bytes specified by the CCB is set in the counter 38. The microcomputer 29 then sends the device number (address) to the input/output device having the device number held in the device number register 27 along with the device number output signal ADRS0. In contrast, when the relevant input/output device learns that the device number is its own number (address), it sends a response signal.
Send SYNC0 to microcomputer 29. When the microcomputer 29 receives the response signal SYNC0, it stops sending out the device number output signal ADRS0. In response to this, the output of the response signal (SYNC0) from the input/output device is stopped, and the sending of the device number is completed. Next, the microcomputer 29 sends the command and then sends the transfer start address (start address) of the input/output device to the input/output bus 3.
4, selector bus driver/receiver circuit 35,
This is done for input/output devices through the selector bus 36. At this time, a command output signal CMD0 is sent from the microcomputer 29 in response to the sending of the command, and a data available signal DAV0 is sent in response to the sending of the transfer start address. Furthermore, it goes without saying that a response signal SYNC0 is returned to the microcomputer 29 from the input/output device in response to these signals. When these setup operations are completed, the microcomputer 29 outputs a transfer start command signal STRF0 through the command register 40. This transfer start command signal STRF0 is input to the selector bus control circuit 31 via the start signal line 30.
As a result, control of the selector bus 36, ie, input/output control, is transferred to the selector bus control circuit 31. On the other hand, along with this, the microcomputer 29 is released from input/output control operations. The selector bus control circuit 31 is connected to the selector bus 36
Sends the status request signal SRQ0 upward. A response signal SYNC0 is then sent from the corresponding input/output device along with the device status. This status is sent to the selector bus control circuit 31 via the selector bus 36, selector bus driver/receiver circuit 37, and internal bus 28 in this order. The selector bus control circuit 31 outputs a status busy signal.
SD040 is monitored, and when the busy signal SD040 becomes inactive (level "1"), that is, when the input/output device becomes ready for data exchange, the status request signal SRQ0 is made inactive. And the input/output device sends a status request signal
When SRQ0 becomes inactive, response signal SYNC0
becomes inactive. On the other hand, the selector bus control circuit 31 receives the response signal
When SYNC0 becomes inactive, data output or data input control operation is performed. In other words, the selector bus control circuit 31 sends to the input/output device a data available signal DAV0 (for transferring data from the main memory to the input/output device) or a data request signal DR0 (for inputting data from the input/output device to the main memory). case). At this time, data is sent onto the selector bus 36. In other words, when transferring data to an input/output device,
The selector bus control circuit 31 sends the 1-byte data temporarily stored in the read data register 26 onto the selector bus 36 through the internal bus 28 and the selector bus driver/receiver circuit 37, and activates the data available signal DAV0. . When the input/output device receives the data available signal DAV0, it activates the response signal SYNC0 and takes in the data on the selector bus 36. Further, when inputting data from an input/output device, the selector bus control circuit 31 writes data sent from the input/output device onto the internal bus 28 through the selector bus 36 and the selector bus driver/receiver circuit 37 into a write data register. Temporarily set the number to 25. When the input/output device receives the data available signal DAV0 or the data request signal DR0, it sends a response signal.
Activate SYNC0. When the selector bus control circuit 31 receives the response signal SYNC0, it makes the data available signal DAV0 or the data request signal DR0 inactive. Then, the input/output device makes the response signal SYNC0 inactive when the data available signal DAV0 or the data request signal DR0 becomes inactive. This completes the exchange of 1 byte of data. When the data exchange of one byte is completed, the count value of the counter 38 is subtracted by "1" by the count signal CNTR0 given from the selector bus control circuit 31. The above operation is repeated until the count value of the counter 38 becomes "0". Then, when the count value reaches "0", the counter 0 signal line 3
9, the selector bus control circuit 31 is notified that the transfer of the number of data bytes specified by the CCB has been completed. As a result, the selector bus control circuit 31 sends a transfer end interrupt signal ETRF0 to the microcomputer 29 through the end signal line 32.
At the same time, the transfer end signal EDBYTE0 is sent to the input/output device. As a result, the control of the selector bus 36 is again transferred to the microcomputer 29.
Move to. On the other hand, the input/output device receives the transfer end signal
Upon receiving EDBYTE0, it sends an interrupt signal ATN0 to the microcomputer 29. Upon receiving the interrupt signal, the microcomputer 29 sends an interrupt acknowledge signal ACK0 to the input/output device. When the input/output device receives the interrupt acknowledgment signal ACK0, it sends its own device number onto the selector bus 36 and also sends a response signal SYNC0 to the microcomputer 29. Note that in this embodiment, the selector bus control circuit 31
The 4-byte data is read data register 26.
A memory request signal BREQ0 is sent to the high-speed bus control circuit 42 through the memory request signal line 33 every time it is sent from the input/output device to the input/output device or every time it is placed in the write data register 25 from the input/output device. As a result, the high-speed bus control circuit 42 operates, and the data in the main memory device is transferred to the read data register 26 via the high-speed bus 21 and stored therein.
Alternatively, the input data stored in the write data register 25 is transferred to the main storage device via the high speed bus 21. The memory address register 24 shows the next address of the main memory. As described above, in the selector channel 20 according to the present invention, there are cases in which the microcomputer 29 performs control of the selector bus, and cases in which the selector bus control circuit 31 performs the control. However, in either case, the selector channel 20 is required to have the following five functions for function diagnosis of the selector channel, simulation of input/output devices, and the like. That is, (1) Device number output signal ADRS0, command output signal CMD0, data available signal DAV0, data request signal DR0, status request signal
SRQ0, response signal to interrupt acknowledge signal ACK0 (so-called selector bus control signal)
SYNC0 is returned. (2) A busy status (busy signal SD040) is returned for a certain period of time in response to the status request signal SRQ0 given from the selector bus control circuit. (3) Holds the output data (equipment number, command data, output information) transferred to the input/output device. (4) Input requests (status request signal SRQ0, data request signal DR0, interrupt acknowledge signal
Data can be output in response to ACK0). (5) Activate interrupt signal ATN0 by receiving transfer end signal EDBYTE0, and clear interrupt signal ATN0 by receiving interrupt acknowledge signal ACK0. FIG. 11 shows in detail an embodiment near the simulator 43 in the selector channel 20 in which the above five functions are realized. In the figure, reference numeral 121 is a flip-flop. This flip-flop 121 is set by the test start signal STEST0 given from the microcomputer 29 in FIG. 2, and reset by the test end signal ETEST0. Thus, the flip-flop 121 outputs an active ("1" level) test signal TEST1 during the set period. As a result, the test mode in the selector channel is designated and the simulator 43 is enabled. Reference numeral 122 is a NAND gate circuit. The NAND gate circuit 122 receives device number output signals ADRS0 and ADRS0, which are respectively given via the driver circuit 123.
Command output signal CMD0, data available signal DAV0, data request signal DR0, status request signal SRQ0, and interrupt acknowledge signal ACK0
is taken as input. The NAND gate circuit 124 receives the output signal of the NAND gate circuit 122 and the test signal TEST1 as inputs, and outputs a response signal SYNC0 from its output terminal. These NAND gate circuits 122 and 124 realize the function shown in (1). Reference numeral 125 is a register, and the load terminal L
, a data input section, and a data output section. This register 125 receives 8-bit wide selector bus data in response to the rise of the device number output signal ADRS0 input to the load terminal L, that is, the state transition from "0" level (active) to "1" level (inactive). Bus (SD**0)
126 (in this embodiment, busy time setting data as described later) is a data register. Reference numeral 127 denotes a flip-flop, for example a D-type flip-flop, which has a data input terminal D, a clock input terminal CK, a reset input terminal CLR, and an output terminal. The flip-flop 127 responds to the state transition of the stakes request signal SRQ0 input to the clock input terminal CK from the "1" level (inactive) to the "0" level (active) during the control operation period of the selector bus control circuit 31. In response, test signals TEST1 to 2 are input to data input terminal D at that time.
It holds the value level. Reference numeral 128 designates an AND gate circuit connected to the output terminal of the flip-flop 127 and having an input terminal to which the held data is input, an input terminal to which the basic clock signal CLK1 is input, and an output terminal. Further, reference numeral 129 denotes a counter, which includes a clock input terminal CK connected to the output terminal of the AND gate circuit 128, a reset input terminal CLR, and an output terminal. Thus, the counter 129 counts up by "1" in response to the rise of the output signal of the AND gate circuit 128. code 130
is a comparator. The comparator 130 receives the count output of the counter 129 and the contents held in the register 125 as inputs, and compares the magnitude thereof. Therefore, the comparator 130 outputs a "1" level output signal until the count output of the counter 129 matches the content held in the register 125.
If they match, a "0" level output signal is output from the output terminal. Reference numeral 131 indicates the output of the comparator 130, the test signal TEST1, the output of a NAND gate circuit 133, which will be described later, and the NAND gate circuit 143.
It is a NAND gate circuit with each output as input. Therefore, the NAND gate circuit 131 receives the status request from the selector bus control circuit 31.
Only when outputting SRQ0, during the period when the output signal of the comparator 130 is at the "1" level (the period until the count output of the counter 129 matches the content held in the register 125 in the test mode), the output signal, that is, the busy Set signal SD040 (busy status) to “0” level (active). On the other hand, numeral 132 is a NAND gate circuit,
Data available signal DAV0, data request signal DR0, and inverter circuit 13 described later
5. The status request signal SRQ0, which is sequentially applied through the NAND gate circuit 134, is input. Further, the reference numeral 133 is also a NAND gate circuit, and includes an input terminal and an output terminal to which the output signal of the NAND gate circuit 132 and the test signal TEST1 are respectively input. The output terminal of this NAND gate circuit 133 is the reset input terminal of the flip-flop 127 and counter 129.
CLR and the input terminal of the NAND gate circuit 131, respectively. And an active (“0” level) data available signal
When DAV0 or data request signal DR0 is input to NAND gate circuit 132, NAND gate circuit 133 outputs a "0" level output signal. This causes flip-flop 12
7 and counter 129 are both reset. The flip-flop 127 performs a latch operation in response to the status request signal SRQ0 inputted to its clock input terminal CK during the control operation of the selector bus control circuit 31 as described above. On the other hand, the status request signal SRQ0 is also applied to the microcomputer (reference numeral 29 in FIG. 2) during control operation. Therefore, the flip-flop 12 is activated by the status request signal SRQ0 given during control operation by the microcomputer.
7 must be prohibited from performing a latch operation. Furthermore, while the selector bus control circuit 31 is in control operation, it is necessary to cancel the inhibition of the latch operation. That is, when the status request signal SRQ0 from the selector bus control circuit 31 is received, it is necessary to give it the meaning of a busy signal (output of the NAND gate circuit 131). The NAND gate circuit 13 realizes this.
4 and an inverter circuit 135. This NAND gate circuit 134 receives an input/output operation control signal.
It receives the status request signal SRQ0 applied via IOCNT1 and the inverter circuit 135 as input. This input/output operation control signal IOCNT1
is the microcomputer 2 (in Figure 2)
9 indicates the "1" level during the control operation period, and the selector bus control circuit 31 indicates the "0" level during the control operation period (during the period when the microcomputer 29 is released from the control operation). Therefore, when the microcomputer 29 outputs the active (“0” level) status request signal SRQ0 during the control operation period, the NAND gate circuit 134
The “0” level output signal is sent to the NAND gate circuit 13.
Send to 2. In addition, the NAND gate circuit 134
When the selector bus control circuit 31 outputs the active (“0” level) status request signal SRQ0 during the control operation period, the selector bus control circuit 31 sends an output signal of “1” level to the NAND gate circuit 132. The above-mentioned register 125, flip-flop 127,
The function shown in (2) above is realized by the AND gate circuit 128, the counter 129, the comparator 130, the NAND gate circuits 131 to 134, and the inverter circuit 135. Reference numeral 136 is a register. This register 1
36 is selector bus data bus (SD〓〓0)1
A data input section that inputs the data on 26, an input enable terminal IE, and an output enable terminal OE.
and an output section. However, register 1
36 is a selector bus data bus (SD 〓〓0) Holds the data on 126. This selector bus data bus (SD〓〓
0) The data on 126 is stored in the selector bus driver/receiver circuit 137 during the control operation by the microcomputer (numeral 29 in FIG. 2).
The data transmitted from the bus (DLN〓〓0) 138 through the selector bus driver/receiver circuit 139 during the control operation period of the selector bus control circuit 31 are transmitted from the bus (DLN〓〓0) 140 through the be. The data held in the register 136 is transferred from its output to the selector bus data bus ( SD〓〓0)126 is output. On the other hand, code 141 is a device number output signal
This is a NAND gate circuit that receives ADRS0, command output signal CMD0, and data available signal DAV0 as inputs. This NAND gate circuit 1
41 is an input enable terminal of the register 136 that outputs a "1" level output signal during a period when any of the above signals is active ("0" level).
Give to IE. Reference numeral 142 is also a NAND gate circuit, which receives the output signal of the NAND gate circuit 134, the data request signal DR0, and the interrupt acknowledge signal ACK0, respectively. This NAND gate circuit 142 generates an output signal of "1" level during a period when any of the above-mentioned signals is active ("0" level). The output signal and test signal of this NAND gate circuit 142
TEST1 is input to each input terminal of the NAND gate circuit 143. In the test mode, the NAND gate circuit 143 sends the output signal of the "0" level to the output enable terminal of the register 136 while the output signal of the NAND gate circuit 142 is at the "1" level.
Give to OE. As a result, the register 136 sends out its held data as described above. As already explained, the output signal of the NAND gate circuit 134 is "0" when the microcomputer 29 outputs the active ("0" level) status request signal SRQ0 during the control operation period.
It is at the "1" level when the selector bus control circuit 31 outputs the active ("0" level) status request signal SRQ0 during the control operation period. That is, the status request signal SRQ0 outputted by the selector bus control circuit 31 during the control operation period has no effect on the register 136. Register 13 above
6. The functions shown in (3) and (4) above are realized by the NAND gate circuits 141 to 143 (NAND gate circuit 134 and inverter circuit 135). Reference numeral 144 designates a flip-flop having the transfer end signal EDBYTE0 as a set input and the interrupt acknowledgment signal ACK0 as a reset input. This flip-flop 144 is set by the active ("0" level) transfer end signal EDBYTE0 applied from the selector bus control circuit 31, and outputs a "1" level output signal. Furthermore, the flip-flop 144 is reset by the active ("0" level) interrupt acknowledge signal ACK0, and outputs an output signal of the "0" level. Reference numeral 145 is a NAND gate circuit which receives the output signal of the flip-flop 144 and the test signal TEST1. This NAND gate circuit 14
Reference numeral 5 outputs an active ("0" level) interrupt signal ATN0 only while the output signal of the flip-flop 144 inputted during the test mode is at "1" level. Further, the NAND gate circuit 145 is connected to the flip-flop 14
The interrupt signal ATN0 is cleared (inactive) in response to the output signal of No. 4 transitioning to the "0" level. The flip-flop 144 and the NAND gate circuit 145 realize the function shown in (5) above. Next, the operation of the simulator 43 shown in FIG. 11 will be explained with reference to FIG. 2 as well. For example, it is assumed that the microcomputer 29 outputs the test start signal STEST0 at the "0" level. As a result, the flip-flop 121 is set,
“1” level test signal from its output terminal
Output TEST1. The simulator circuit 43 is then enabled and the selector channel is placed in test mode. In this state, the NAND gate circuit 122 outputs the device number output signal ADRS0, command output signal CMD0, data available signal DAV0, and data request signal.
DR0, status request signal SRQ0, and interrupt acknowledge signal ACK0 are each input. Then, in the NAND gate circuit 122, any one of the above control signals is active (“0” level).
During a certain period, a binary signal of "1" level is output. The NAND gate circuit 124 receives the output signal of the NAND gate circuit 122 and the test signal.
TEST1 is entered. Then, the NAND gate circuit 124 is in test mode (test signal
During the period when TEST1 is at “1” level, the inverted signal of the output signal of the NAND gate circuit 122 is sent as the response signal.
Output as SYNC0. That is, the NAND gate circuit 124 outputs the active response signal SYNC0 in response to the input of the active control signal to the NAND gate circuit 122, and outputs the active response signal SYNC0 in response to the input of the active control signal being stopped. Stop output. This realizes the function (1) described above. Next, the operation of the function (2) will be explained. For example, it is assumed that the device number output signal ADRS0 (active) is being applied and the corresponding data (busy time setting data in this embodiment) is being output onto the selector bus data bus (SD〓〓〓0) 126. Device number output signal ADRS0 is register 1
It is input to the load terminal L of No. 25. As a result, the register 125 is set to the selector bus data bus (SD〓
0) Input and hold the data on 126. Thereafter, the microcomputer 29 performs setup operations such as sending commands and sending a transfer start address, and further sets up the selector bus control circuit 31.
It is assumed that the transfer start command signal STRF0 is outputted and the control operation is moved to the selector bus control circuit 31. As a result, the selector bus control circuit 31 receives the status request signal through the driver circuit 123.
Send SRQ0 (active). At this time, an active response signal is generated from the NAND circuit 124 in response to the active status request signal SRQ0.
As mentioned above, SYNC0 is returned.
The status request signal SRQ0 is input to the clock input terminal CK of the flip-flop 127. Flip-flop 127 is a status request signal.
The state of the test signal TEST1 (in this embodiment, "1" level) at the falling edge of SRQ0 (state transition from inactive to active) is latched. The latch data of flip-flop 127 and basic clock signal CLK1 are input to AND gate circuit 128, respectively. Then, the AND gate circuit 128 causes the flip-flop 127 to be "1".
It is opened while the level test signal TEST1 is latched, and the basic clock signal CLK1 is output as is. The output signal of the AND gate circuit 128 is input to the clock input terminal CK of the counter 129. The counter 129 is an AND gate circuit 128
The count output is counted up by "1" in response to the rise of the output signal, that is, the basic clock signal CLK1. The count output of the counter 129 and the data held in the register 125 (busy time setting data) are both input to a comparator 130. The comparator 130 outputs a binary signal of "1" level until the count output of the counter 129 matches the data held in the register 125. When the count output matches the held data, the comparator 130 outputs a binary signal of "0" level. The output signal of this comparator 130, the test signal TEST1, and each NAND gate circuit 13
Each of the 3,143 output signals is input to a NAND gate circuit 131. The NAND gate circuit 131 then operates the comparator 130 in the test mode.
output is at “1” level, and the selector bus control circuit 31 is active status request signal
Active (“0”) while outputting SRQ0.
outputs a binary signal (busy signal SD040) to the selector bus data bus (SD〓〓0) 126, and remains inactive (“1” level) during the period when the output of the comparator 130 is at “0” level. The binary signals are also connected to the selector bus data bus (SD〓〓〓
0) Output onto 126. In this way, the busy time of the input/output device can be simulated. That is, the function (2) described above is realized. This busy time setting is based on the 8-bit wide selector bus data bus (SD
〓〓0)126 In this embodiment,
Up to 2 ⁸ (=256) levels are possible. Here, each level (busy time) is the basic clock signal.
It shows a time that is an integral multiple of one cycle of CLK1. That is, according to the embodiment of the present invention, the busy time of an input/output device can be set up to 256 levels by the firmware of the microcomputer 29, and simulations from low-speed input/output devices to high-speed input/output devices are possible. Become. The selector bus control circuit 31 outputs a busy signal.
When SD040 becomes inactive (level "1"), the status request signal SRQ0 is made inactive, and it is determined that the input/output device is ready for data exchange, and the following operations are performed. That is, in the case of data output to an input/output device, the selector bus control circuit 31 activates the data available signal DAV0 and sends out the data. Further, in the case of a data input request from an input/output device, the selector bus control circuit 31 activates the data request signal DR0. As a result, in either case, the NAND gate circuit 133 sets its output signal to "0". The output signal of the NAND gate circuit 133 is input to the reset input terminal CLR of the flip-flop 127 and the counter 129, respectively.
Both are in the reset state. Next, when the busy signal SD040 becomes inactive (level "1"), the selector bus control circuit 31 activates the data available signal DAV0, and the selector bus control circuit 31 activates the data available signal DAV0 and transfers predetermined data to the input/output device. Data bus (SD
〓〓0) 126 will be explained. At this time, it is assumed that the number of transfer data bytes is specified as 4 bytes. The data available signal DAV0 is input to the NAND gate circuit 141, so that the output signal of the NAND gate circuit 141 changes from the "0" level to the "1" level.
Transition to a level. This NAND gate circuit 141
The output signal is input to the input enable terminal IE of the register 136. The register 136 inputs and holds predetermined data sent onto the selector bus data bus (SD〓〓〓0) 126 in response to the state transition of the output signal of the NAND gate circuit 141 from the "0" level to the "1" level. . In this way, the data (output information) sent for transfer to the input/output device can be held. That is, the function (3) described above is realized. When the above operation is repeated and the transfer of 4 bytes is completed, the selector bus control circuit 31 sends the transfer end interrupt signal ETRF0 to the microcomputer 29 as described above, and also sends the transfer end signal EDBYTE0 to the input/output device. Send out. As a result, control of the selector bus 36 is transferred to the microcomputer 29 again. The transfer end signal EDBYTE0 is set into the flip-flop 144. This causes flip-flop 144
enters the set state, causing its output signal to transition from the "0" level to the "1" level. The output signal of the flip-flop 144 is input to a NAND gate circuit 145 together with the test signal TEST1. In response to the state transition of the output signal of the flip-flop 144, the NAND gate circuit 145 causes its output signal (interrupt signal ATN0) to transition from the "1" level to the "0" level.
In other words, the NAND gate circuit 145 receives the transfer end signal.
This means that the interrupt signal ATN0 is activated in response to EDBYTE0. Microcomputer 29 uses interrupt signal ATN0
When becomes active, it sends an interrupt acknowledge signal ACK0 to the input/output device. This interrupt acknowledge signal
ACK0 is a reset input to flip-flop 144. This puts the flip-flop 144 in a reset state, causing its output signal to transition from the "1" level to the "0" level. The NAND gate circuit 145 responds to the state transition of the output signal of the flip-flop 144 and outputs its output signal (interrupt signal).
ATN0) is caused to transition from the “0” level to the “1” level. That is, the NAND gate circuit 145 outputs the interrupt signal ATN0 in response to the interrupt acknowledge signal ACK0.
This means that it has been cleared (inactive). In this way, the function (5) described above is realized. On the other hand, the interrupt acknowledge signal ACK0 is also input to the NAND gate circuit 142. As a result, the NAND gate circuit 142 causes its output signal to transition from the "0" level to the "1" level. The output signal of the NAND gate circuit 142 is inputted to the NAND gate circuit 143 together with the test signal TEST1. In response to the state transition of the output signal of the NAND gate circuit 142, the NAND gate circuit 143 causes its output signal to transition from the "1" level to the "0" level. The output signal of this NAND gate circuit 142 is the output enable terminal of the register 136.
Entered into OE. Then, the register 136 sends the held data onto the selector bus data bus (SD〓〓〓0) 126 in response to the state transition of the output signal from the "1" level to the "0" level. The above retained data is the data available signal
Of course, this is the predetermined data transferred together with DAV0. In other words, the function (4) above is realized. And microcomputer 2
9 is set to register 1 by interrupt acknowledge signal ACK0.
By checking whether the data read from 36 matches the predetermined data transferred together with the data available signal DAV0, the function of the selector channel itself can be diagnosed. Next, the operation of the channel diagnostic method of the present invention will be explained in more detail. When the simulator 43 is used by a program, the operation of the simulator 43 can be started by specifying the device number as "0" using the SI0 command. When the microcomputer (29 in FIG. 2) learns that the content of the device number register (27 in FIG. 2) is "0", it sends a test start signal STEST0 to the simulator 43 to set it in test mode. In other words, the test start signal STEST0 is applied to the flip-flop 12.
The flip-flop 121 outputs the test signal TEST1 at the "1" level. After that, the microcomputer 29 transfers the number of transfer bytes specified by the CCB to the internal bus (reference numeral 2 in Figure 2).
8) in the counter (38 in FIG. 2), and also sets the start address of the main memory specified by the CCB in the memory address register (24 in FIG. 2). The microcomputer 29 then sends the device data together with the device number output signal ADRS0. This device number output signal ADRS0 is input to the NAND gate circuit 141, and the register 136 holds the data on the selector bus data bus (SD〓〓〓0) 126 according to this output signal. Next, the microcomputer 29 sends out a data request signal DR0. This data request signal DR0 is input to the NAND gate circuit 142. The output signal of the NAND gate circuit 142 is input to the NAND gate circuit 143 together with the test signal TEST1, and this output signal causes the register 136 to send the held data onto the selector bus data bus (SD〓〓0) 126. The microcomputer 29 reads this data and checks whether it matches the sent data. After that, the microcomputer 29 outputs a command output signal CMD0,
The data available signal DAV0 is sent out along with the corresponding data. It is clear that this data is held in register 136 as before. Then, the microcomputer 29 reads and checks the data held in the register 136 as described above. In this case, reading of data corresponding to command output signal CMD0 is performed by status request signal STRQ0, and reading of data corresponding to data available signal DAV0 is performed by interrupt acknowledge signal ACK0. In this way, the input/output control function of the selector channel can be confirmed. Since this function check of the selector channel is performed by self-diagnosis as described above, early detection of failures and early recovery are expected. When the above diagnostic operation is completed normally, the microcomputer 29 sends out predetermined data (busy time setting data) together with the device number output signal ADRS0. As a result, the above data is held in register 125 and register 136, respectively. The microcomputer 29 then sends a transfer start command signal STRF0 to the selector bus control circuit 31.
As a result, input/output control is performed by the selector bus control circuit 3.
Move to 1. The selector bus control circuit 31 first sends out a status request signal SRQ0. Thereafter, data transfer between the simulator 43, the high-speed bus (reference numeral 21 in FIG. 2), and the main storage device is performed in accordance with the procedure described above. When the data transfer is completed, a transfer end interrupt signal is sent from the selector bus control circuit 31.
ETRF0 is sent to the microcomputer 29 through the end signal line (32 in FIG. 2), and the transfer end signal EDBYTE0 is sent to the simulator 43.
sent to. As a result, input/output control is transferred from the selector bus control circuit 31 to the microcomputer 29 again. Flip-flop 1 in simulator 43
44 and the NAND gate circuit 145 operate in response to the active transfer end signal EDBYTE0 as described above, and the interrupt signal ATN0 output from the NAND gate circuit 145 becomes active. The microcomputer 29 sends an interrupt acknowledge signal ACK0 to the simulator 43 when the interrupt signal ATN0 becomes active. This active interrupt acknowledge signal ACK0 is input to the NAND gate circuit 142. As mentioned above, the register 136 transfers the held data to the selector bus data bus (SD).
〓〓0) Send on 126. The microcomputer 29 compares the data sent (read) from the register 136 with the transferred data to diagnose the function of the selector channel. In this embodiment, the series of input/output control operations described above are performed by changing the busy time (busy time setting data) and transfer data (data sent together with the data available signal DAV0) one by one (for example, the busy time is (In the example, up to 256 levels can be set)
When an error is recognized as occurring, the busy time at that time is transferred to the CCB and the process is terminated. This busy time within the CCB is determined by a program. In this way, simulations can be performed from low-speed input/output devices to high-speed input/output devices. Additionally, this simulation allows for easy testing of the limits of the timing margin of high-speed buses, and by accumulating these test data, it becomes possible to evaluate reliability data in time series and to determine whether preventive maintenance is appropriate. As described in detail above, according to the present invention, it is possible to provide a diagnostic method in a selector channel that can efficiently diagnose its own functions, enable early detection of failures, and enable early recovery. Further, according to the present invention, performance evaluation and reliability evaluation in a channel can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a connection system for a general direct memory access device, and FIGS. 2 to 11 show an embodiment of the present invention.
The figure is a block diagram showing the configuration of the selector channel.
Figure 3 is a system configuration diagram of a data processing device that uses the selector channel shown in Figure 2, and Figure 4 is a system configuration diagram of a data processing device that uses the selector channel shown in Figure 2.
A block diagram showing the vicinity of the arithmetic and control unit of the central processing unit in the figure, FIG. 5 is a diagram showing the program status word, FIG. 6 is a diagram for explaining channel control operation, and FIG. 7a is a diagram showing the SIO
The format for executing the instruction, Figure 7b, is
Format for executing TIO instruction, Figure 8 shows the channel control block, Figure 9
The figure shows the channel control word in the channel control block. Figure 10 is a block diagram showing the basic configuration of the selector channel.
The figure is a detailed configuration diagram of a simulator according to the present invention. 21...High speed bus, 22...High speed bus driver/receiver circuit, 24...Memory address register, 25...Write data register, 26...
Read data register, 27...Device number register, 28...Internal bus, 29...Microcomputer, 31...Selector bus control circuit,
34...I/O bus, 35, 37...Selector bus driver/receiver circuit, 36...Selector bus, 38...Counter, 40...Command register, 41...Random access memory, 42...
High-speed bus control circuit, 43...Simulator, 12
1,144...flip flop, 122,12
4...NAND gate circuit, 125, 136...Register, 127...(D type) flip-flop,
129...Counter, 130...Comparator.

Claims (1)

[Scope of Claims] 1. A microcomputer that reads and decodes channel control words stored in a main memory, sends input/output operation commands, and is released from input/output control operations until the end of the operation; a bus control circuit that transfers data between the input/output device and the main storage device according to an output operation command, and sends a transfer end interrupt signal to the microcomputer after the data transfer is completed; The control signal sending means sends out a corresponding control signal in response to a control signal sent from the bus control circuit, and includes a register internally holding time setting data sent from the microcomputer, and a register from the bus control circuit. a counter that starts time counting in response to a status request; and means that compares the count value of this counter with the time setting data and, when they match, sends a response signal indicating that transfer is possible to the bus control circuit. control signal transmitting means having a control signal transmitting means for retaining data transmitted together with a control signal indicating data output from the microcomputer or bus control circuit in a test mode, and using the retained data to indicate an input request from the microcomputer or bus control circuit; and means for transmitting the control signal to the microcomputer or the bus control circuit in response to the control signal, and for performing self-channel function diagnosis and performance evaluation based on the control signal and data transmitted by the respective means. Diagnostic method in characteristic channels.