JPS6230968A - Current-voltage conversion circuit - Google Patents
Current-voltage conversion circuitInfo
- Publication number
- JPS6230968A JPS6230968A JP16864485A JP16864485A JPS6230968A JP S6230968 A JPS6230968 A JP S6230968A JP 16864485 A JP16864485 A JP 16864485A JP 16864485 A JP16864485 A JP 16864485A JP S6230968 A JPS6230968 A JP S6230968A
- Authority
- JP
- Japan
- Prior art keywords
- current
- output
- transistor
- voltage conversion
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、pinボトダイオードや光電子増倍管等から
の微弱な出力電流を、高い周波数に至るまで安定して高
い変換効岸で電圧に変換できる電流電圧変換回路に関す
る。[Detailed Description of the Invention] [Field of Industrial Application] The present invention converts a weak output current from a pin bottom diode, a photomultiplier tube, etc. into a voltage with a stable high conversion efficiency up to high frequencies. This invention relates to a current-voltage conversion circuit that can convert current to voltage.
第2図は従来の電流電圧変換回路の一例を示し、図中、
1はホトダイオード、2は演算増幅器、3は帰還抵抗R
f、4は演算増幅器2の一方の入力端子、5は演算増幅
器2の他方の入力端子、6は変換電圧Voの出力端子で
ある。ここで電流−電圧変換係数は、Vo/1p=−R
fで与えられる。FIG. 2 shows an example of a conventional current-voltage conversion circuit.
1 is a photodiode, 2 is an operational amplifier, and 3 is a feedback resistor R.
f, 4 is one input terminal of the operational amplifier 2, 5 is the other input terminal of the operational amplifier 2, and 6 is the output terminal of the converted voltage Vo. Here, the current-voltage conversion coefficient is Vo/1p=-R
It is given by f.
しかし、実際の回路では、ホトダイオードの接合容量や
、ホトダイオードから演算増幅器に至る配線容量などよ
りなる入力容量C8が存在し、この入力容量Csと帰還
抵抗Rfにより、fp = 2 πRf−Csなる周波
数に於いてポールを作る。このポール周波数が、演算増
幅器2の帯域幅より低い範囲内にある場合、この電流電
圧変換系の位相余裕が少なくなり、リンギングあるいは
発振を生ずる。However, in an actual circuit, there is an input capacitance C8 consisting of the junction capacitance of the photodiode, the wiring capacitance from the photodiode to the operational amplifier, etc., and this input capacitance Cs and the feedback resistance Rf cause the frequency to become fp = 2 πRf - Cs. Make a pole. If this pole frequency is within a range lower than the bandwidth of the operational amplifier 2, the phase margin of this current-voltage conversion system decreases, causing ringing or oscillation.
このように、入力容量C3によりポールが低い周波数で
発生した場合、Rfに並列に補償容量Cfを(=j加し
て、動作の安定を図るのが;、゛L未来−的に行われて
来た手法であるが、このようにすると、結局、電流電圧
変換系の帯域幅が狭められることになり、動作速度を低
下させる。In this way, when a pole is generated at a low frequency due to the input capacitor C3, a compensating capacitor Cf (=j) is added in parallel to Rf to stabilize the operation. However, if this method is used, the bandwidth of the current-voltage conversion system will be narrowed, and the operating speed will be reduced.
本発明は、微少電流源の入力容量が演算増幅器の帰還抵
抗と協働して、比較的低い周波数でポールを生成しない
ようにした電流電圧変換回路を提供することを目的とす
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a current-voltage conversion circuit in which the input capacitance of a minute current source cooperates with the feedback resistance of an operational amplifier to prevent poles from being generated at relatively low frequencies.
元来この発明が対象とする電流電圧変換回路の場合、変
換係数は十分大きくなければならないから、演算増幅器
の帰還抵抗を小さくすることばできず、従って、微少電
流源からの入力容量との協同で位相余裕が少なくなるの
も止むを得ない。このことから増幅器側で改変する余地
は殆ど無く、上記問題点を解決するためには、増幅器側
と微小電流源側の間に、入力容量と帰還抵抗が協働する
のを阻止するような手段を挿入するのが有効と考えられ
た。In the case of the current-voltage conversion circuit originally targeted by this invention, the conversion coefficient must be sufficiently large, so it is impossible to reduce the feedback resistance of the operational amplifier. It is unavoidable that the phase margin decreases. For this reason, there is almost no room for modification on the amplifier side, and in order to solve the above problem, a means to prevent the input capacitance and feedback resistance from working together between the amplifier side and the minute current source side is needed. It was considered effective to insert .
周知の如く、ヘース接地トランジスタでは、エミッタ副
入力インピーダンスは極めて低く、コレクタ側出力イン
ピーダンスは極めて高くなって、微少電流源側から増幅
器側に対するバッファとして利用できることに着目し、
微少電流源と増幅器との間に、バイアス電流により適当
な動作点を選定したベース接地トランジスタを挿入する
こととした。しかし、これだけでは、バイアス電流によ
る出力のオフセットが生しているから、同様なバイアス
電流を与えたベース接地トランジスタのコレクタ出力を
演算増幅器の(従来接地していた)他方の入力端子に接
続し、演算増幅器を差動増幅器として動作させ、前記出
力オフセットを補償させることにした。As is well known, in a grounded transistor, the emitter side input impedance is extremely low and the collector side output impedance is extremely high, so we focused on the fact that it can be used as a buffer from the micro current source side to the amplifier side.
We decided to insert a common-base transistor whose operating point was selected appropriately using a bias current between the minute current source and the amplifier. However, this alone causes an offset in the output due to the bias current, so connect the collector output of the common-base transistor to which a similar bias current is applied to the other input terminal of the operational amplifier (which was conventionally grounded). It was decided to operate the operational amplifier as a differential amplifier to compensate for the output offset.
第1図は本発明一実施例を示し、2aは差動増幅器、7
は微少電流を入力させるためのベース接地トランジスタ
、8はトランジスタ7のバイアス電流による出力オフセ
ットを補償するためのベース接地トランジスタ、9.1
0は1−ランジスタフ、8のエミッタバイアス用(数M
Ωの)抵抗、11はオフセント補償用抵抗で、その他の
符号は第2図の場合と同様である。FIG. 1 shows an embodiment of the present invention, in which 2a is a differential amplifier, 7
8 is a common base transistor for inputting a minute current; 8 is a common base transistor for compensating for the output offset due to the bias current of transistor 7; 9.1
0 is for 1-Langistav, 8 for emitter bias (several M
Ω) resistor, 11 is an offset compensation resistor, and other symbols are the same as in FIG.
このような回路にした結果、実際に、配線等による入力
容量の影響が演算増幅器に及ばなくなり、演算増幅器帯
域内ではポールが生じない:演算増幅器人力のイマジナ
リショートにより、トランジスタの負荷インピーダンス
はゼロに近く、コレクタ接合による高域遮断周波数が高
い:ベース接地トランジスタの入力インピーダンスは低
く、入力容量の影響(入力容量による高域遮断、入力容
量の変化による動作特性の変動)が少ない:従って、配
線容量、配線長の悪影響が生じ難い:などの効果が認め
られた。As a result of creating a circuit like this, the influence of the input capacitance due to wiring etc. actually does not affect the operational amplifier, and no poles occur within the operational amplifier band: Due to the imaginary short circuit of the operational amplifier, the load impedance of the transistor becomes zero. The high-frequency cutoff frequency due to the collector junction is high: The input impedance of the common-base transistor is low, and the influence of input capacitance (high-frequency cutoff due to input capacitance, fluctuation in operating characteristics due to changes in input capacitance) is small: Therefore, wiring capacitance The following effects were observed: , the negative effects of wiring length are less likely to occur.
以上説明したように本発明によれば、比較的簡単な回路
で、極めて安定して良好な変換効率で高速動作する電流
電圧変換回路が得られる。As described above, according to the present invention, it is possible to obtain a current-voltage conversion circuit that is extremely stable and operates at high speed with good conversion efficiency using a relatively simple circuit.
第1図は本発明一実施例の回路図、第2図は従来の微少
電流源用電流電圧変換回路側図である。
1−ホトダイオ−じ、 2−演算増幅器、2a−差動
増幅器、 3−帰還抵抗、 4.5−演算増幅器の入力
端子、 6−変換電圧の出力端子、7.8−ベース接地
トランジスタ、 9.10〜エミツタバイアス用抵抗
、 11−オフセント補償用抵抗、vo−変換出力電
圧、 +vb−ホトダイオード逆バイアス用電圧、 +
Vcc −回路電源電圧。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a side view of a conventional current-voltage conversion circuit for a minute current source. 1-photodiode, 2-operational amplifier, 2a-differential amplifier, 3-feedback resistor, 4.5-input terminal of operational amplifier, 6-output terminal of converted voltage, 7.8-base common transistor, 9. 10 - Resistor for emitter bias, 11 - Resistor for offset compensation, vo - Conversion output voltage, +vb - Voltage for photodiode reverse bias, +
Vcc - circuit power supply voltage.
Claims (1)
を選定したベース接地トランジスタのエミッタに接続し
、そのコレクタ出力を差動増幅器の一方の入力端子に接
続し、更に上記ベース接地トランジスタのバイアス電流
による出力のオフセットを補償するために、同様なバイ
アス電流を与えたベース接地トランジスタのコレクタ出
力を前記差動増幅器の他方の入力端子に接続し、これら
トランジスタに、増幅器の帰還抵抗と電流源側容量の協
同によるポール生成を阻止するバッファ作用を行わせる
ようにしたことを特徴とする電流電圧変換回路。The output of the minute current source is connected to the emitter of a common-base transistor whose operating point has been selected appropriately using a bias current, and its collector output is connected to one input terminal of a differential amplifier, and the bias current of the common-base transistor is In order to compensate for the output offset due to 1. A current-voltage conversion circuit characterized in that a buffering action is performed to prevent pole generation due to the cooperation of the current-voltage conversion circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16864485A JPS6230968A (en) | 1985-08-01 | 1985-08-01 | Current-voltage conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16864485A JPS6230968A (en) | 1985-08-01 | 1985-08-01 | Current-voltage conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6230968A true JPS6230968A (en) | 1987-02-09 |
Family
ID=15871856
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16864485A Pending JPS6230968A (en) | 1985-08-01 | 1985-08-01 | Current-voltage conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6230968A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01144831U (en) * | 1988-03-30 | 1989-10-04 | ||
JP2008301083A (en) * | 2007-05-30 | 2008-12-11 | Mitsubishi Electric Corp | Differential-signal generating circuit |
-
1985
- 1985-08-01 JP JP16864485A patent/JPS6230968A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01144831U (en) * | 1988-03-30 | 1989-10-04 | ||
JPH0516508Y2 (en) * | 1988-03-30 | 1993-04-30 | ||
JP2008301083A (en) * | 2007-05-30 | 2008-12-11 | Mitsubishi Electric Corp | Differential-signal generating circuit |
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