JPS6230076Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a rhythm generating device that selects a desired number of rhythm patterns for each measure during the performance of a song and automatically sounds a plurality of sets of these patterns in sequence. .

When a conventional rhythm generator selects a certain rhythm, it typically plays that rhythm pattern repeatedly throughout a song. However, when people actually play the rhythm, it is rare for them to perform one song with the same pattern, and it is normal to add similar types of variation rhythms here and there. The rhythm of the generator could not escape the feeling of monotony.

Recently, in order to eliminate this monotony, devices having variations have been considered, but the movement of the plurality of variations has been performed automatically at equal time intervals or manually switched. However, although the former method is more relaxed than before, it still feels monotonous because the same cycle is repeated, and the latter method is difficult to operate when playing with both hands and feet.

The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a rhythm generating device that can freely select rhythm patterns and repetition numbers, combine them in sequence, and automatically generate sounds.

In order to achieve the above object, the rhythm generating device of the present invention includes a rhythm clock generator, a first address counter that inputs clock pulses from the rhythm clock generator and outputs an address signal that goes around in a predetermined number of measures, and a plurality of first address counters. a rhythm pattern storage section in which each storage unit stores a rhythm pattern for a predetermined measure, and the rhythm pattern is read out in response to an address signal from the first address counter;
a bar counter for counting the number of bars by carrying the address counter; and designation information for alternatively designating storage units in the rhythm pattern storage section in the order of address numbers as the song progresses.
A specified information storage circuit that stores the rhythm pattern in the decimal code and one storage unit of the rhythm pattern storage section that is alternatively specified in the specified information storage circuit, the number of repeated measures to be read out is stored as an address number as the song progresses. a bar count storage circuit that sequentially stores the number of measures in binary code; a decoder that selectively designates one storage unit of the rhythm pattern storage section based on a binary code output signal of the designation information storage circuit;
A comparator that outputs a match signal when the output signal of the measure counter and the measure number storage circuit match, and also resets the measure counter, and a comparator that counts the match signal from the comparator and uses the counted value to output a match signal. The present invention is characterized by comprising a second address counter that sequentially reads each address of the designation information storage circuit and the measure number storage circuit.

The present invention will be described in detail below with reference to examples.

The figure is an explanatory diagram showing the configuration of an embodiment of the present invention. In the figure, the rhythm pattern storage unit ROM
(RAM) ₉₁ to _9o store different rhythm patterns for each bar and output them to the sound source circuit according to the address of the rhythm clock. Which ROM of these
(RAM) 9 ₁ to 9 _o to be selected is stored in advance in the specified information storage circuit RAM (ROM) 6, and the number of measures of the rhythm pattern stored in these RAM (ROM) 6 is stored in advance. It is assumed that the number of bars is stored in the bar number storage circuit RAM (ROM) 7.

The rhythm clock from the rhythm clock generator 1 is input to the address counter 2, and the ROM (RAM)
The addresses are ₉₁ to _9o . For example, if address counter 2 is set to 24 base, ROM (RAM) 9 ₁
The number of bits for ~ _9o is 24×m bits for the number of sound sources m. If we define 24 clocks as one measure, then 24
The measure counter 3 advances by one bit every clock, and is compared with the output number of the measure number storage circuit RAM (ROM) 7 by a comparator 5 until they match. When a match occurs, a match signal from the comparator 5 is input to the address counter 4 for counting, and the counted value is sent to the designated information storage circuit RAM (ROM) 6 and the measure number storage circuit.
The data is sent to RAM (ROM) 7 and the contents of each are read out sequentially. The address counter 4 has the same base number as the number n of changes in the pattern during one song, that is, the number n of words in the bar number storage circuit RAM (ROM) 7.

Output to the sound source circuit is specified information storage circuit RAM
The contents of (ROM) 6 are code-converted by decoder 8,
The contents of ROM (RAM) 9 ₁ to 9 _o are read and sent out.

The operation of the above-mentioned configuration will be specifically explained below.

Now, when I start playing, up to 2 measures are ROM9 _1.
The number of measures is 2 with the rhythm pattern stored in
The next three measures are the same type of variation rhythm pattern stored in _ROM92 , and the number of measures is 3.
Furthermore, the next bar is a rhythm pattern in the ROM ₉₁ , and the number of bars is set to 1 or less, and is stored in the designation information storage circuit RAM6 and the bar number storage circuit RAM7.

Next, the performance is started, and the address counter 2 counts the rhythm clocks from the rhythm clock generator 1 and inputs the addresses into the ROMs ₉₁ to _9o .

At that time, it is assumed that a signal (0, 0, 0) is output from the address counter 4 to the designated information storage circuit RAM6, and the signal (0, 0, 0) is outputted from the address counter 4 via the decoder ₈ to the ROM91.
A signal is output to operate the When the address counter 2 counts 24 clocks, it inputs one pulse to the bar counter 3. When the address counter 2 counts 24 clocks again, one more pulse is input to the measure counter 3, and the signal (0, 1,
0) is output. The bar number storage circuit 7 initially receives the signal (0, 0, 0) from the address counter 4 and outputs the signal (0, 1, 0) to the comparator 5. Then, the output signals of the bar number storage circuit RAM7 and the bar counter 3 match, and one pulse of the matching signal is output to the address counter 4, and the output signal is set to (0, 0, 1), and the bar counter 3 is reset. Output a signal. Further, the bar number storage circuit RAM7 inputs the signal (0, 0, 1) of the address counter 4 and outputs the signal (0, 1, 1).

The designated information storage circuit RAM6 outputs signals (0, 0, 1) from the address counter 4 to operate the _ROM92 , and the rhythm pattern in the _ROM92 is outputted to the sound source circuit according to the address signal from the address counter 2. Ru.

Next, 3 pulses are input from the address counter 2 to the bar counter 3 and the signal (0, 1, 1) is output, which matches the signal of the bar number storage circuit RAM 7, so the match signal is input to the address counter 4, and the signal (0, 1, 1) is output. Proceed with counting. As a result, the measure number memory circuit RAM7 outputs a signal (0, 0, 1),
The designated information storage circuit RAM6 is
Operate _ROM93 .

Similar operations are subsequently performed in sequence.

In the embodiment, the rhythm pattern storage section 9 ₁ -
As shown in 9 _o as ROM (RAM), fixed memory (ROM) is normally used, but random access memory (RAM) may also be used. On the other hand, the designation information storage circuit 6 and the measure number storage circuit 7
Typically, random access memory (RAM) is used, as shown as RAM (ROM), but fixed memory (ROM) may also be used.

In addition, in the embodiment, a plurality of rhythm pattern storage units 9
Although ₁ to 9 _o were used, they may be combined into one.

As explained above, according to the present invention, while playing one song, the desired rhythm pattern for each measure is selected for the desired number of measures, and information on multiple sets of these is stored in advance in the rhythm pattern designation information storage circuit. The number of bars is stored in a bar number storage circuit, and the corresponding rhythm is sequentially sounded based on the output signal. As a result, the type of rhythm pattern and the number of repeated measures can be freely changed in advance, so that it is possible to perform a rhythm performance with a desired variety, as opposed to the monotony of conventional rhythm generators.

[Brief description of the drawings]

The figure is an explanatory diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a rhythm clock generator, 2 and 4 are address counters, 3 is a measure counter, 5 is a comparator, 6 is a specified information storage circuit, and 7 is a 8 is a decoder, and 9 ₁ to 9 _o are rhythm pattern storage units.

Claims (1)

[Claims for Utility Model Registration] A rhythm clock generator 1, a first address counter 2 that receives clock pulses from the rhythm clock generator 1 and outputs an address signal that goes around in a predetermined number of bars, and a plurality of storage units. a rhythm pattern storage section 9 in which each storage unit stores a rhythm pattern for a predetermined measure, and the rhythm pattern is read out in response to an address signal from the first address counter 2; A bar counter 3 that counts the number of bars by carrying the address counter 2, and designation information 2 for selectively designating storage units in the rhythm pattern storage section 9 in the order of address numbers as the song progresses. The number of readout repetition measures of one storage unit of the specified information storage circuit 6 which stores in decimal code and the rhythm pattern storage section 9 that is alternatively specified by the specified information storage circuit 6 is calculated according to the progress of the song. one of the rhythm pattern storage sections 9 based on the binary code output signal of the designation information storage circuit 6;
Decoder 8 for selectively specifying two storage units
and a comparator 5 that outputs a match signal when the output signal of the measure counter 3 and the measure number storage circuit 7 match and resets the measure counter 3; and a comparator 5 that counts the match signals from the comparator 5. , a second address counter 4 that sequentially reads each address of the designation information storage circuit 6 and the bar count storage circuit 7 according to the counted value.