JPS62298089A - Charge accumulating type semiconductor memory - Google Patents

Abstract

PURPOSE:To minimize greatly the noise of a capacity bonding due to an inter- layer parasitic capacity between a data line and a plate electrode by fixing the electric potential of a sub-data line of non-selection. CONSTITUTION:When sub-data lines 2A and 3A are connected to main data liens 2 and 3, switches 5A and 6B are closed and 6A and 5B are closed. Thus, only the sub-data liens 2A and 3A dependent on a main data line are respectively connected to the main data lines 2 and 3 and other sub-data line is connected to a fixing electric potential VD. When a sub-data line is divided, a sub-data line changed by the same electric potential as the main data line is only one and the electric potential of a remaining n-1 number of the sub-data line is fixed. Since the line to capacity-bond mainly with a plate is the sub-data line, the noise of the capacity bonding can be made into about 1/n.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention has a large number of cells that store information using charge carriers in a semiconductor, and the information stored in the cells is Random access memory (RAM) has a mechanism for reading and writing information to cells according to specified address information.
In particular, the present invention relates to an ultra-highly integrated RAM having a cell array configuration that accurately stores and accumulates a small amount of signal charge.

[Conventional technology]

A pair of data in so-called one-transistor type dynamic RAM (T r r) RAM, which is well known as a RAM that uses charge carriers in a semiconductor as an information source, and uses one transistor and one capacitor as storage elements. FIG. 2 shows a conventional example of the structure of a memory cell array shown by lines.

In FIG. 2, 10 is an MIS transistor (MIST) that becomes a word gate, 11 is a capacitor that stores signal charge carriers that is an information source, 21 is a memory cell consisting of one of these capacitors and one M/S transistor, and 22 ,23
24 is a data line that transmits charge carriers, and 24 is a word line that opens and closes the word gate by addressing in the incoming direction.
Reference numeral 28 indicates a peripheral circuit that detects signal charges and writes data into the memory cells, 29 indicates a plate forming an electrode at one end of the storage capacitor, and 15 indicates an interlayer parasitic capacitance that is generated parasitically between the data line and the plate.

A layout diagram and a structural sectional view of this memory cell section are shown in FIGS. 4 and 3, respectively.

In the fourth time, 40 is an electrically active region layer, 43 is a first gate layer forming a plate electrode, 44 is a second gate layer forming a word gate of a memory cell sensor, 46
4 is a first wiring layer constituting a data line, and 47 is a contact layer for electrically connecting the electrically active region to the first wiring layer. 48, where the two layers 40 and 43 overlap, corresponds to a storage capacitance portion of one memory cell, and 49, where the two layers 40 and 44 overlap, corresponds to a word gate portion, respectively.

In addition, a structural cross-sectional view of the a-a' portion corresponding to this is shown in FIG. Gate,
35 is an insulator, and 36 is a first wiring layer.

In such a conventional dynamic memory cell, the overlapping portion 50 between the first gate portion and the second wiring layer creates a parasitic capacitance between the plate and the data line.

[Problem that the invention seeks to solve]

In the above conventional technology, when the potential of the data line fluctuates when reading or writing information from a memory cell, large capacitive coupling noise is superimposed on the plate due to the interlayer parasitic capacitance. There was a problem.

In conventional dynamic memories, the capacitance Cg of the signal charge storage section is designed to be as large as possible in order to ensure a signal-to-noise ratio (S/N ratio) for stable read operations.

However, as memories become more highly integrated, the storage capacity per memory cell tends to decrease, making it difficult to secure a sufficient signal amount. In addition, for example, as in a semiconductor multilevel memory device (described in Japanese Patent Laid-Open No. 60-13398 and Japanese Patent Application No. 58-242021), the accumulated charge is divided and read and written, and each memory cell has three or more values. Memories of T! In ultra-highly integrated memory devices that perform multiplication, it is particularly required to accurately detect small signal amounts.

As described above, in order to realize a highly integrated dynamic memory device, a technique for reducing the amount of noise itself is essential.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory array configuration that minimizes noise generated in a memory cell array, particularly capacitive coupling noise caused by interlayer parasitic capacitance between a data line and a plate electrode.

[Means for solving intervening vertices]

In order to solve the above problems, in the present invention, the data line is configured with one main data line and a plurality of subordinate data lines, and the data line is configured to have one main data line and a plurality of sub data lines subordinate to it. It is limited to only the main data line and one sub data line. In addition, by arranging the sub data line between the main data line and the plate and fixing the potential of the unselected sub data line, the structure (shield structure) can almost eliminate the coupling capacitance between the main data line and the plate. And so.

An example of improving the performance of dynamic memory by dividing data lines into smaller pieces is given in (]) International Solid State Circuits Conference (I.N.S.C.C.), Digest of Technical Papers (1984). ) pages 282 to 283 ('84 TSSCCI) of Technical Paperq, pp 28
2-283) and also (2) I Nis Nis C C, Digest
of Technical Papers (1985) No. 242
From page 243 ('85 ISSCCDigeSt
of Technical Papers, pp.
242-243), etc.

In (1), the signal voltage is increased by dividing the data line into multiple parts and reducing the data line capacitance.
No noise reduction structure as in the present invention is adopted. Therefore, although it has a great effect on noise caused by coupling between data lines and coupling between data lines and word lines, it is difficult to suppress noise caused by fluctuations in plate potential as described above. cannot be expected to improve.

In addition, (2) is N) equivalently converting the open data line structure into a folded data a structure to reduce noise, and (ji) reducing the data line capacity to speed up the circuit and reduce power consumption. However, it does not take into consideration capacitively coupled noise as intended by the present invention, and it is not possible to escape from the noise peculiar to an open data line structure.

As mentioned above, it is obvious that the data line division structure in these two examples is different from the present invention both in structure and in its aims.

[Effect]

According to the above structure, the coupling capacitance between the data line and the plate occurs only between the selected sub-data line and the plate. Therefore, for example, if the number (number of divisions) of sub data lines subordinate to the main data line is n, the amount of noise generated can be reduced to 17n.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. Note that in the following embodiments, an n-channel MI is used in the memory cell.
S) - The case where a transistor is used will be explained, but it does not matter whether the channel is n or p, and whether the word gate is M
It does not depend on whether it is an IS type or another type, such as a junction type, and can be applied in exactly the same way as long as it is a dynamic type memory.

(Example 1) FIG. 1 shows an example of the present invention. For simplicity, only two blocks of the sub data lines divided into a plurality of lines are shown here as representatives.

In addition, only two data line pairs of the entire memory array are shown as representatives. ] in the figure is a memory cell, 2 and 3 are a pair of main data lines 2A, 3A and 2B.

3B is a pair of sub data lines, 4 is a word line for opening and closing the word gate, 5A and 5B are connection switches that control the connection between the sub data line and the main data line, and 7 is for an unselected data line. Fixed potential wiring arranged to give a fixed potential, 6A and 6B are potential fixing switches that control the connection between the sub data line and the fixed potential wiring, 8 is for detecting signal charges,
Peripheral circuits responsible for writing information are shown.

The operation of this device will be explained below.

Now, for example, the sub data line pair 2A, 3A is the main data line 2.
, 3, switches 5A and 6B
is closed, and 6A and 5B are closed. As a result, only the sub data lines 2A and 3A subordinate to the main data line are connected to the main data lines 2 and 3, respectively, and the other sub data lines are connected to the fixed potential Vn.

If the sub data line is divided into n parts, only one sub data line changes at the same potential as the main data line, and the remaining n -1
The potential of the book's sub data line should be fixed.

Since it is the sub data line that is mainly capacitively coupled to the plate, the capacitively coupled noise can be reduced to about 1/n.

At the same time, the electrically active region (
The total area of the .tau.1+ or p.sup.1 region) is also approximately 1/Tl.

This reduces the capacitance between the main data line and the board to 1. / n
It is possible to reduce the change in substrate potential (J) (noise) due to a change in the potential of the data line to 1/n.

In addition to reducing various noises, the value of data line capacitance C
Since D can also be reduced to nearly 1/n, the charging and discharging current of the data line can be reduced, and improvements in various characteristics such as improved memory dynamic margin and lower power consumption can be expected.

Furthermore, as a highly sensitive signal detection mechanism, a dynamic memory device using a charge transfer amplifier (Japanese Patent Application No. 58-16
By applying the present invention to No. 3216, Japanese Patent Application No. 59-170417), it is possible to dramatically increase the overall S/N ratio, which can increase the signal voltage and reduce noise at the same time.

Furthermore, when using an n-channel MTS transistor memory cell as in this example, the value of the fixed potential Vo is as follows:
It is desirable to set the value as high as possible. By doing so, spike noise is added to the unselected word lines and the word line
Even when the gate becomes conductive, the stored information can be prevented from being completely lost.

FIG. 5 is a circuit block diagram showing a more specific embodiment of the present invention.

In the figure, 50 is a memory cell block, 52 is a plate electrode, 53 is a block selection signal line, 54 is a potential fixing signal line,
55 is an inverter, 56 is a row address selection circuit, and 57 is a block selection circuit.

In this example, main data lines 2, 3 and sub data lines 2A, 3A
An n-channel MTS transistor is used for the connection switch 5A between the terminals and the potential fixing switch 6A for the sub data line. The connection switch 5A is a block selection signal φSEL arranged in the row direction, and the potential fixing switch 6A is a block selection signal φS formed by an inverter 55.
Each is driven by the inverted signal 7■π of EL. By doing this, by setting φ3EL applied to one block among the plurality of blocks subordinate to the main data line to the selection state S (here, φg+=t, =)−Iigh, the sub data of the selected block is Only the line is connected to the main data line, and a fixed potential Vo is applied to the sub data lines of other non-selected blocks.

The connection switch and potential fixing switch can be configured with one MIS transistor per sub-data line as shown here, and there is almost no increase in the area of a part of the memory cell array, which reduces the degree of integration. There is no risk of inviting it. Also,
As the block selection circuit 57, it is sufficient to simply add a circuit similar to the row address selection circuit that operates based on information on the upper bits of the row address, and the area of the peripheral circuit section does not increase.

As described above, according to the present invention, a large noise reduction effect can be expected by simply providing a small amount of additional circuitry to each of the conventional memory cell array and row address selection circuit.

Note that here we have shown an example in which one n-channel MTS transistor is used as the connection switch and the potential fixing switch, but instead of this, n-channel and P-channel MTS transistors may be connected in parallel. It is obvious that the present invention can be similarly applied even if a so-called Sea Moss (CMO3) switch is used.

6 and 7 are diagrams showing the structure η of the present invention. It is a structural sectional view of the aa' part.

In FIG. 7, 48 is a first wiring layer constituting a sub data line;
Reference numeral 49 denotes a second wiring layer constituting the main data line.

Further, in FIG. 6, 38 is a first wiring layer, 39 is a second wiring layer, and 37 is an insulating film between the eyebrows of the wiring layer.

In this example, the main data line and the sub data line are formed in different wiring layers, and are arranged in parallel so that the main data line partially covers the sub data line.

In this way, the area of overlap between the main data line and the plate becomes very small, as shown at 70 in FIG. Thereby, even if the potential of the main data line changes, noise due to capacitive coupling to the plate can be made extremely small due to the shielding effect of the sub data line.

Note that, assuming that the width of the first wiring layer is dx and the width of the second wiring layer is d2, the larger the value of dz/dz, the greater the noise reduction effect.

〔Effect of the invention〕

According to the present invention, noise generated in a cell array of an ultra-highly integrated dynamic memory can be reduced, and a memory device with excellent operational stability can be provided.

Furthermore, it has conventionally been considered unsuitable for highly integrated RAMs due to the amount of noise. Open data line (open bit B)
By applying the present invention to the structure, the noise can be significantly reduced. This makes it possible to realize an ultra-highly integrated dynamic memory device having an open data line structure.

[Brief explanation of the drawing]

FIG. 1 is a cell array configuration diagram of one embodiment of the present invention, and FIG.
The figure is a cell array configuration diagram of a conventional dynamic memory, FIGS. 3 and 4I$1 are its structural sectional view and plan layout diagram, and FIG. 5 is a circuit block diagram of a more specific embodiment of the present invention. 6 and 7 are a structural sectional view and a plan layout diagram of an embodiment of the present invention. 1...Memory cell, 2, 3...Main data line, 2A. 3A, 211.3Fl...Sub data line, 4...Word line, 5A, 5B...Connection switch, 6A, 6T3
...Potential fixing switch, 7...Fixed potential wiring, 8
...Peripheral circuit, 50...Memory cell block, 52
...Plate, 53...Block selection signal line, 54
...Potential fixed signal line, 55...Inverter, 56.
. . . Row address selection circuit, 57 . . . Block selection circuit, 58 . . . Interlayer parasitic capacitance, 30 . . . Semiconductor substrate, 3
1.35... Insulator, 3; 3... First gate, 3
4... Second gate, 38° 48... First wiring layer, 37... Interlayer insulating film, : 39° 49... Second wiring layer. Z z mouth + :' ! ! Z1 Memory Hill 2'1.23 Chi Ga Izumi 2 24 Word ζt Mi Z3 Usage y1 Z9 Al-To ■ 5 Figure et al. Rikui own name y3.54'
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Claims (2)

[Claims] 1. An array of cells that stores charge carriers in the semiconductor as a source of information, an addressing mechanism that specifies the location of each cell, a main data line that carries the source of charge carriers, and also a charge carrier. A plurality of sub data lines are provided subordinate to one main data line to transmit data, and a memory cell specified by the addressing mechanism is connected to the sub data line, and a plurality of sub data lines are provided to connect the main data line and the sub data line. At least a first connecting means, a plurality of second connecting means for connecting the sub data line to the second DC potential, and an information writing mechanism and a reading mechanism provided for each main data line. A charge storage type semiconductor memory, wherein a plurality of sub data lines other than the sub data line connected to the main data line are connected to a first DC potential. 2. In the semiconductor memory according to claim 1, the sub data line is formed in a first wiring layer, the main data line is formed in a second wiring layer, and the main data line is formed above the sub data line, A charge storage type semiconductor memory characterized by being arranged in parallel so as to cover a part of the semiconductor memory.