JPS62290358A - Drive stop control system of thyristor rectifier - Google Patents

Abstract

PURPOSE:To prevent breakage of a thyristor, by a method wherein gate firing signal supplied to the thyristor in synchronization with phase zero point of power source voltage disappears at drive stop state. CONSTITUTION:Voltage Xo detected by an instrument transformer is inputted in a synchronous signal making circuit 11, and power source synchronous signal Sv at high level during period of positive voltage of an aerial line is produced, and inputted and supplied to a zero point pulse generator 12 and a three-input AND gate 17. The pulse generator 12 outputs zero point pulse Zp, and supplies reset signal to an integrator 13. Output Is of the integrator 13 is supplied to a comparator 15 and also output Vp of a phase angle command operation circuit 16 is supplied similarly, and the comparison output is outputted to the gate 17. In this case, D flipflop 18 is installed, and its output Df is supplied to the AND gate 17 in place of drive command signal Ds. In this constitution, disappearing timing of the gate firing signal is synchronized with the zero point of the power source voltage, and the gate firing signal of prescribed pulse width is generated.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a firing control method when the drive of a thyristor rectifier with variable output voltage is stopped.

C. Prior Art] FIG. 3 shows a power supply circuit for a DC motor that drives an electric vehicle, and shows a pantograph 3 in sliding contact with an AC voltage overhead line 31.
2 is connected to the primary winding of a step-down transformer 35 via an AC circuit breaker 34, and is connected to an instrument transformer (
PT) 33.

The secondary windings of the step-down transformer 35 are thyristors 37a and 37b.
and the input terminal of a thyristor rectifier 36 formed by connecting diodes 38a and 38b in a bridging manner,
An output voltage that changes by controlling the firing phase angle i#I of the thyristors 37a and 37b is applied to a series circuit of an armature coil 39a and a field coil 39b of a DC motor 39.

The firing phase angle control circuit of the gates of the thyristors 37a and 37b of the thyristor rectifier 36 is disclosed in, for example, Japanese Patent Application Laid-open No. 59-18.
This is disclosed in Japanese Patent No. 5102, and will be explained based on FIGS. 4 and 5.

Voltage V detected at instrument transformer 33. (Fig. 5 (a)) is input to the synchronization signal generation circuit 11, where the power supply synchronization signal SvC, which is at a high level during the period when the power supply voltage, that is, the voltage of the overhead wire 31 is positive, is generated. This power synchronization signal Sv is input to the zero point pulse generation circuit 12 and the three-man power AND gate 17.

The zero point pulse generation circuit 12 detects the rise of the power supply synchronization signal Sv,
A short time width pulse signal that synchronizes with the falling edge, that is, a zero point pulse Zp that synchronizes with the zero point of the power supply voltage [Figure 5 (c)]
is output and given to the separator 13 as a reset signal. A clock oscillator 14 generates a clock signal CLK, and the clock signal is applied to the zero point pulse generation circuit 12 and the separator 13.

The integral output Is (FIG. 5 (d) solid line) of the separator 13 is given to the ten input terminal of the comparator 15.The phase angle command calculation circuit 16 outputs a voltage signal according to the setting signal. This voltage signal, that is, the phase angle command signal VpC
5(d) broken line] is applied to one input terminal of the comparator 15. Therefore, the comparator 15 outputs a pulse signal Vq that becomes high level when Is becomes larger than Vp (Fig. 5 (e)).
However, this output Vq is a 3-person AND game) 17
is input. The remaining input of the three-man power AND gate 17 is the drive command signal Ds [5th Z] which becomes high level when the DC motor 39 is driven, and from the AND gate 17, the gate shown in FIG. A firing signal Ct is generated.

Since the clock signal CL is given to the fine separator 13 as an object to be integrated, and the zero point pulse zp is given to the integrator 13 as a reset signal, the output of the integrator 13 is a sawtooth wave shown in FIG. 5(d). Therefore, the phase angle command signal V
Gate firing signal G whose pulse width changes depending on the height of p
t will be obtained.

The circuit shown in Fig. 4.5 is for creating a gate firing signal to be given to the thyristor 37a to be fired during the period when the power supply voltage is positive, and a gate firing signal for the negative side thyristor 37b. Gt can be similarly created by using an inverted signal of the power synchronization signal Sv.

[Problem to be Solved by the Invention 3] In the circuit as described above, when the DC motor stops or for some reason the drive command signal Ds disappears (becomes low level), the gate firing signal Gt becomes low level,
Depending on the timing of this disappearance, the final gate firing pulse (indicated by the arrow in Figure 5 (G)) becomes very narrow, and because of this, the prescribed gate current is not supplied due to insufficient gate firing signal of the thyristor. First, there is a problem in that so-called local spots occur, causing destruction of the thyristor. A similar problem also occurs when the gate firing signal disappears while the main circuit current is flowing through the thyristor.

The present invention has been made in view of such problems, and provides a rectifier that can output a gate firing signal with a sufficient pulse width and prevent the destruction of the thyristor, regardless of the timing of disappearance of the drive command signal Ds. The purpose is to provide equipment.

[Means for solving problems]

The drive control method for the thyristor rectifier according to the present invention eliminates the gate firing signal applied to the thyristor in synchronization with the phase zero point of the power supply voltage when the drive is stopped.

[Effect]

In the present invention, the timing at which the gate firing signal applied to the thyristor disappears when the drive of the device is stopped is synchronized with the zero point of the power supply voltage, and a gate firing signal having a predetermined pulse width is generated.

C Actual Road Example] The control method of the present invention will be described in detail below based on the drawings showing one embodiment thereof.

FIG. 1 is a block diagram of an ignition phase angle control circuit implementing the method of the present invention, and FIG. 2 is a timing chart thereof.

This circuit includes a D flip-flop (Enojito Egger type data clutch circuit) 18, applies a drive command signal Ds to its data terminal and a zero point pulse Zp to its trigger terminal T, and outputs an output from its output terminal Q. Df)
This circuit differs from the conventional circuit shown in FIG. 4 in that it is applied to the AND gate 17 instead of the tr drive FII command signal Ds.

For example, the power supply voltage Vo detected by the instrument transformer 33 shown in FIG. A power supply synchronization signal Sv [FIG. 2 (b)] is created, and this power supply synchronization signal Sv
and is input to the three-man power AND gate 17.

The zero point pulse generation circuit 12 detects the rise of the power supply synchronization signal Sv,
A zero-point pulse Zp (FIG. 2 (c)) with a short time width synchronized with the falling edge is output, and is given to the integrator 13 as a reset signal and to the D flip-flop 18 as a trigger signal. A clock oscillator that oscillates a clock signal from a zero-point pulse generation circuit 1.
2 and an integrator 13. The integral output Is (FIG. 2 (d) solid line) of the integrator 13 is given to the ten input terminal of the comparator 15. The zero phase angle command calculation circuit 16 outputs a voltage (No. 8) according to the setting signal. , this voltage signal, that is, the phase angle command signal Vp (Figure 2 (d) broken line)
is applied to one input terminal of the comparator 15. Therefore, comparator 15
teeth! When S becomes larger than Vp, a pulse signal Vq (FIG. 2 (E)) that becomes high level is output, and this output Vq is input to the three-man power AND gate 17.The DC motor drives 39. Drive command signal D that sometimes becomes high level
s (FIG. 2(g)) is applied to the data terminal of the D flip-flop 18, and its output IM (FIG. 2(g)) is input to the three-man power AND gate 17.

A gate firing signal Gt shown in FIG. 2 (H) is generated from the AND gate 17.

Since the clock signal CLK is given to the integrator 513 as an object to be integrated, and the zero point pulse zp is given to the integrator 13 as a reset signal, the output of the integrator 13 becomes a sawtooth wave as shown in FIG. 2(d). Thus, a gate firing signal Gt whose pulse width changes depending on the level of the phase angle command signal Vp is obtained.

When we look at the point at which the drive command signal Ds disappears, the data input of the D flip-flop knob becomes low level, but since the trigger signal is given at the zero point of the power supply voltage vo, the cent state remains until the trigger signal is given. continued,
Therefore, the signal Dr becomes low level in synchronization with the zero point pulse zp. As a result, the gate firing signal Gt changes to low level at that point. Therefore, even when the drive command signal disappears, the pulse width of the gate firing signal Gt does not become narrower as in the conventional case, and the gate firing signal Gt having a predetermined pulse width can be obtained.

Note that the method of the present invention can be implemented without relying on the circuit described above.

〔effect〕

As described above, in the present invention, the timing at which the gate firing signal disappears when the drive is stopped is synchronized with the phase zero point of the power supply voltage. An arc signal is obtained, thus the wave speed of the thyristor is prevented, and thus a reliable thyristor rectifier device can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an ignition phase angle side control circuit showing an embodiment of the method of the present invention, Fig. 2 is its timing chart, Fig. 3 is a power supply circuit diagram of a DC motor, and Fig. 4 is a conventional point diagram. FIG. 5 is a block diagram of the arc phase angle side control circuit and its timing chart. 11... Synchronization signal generation circuit 12... Zero point pulse generation circuit 13... Integrator 15... Comparator 16.
・・Phase angle command calculation circuit 17・AND gate 18・
...D flip-flop 36...Thyristor rectifier 37a, 37b...Thyristor In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a thyristor rectifier whose output voltage is variable by firing phase angle control, drive stop control characterized in that when driving is stopped, the gate firing signal applied to the thyristor is synchronized with the phase zero point of the power supply voltage and disappears. method.