JPS62289777A - Semiconductor integrated logic circuit - Google Patents

Abstract

PURPOSE:To test a logic circuit part by adding a flip-flop circuit which is irrelevant to normal operation to a flip-flop circuit which can be put in scan-pass constitution. CONSTITUTION:The extension flip-flop which is irrelevant to the normal operation is connected through a selector 15. When a logic circuit 11 controls the resetting of a flip-flop circuit 12 during a scan-pass test, the output of the logic circuit 11 is put by the selector 15 in the data of the extension flip-flop circuit 13 which is irrelevant to the normal operation. Thus, the output of the logic circuit 13 can be read out during scan-pass operation and a test is taken.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Imaginary Field of Application] The present invention relates to a semiconductor integrated logic circuit, and more particularly to a semiconductor integrated logic circuit having a flip-flop circuit for iffing a shift register for a scan path.

[Traditional Keijutsu]

Conventionally, there is a logic circuit having a configuration shown in FIG. 4 as a logic circuit having a flip-flop circuit constituting this type of shift register for scan paths. The circuit in FIG. 4 is a flip-flop circuit F41 to F4 forming a shift register.
A flip-flock group consisting of Ω, selectors 841 to S4n that can switch between Sayayan mode and normal mode, a scan-in terminal 41, a scan-out terminal 42,
A circuit under test 44 consisting of a clock terminal 43 and a combination circuit
It's been a long time since I've been in the middle of a long time.

In this configuration, the clocks of the flip circuits F41 to F4n are outputted to the clock terminal 43 outside Naosaki,
Although the sets and resets of the sentence flip-flop circuit are not used, when implementing a scan path configuration in an actual one-way circuit, the clock and set/reset of the flip-flop circuit can be controlled using other logic circuits. There are many cases in which there is only one heat.

Figure 5 shows an example in which the clock of the flip-flop circuit is controlled by another logic circuit, and Figure 6 shows an example in which the output of the flip-flop circuit is turned upside down by the electric logic circuit.
'iJ down.

In the scan path test, if there is a logic circuit that controls the 7-lip-flop clock and set/reset, it is necessary to bypass the logic circuit, so the test of that logic circuit is difficult. become unable.

[Problem that the invention seeks to solve]

In the conventional configuration described above, the logic L that controls the clock system and set/reset system of the flip-flop circuit is
! When testing 12I'f6, it is not possible to use the scan path test method, so there is a drawback that the test must be performed by the usual test method of inputting a test pattern from the input terminal and measuring the signal at the output terminal.

[Means for solving problems]

An object of the present invention is to increase the efficiency of testing in a scan path test method with a simple configuration. The purpose is to provide circuits.

In the semiconductor integrated logic circuit of the present invention, a control system signal of a shift register circuit consisting of a plurality of clip circuits connected in series in a scan path configuration is used as a selector for a data signal of a flip-flop circuit constituting the shift register. All features are connected through.

〔Example〕

FIG. 1 shows a basic circuit of the present invention.

In FIG. 1, flip-flop circuits 1, 2, and 3 have selectors 5, 6, and 7 connected to signal lines a and b.

By selecting cf, it is possible to create a scan canvas configuration. The map flip-flop circuit 4 has data connected to the control circuit 9 of the other 7 flip-flops via the selector 8, and the flip-flop circuits 1, 2, .
3 and a scan path configurable connection is shown as 'fx'.

In such a connection, each of the selectors 5, 6, 7.8 selects the signal line e, f8g, h.
Select word lines a, b, c, d and flip-flop 1, 2,
The combinational circuit 10 can be tested by configuring 3.4 into a shift register configuration and performing a scan path operation. At this time, the free lag flop system control circuit 9
can be tested simultaneously by the flip-flop circuit 4.

FIG. 2 illustrates a first embodiment of the invention. Second
In the figure, logic circuit 11 controls the reset of flip-flop circuit 12 in normal operation, and selector 14.1
5, the flip-flop circuits 12 and 13 can be configured as a shift register in a scan canvas configuration he, and the selector 16
inputs the signal from the logic circuit 11 to reset the flip-flop circuit 12 during normal operation, and outputs a signal that divides the reset of the flip-flop circuit 12 by 'S during the scan path test. The flip-flop circuit 13 is an additional flip-flop that is not related to normal operation.

In this connection, when testing the logic circuit 11 that controls the reset of the flip-flop circuit 12 during the scan path test, the data of the additional 7-lip, 70-tub circuit 13 that is not related to normal operation is changed to the logic circuit by the selector 15. By reading the output of 11, it can be read out during scan path operation.

FIG. 3 shows a second embodiment of the invention. Third
In the figure, a logic circuit 21 controls a clock of %22 flip-flops in normal operation, and a flip-flop circuit 23 is an additional flip-flop not related to normal operation. Further, selectors 24 and 25 enable scan path testing of each of the seven lip-flops, and selector 26 allows switching between a normal clock and a scan clock.

If such a connection is used and the normal clock and scan clock are switched during the scan path test, an active edge may appear for the clock of the flip-flop circuit 22, so the selector 26 is switched during the scan path test. , you have to choose a scan clock to prefix. In such a case, the logic circuit 21 cannot be tested, but it can be tested by using an additional flip-flop as in the main structure.

〔Effect of the invention〕

As explained above, the invention is possible by adding a flip-flop circuit that is not related to normal operation to the scan path configuration, and by adding a flip-flop circuit that is not related to normal operation, it is possible to test logic circuit sections that cannot be tested with conventional scan path tests. You can taste the effect.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit diagram of the invention, Fig. 2 is a circuit diagram of the first modification of the invention, and Fig. 3 is a circuit diagram showing problems in the scan canvas configuration of the 2nd n subordinate of the invention. It is. 1.2, 3, 4, 12, 13, 22, 23°F41~F
4n, 51.52.61.62-=-flip Lg circuit, 5,6,7,8,14,15,24°25, S41
~S4n...Selector circuit, g, 11, 21...
...logic circuit, 10.44... combinational circuit,
53... Inverter, 63...
NAN D. Mr.2~゛Representative Patent Attorney Susumu Uchihara,゛・1・
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Claims (1)

[Claims] The control system signal of the shift register circuit, which is made up of a series connection of multiple flip-flop circuits that can be configured as a scan path, is
A semiconductor integrated logic circuit, characterized in that it is connected to data terminals of other flip-flop circuits forming a shift register via a selector.