JPS61294378A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To write and read contents of flip flops other than faulty flip flops by constituting a logic integrated circuit to that all flip flops in this circuit can be shifted in many directions. CONSTITUTION:If one optional flip flop, for example, 21 out of flip flops 20-22 does not function, the first and the second selecting signal terminals 9 and 10 are set to logical '1' and '0' respectively to constitute a scan path, and contents of the flip flop 22 are read out from a scan output terminal 12, and a signal applied to a scan input terminal 8 is written in the flip flop 20 simultaneously. Further, selecting signal terminals 9 and 10 are set to logical '1' together to constitute a scan path, and a shift register in the order opposite to said order is constituted. The signal applied to the scan input terminal 8 is written in the flip flop 22, and contents of the flip flop 20 are read out from the scan output terminal 12 simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic integrated circuit, and more particularly to a logic integrated circuit having a scan path.

[Conventional technology]

A block diagram of an example of a conventional logic integrated circuit of this type is shown in Figure 5.
As shown in the figure. The logic integrated circuit in FIG. 5 is a combinational logic circuit 15.
, selectors 16, 17, 18, and flip-flop 2
0, 21.22, input terminal 1゜2.3.4, output terminal 5, 6.7, clock input terminal 11, first selection signal terminal 9, scan-in terminal 8, scan-out terminal 12, power input It consists of terminals 13, 14 and K.

In the logic integrated circuit shown in FIG. 5, the input terminals are usually 1°2,
3. The input signal from 4 is input to the combinational logic circuit 15.
'', and the signals from the combinational logic circuit 15 to the 7-lip 70 tube are sent to the selector 16,
17. Flip-flocks 20, 21 selected by 18
．． 22. flip flop 20, 21.2
The output from combinational logic circuit 15 is supplied via signal lines 86, 87, 88 to output terminal 5.2. 6. Output from 7.

When configuring a scan path, by supplying a control signal to the first selection signal terminal 9, the selectors 16, 1
7.18 to select signals from signal lines 80, 81, 82, configure a shift register with scan-in terminal 8 as input and scan-out terminal 12 as output, and select signals from signal lines 80, 81, 82. 7 reading from the system scanout terminal 12 by shifting the contents;
Scan-in terminal 8 on lip 70 knob 20, 21.22
one or more configurations capable of writing signals from;
Flip-flop 2 directly via combinational logic circuit 15
0, 21, and 22 can be read and written, and the function test of this logic integrated circuit can be carried out efficiently.

[Problem that the invention seeks to solve]

In the above-mentioned conventional logic integrated circuit having a scan path, when a scan path is configured, a shift register is configured with the scan path as an input and the scan out terminal as an output, but the direction in which the contents of this shift register are shifted is Since it is only unidirectional, even if only one of the flip-flops that make up the shift register does not function, the signal from the scan-in terminal can be set to the flip-flop, and the set contents can be read from the scan-out terminal. There is a drawback that this function cannot be fulfilled at all.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to read out the contents of 70 flip-flops other than the non-functioning flip-flop from the scan-out terminal even if only one of the flip-flops does not function. An object of the present invention is to provide a logic integrated circuit into which logic signals can be written from terminals.

[Means for solving problems]

The logic integrated circuit of the present invention includes a combinational logic circuit, a scan-in terminal, a scan-out terminal, and a selector whose input terminal is connected to the output terminal of the combinational logic circuit. a plurality of flip-flops connected between the plurality of flip-flops, and a serial shift register configured to toss the scan-in terminal as an input terminal and the scan-out terminal as an output terminal in response to supply of a first selection signal. and a first configuration means for controlling the plurality of flip-flops with the scan-in terminal as an input terminal and the scan-out terminal as an output terminal in a direction opposite to that of the first configuration means in response to supply of a second selection signal. and second configuration means configured as a serial shift register for shifting.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment has a combinational logic circuit 15, a scan-in terminal 8, a scan-out terminal 12, and a combinational logic circuit 1.
Selector 16.17.1 whose input terminal is connected to the output terminal of 5
A plurality of flip-flops 20, 21 and 22 are connected via the respective terminals 8 and 12 between the scan-in terminal 8 and the scan-out terminal 12, and a first selection signal is supplied to the first selection signal terminal 9. Flip-flop 20 in response
．． Selector 19 as a first configuration means that configures 21 and 22 into a serial shift register with scan-in terminal 8 as an input terminal and scan-out terminal 12 as an output terminal.
．． A signal line connecting the first selection signal terminal 9 and the input terminal of the selector 16, 17, 18, and a signal line connecting the scan-in terminal 8 to the selector 16. A plurality of flip-flops are scanned in response to signals #27, 28, 29, and 30 that are sequentially sent through the flip-flop 20 to the selector 19, and a second selection signal that is supplied to the second selection signal terminal 10. terminal 8
a selector 1 as a second configuration means configured into a serial shift register that shifts in the opposite direction to the first configuration means, with the input terminal being the input terminal and the scan-out terminal 12 being the output terminal;
9. Second selection signal input terminal 10 and selector 16.17
, 18 and 19, a signal line 25 for sending the signal input to the scan-in terminal 8 to the flip-flop 22 at the last stage, and a signal line 25 for returning the output of the flip-flop to the previous stage for input. , and a signal line 26 for sending the output of the front-stage flip-flop 20 to the scan-out terminal 12.

Next, the operation of this embodiment will be explained.

The logic integrated circuit of this embodiment is normally used with the first selection signal terminal 9 set to logic 10". In this case, the input terminal 1
．． 2. 3. The input signal from 4 is the combinational logic circuit 1
5, the signal from the combinational logic circuit 15 to the flip-flop is passed through the signal lines 31, 32, 33 to the selectors 16, 1.
7. Flip-flops 20, 21 selected by 18
．． 22. These flip-flops20.
21 and 22 operate in synchronization with the clock signal supplied from the clock input terminal 11. flip flop 20
The output from 21.22 is supplied to the combinational logic circuit 15 via signal lines 34, 35.36, and the output signals are output from output terminals 5, 6.7. Thus, the logic integrated circuit typically operates as a logic circuit including combinational logic circuits and flip-flops.

Next, when configuring the scan path and reading and writing the contents of the flip-flop, the first selection signal terminal 9 is set to logic %1#, and the second selection signal terminal 10 is set to logic 10.
’. In this case selector 16.17.18.1
The flip-flops 20, 21, and 22 are configured as shift registers having the scan-in terminal 8 as an input and the scan-out terminal 12 as an output. In this case, each time a clock signal is input to the clock input terminal 11, the contents of the flip-flops 22, 21, and 20 are output from the scan-out terminal 12 in this order.

At the same time, the good signal applied to the scan-in terminal 8 is shifted in the order of flip-flops 20, 21, and 22. In this way, the contents of the flip-flops inside the logic integrated circuit are read 7, and an arbitrary logic signal is applied to the flip-flops. Values can be written. The concept explained here is that the contents of the flip-flop 20 are shifted to the flip-flop 21, and the contents of the flip-flop 21 are changed to 7, 70, 2.
The configuration of the shift register that shifts to 2 is assumed to be the first configuration.

Next, when configuring a scan path and reading and writing the contents of the flip-flops in the reverse order of the first configuration, the first selection signal terminal 9 is connected to the logic 111. The second selection signal terminal 10 is set to logic 111. At this time, the selectors 16, 17, 18, 19 are connected to the signal lines 23, 24, 25.
．． 26 and selects the signal from flip-flop 22,2.
1.20 is configured as a shift register with the scan-in terminal 8 as an input and the scan-out terminal 12 as an output, but it is the opposite of the first configuration Jl! The second configuration shift register is configured to shift to i. That is, every time a clock signal is input to the clock input terminal 11, the contents of the flip-flops 20, 21, and 22 are outputted from the scan-out terminal 12 in this order, and the signal applied to the scan-in terminal 8 at the same time is 7 rip 70 bits. 22.21.2
Shifts in the order of 0. In this way, the contents of the flip-flops inside the logic integrated circuit can be read out in the reverse order of the first configuration, and arbitrary logical values can be written therein.

Here, if any one of the flip-flops 20.21.22 does not function, for example, the flip-flop 2
1 does not function, the first selection signal terminal 9 is set to logic %11. A scan path is configured by setting the second selection signal terminal 10 to logic 101, a shift register of the first configuration is configured, and the contents of the flip-flop 22 are read from the scan-out terminal 12, and at the same time a signal is applied to the scan-in terminal 8. can be written to the flip-flop 20, and the first selection signal terminal 9 is set to logic 11, and the second selection signal terminal 10 is set to logic 11' to form a scan path, and the first selection signal terminal of the second configuration is set to logic 11'. By configuring the shift register as a shift register that shifts in the reverse order, the signal applied to the scan-in terminal 8 is written to the flip-flop 22, and at the same time, the contents of the flip-flop 20 are read from the scan-out terminal 12. be able to. That is, even if the flip-flop 21 does not function, the contents of the other 7-lip 70-tubes 20, 22 can be read from the scan-out terminal 12, and the signal applied to the scan-in terminal 8 can be written.

FIG. 2 is a circuit diagram of an example of a detailed circuit of the flip-flop shown in FIG. 1. Reference numbers 41, 51, and 54 are an input terminal, an output terminal, and a clock input terminal, respectively.

FIG. 3 is a circuit diagram of an example of a detailed circuit of the selector 19 shown in FIG. 1. Reference numerals 42 and 43 are input terminals, reference numeral 52 is an output terminal, and reference numeral 55 is a selection signal terminal. When the logic 11' is supplied to the selection signal terminal 55, the signal supplied to the input terminal 42 is selected, and when the logic "O1" is supplied, the signal supplied to the input terminal 43 is selected.

FIG. 4 is a circuit diagram of an example of a detailed circuit of the selectors 16, 17, and 18 shown in FIG. Reference number 44°45.46
is the input terminal, and reference number 53 is the output terminal.

Reference numerals 55 and 57 are selection signal terminals. When logic 10' is supplied to selection signal terminal 57, the signal supplied to input terminal 46 is selected, and logic 111 is supplied to selection signal terminal 57.
When logic 10' is supplied to the 9 selection signal selector 56, the signal supplied to the input terminal 45 is selected, and the selection signal terminal 57
When the logic %11 is supplied to the logic '11° selection signal terminal 56, the signal supplied to the input terminal 44 is selected.

〔Effect of the invention〕

As explained above, the present invention enables all flip-flops in a logic integrated circuit to be configured into a serial shift register capable of shifting in both directions, so that any one of the plurality of flip-flops can function. Even if the flip-flop does not function, the contents of the flip-flops other than the non-functioning flip-flop can be read from the scan-out terminal and logic signals can be written from the scan-in terminal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the flip-flop shown in FIG. 1, FIG. 3 is a detailed circuit diagram of the selector 19 shown in FIG. 1st
Detailed circuit diagram of selectors 16, 17 and 18 shown in the figure, No. 5
The figure is a block diagram of an example of a conventional logic integrated circuit. 1.2, 3.4... Input terminal, 5. 6. 7
...Output terminal, 8...Scan-in terminal, 9...First selection signal terminal, 10...
. . . second selection signal terminal, 11 . . . clock input terminal, 12 . . . scan out terminal, 13.
14...Power input terminal, 15...Combinational logic circuit, 16.17, 18.19...Selector, 20.21.22...Flip-flop , 23-36... Signal line, 41-46 River...
Input terminal, 51, 52.53...Output terminal, 5
4... Clock input terminal, 55, 56.57.
...Selection signal input terminal, 80 to 88...
Signal line. Figure 3 55'ro 57 Figure 4

Claims (1)

[Claims] A combinational logic circuit, a scan-in terminal, a scan-out terminal, and a plurality of flip-flops connected between the scan-in terminal and the scan-out terminal via a selector whose input terminal is connected to the output terminal of the combinational logic circuit. and first configuration means for configuring the plurality of flip-flops into a serial shift register having the scan-in terminal as an input terminal and the scan-out terminal as an output terminal in response to supply of a first selection signal; In response to supply of a second selection signal, the plurality of flip-flops are configured as a serial shift register with the scan-in terminal as an input terminal, the scan-out terminal as an output terminal, and shifting in the opposite direction to the first configuration means. and second configuration means for configuring the logic integrated circuit.