JPS6228888B2 - - Google Patents

Info

Publication number
JPS6228888B2
JPS6228888B2 JP15041179A JP15041179A JPS6228888B2 JP S6228888 B2 JPS6228888 B2 JP S6228888B2 JP 15041179 A JP15041179 A JP 15041179A JP 15041179 A JP15041179 A JP 15041179A JP S6228888 B2 JPS6228888 B2 JP S6228888B2
Authority
JP
Japan
Prior art keywords
voltage
gain control
transistor
differential amplifier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15041179A
Other languages
Japanese (ja)
Other versions
JPS5672509A (en
Inventor
Mitsuo Ookawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15041179A priority Critical patent/JPS5672509A/en
Publication of JPS5672509A publication Critical patent/JPS5672509A/en
Publication of JPS6228888B2 publication Critical patent/JPS6228888B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers

Landscapes

  • Processing Of Color Television Signals (AREA)
  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 本発明は、1個の制御端子へ印加する直流制御
電圧の大きさを変化させることによつて、利得制
御回路の制御出力特性に異なつた2種の出力特性
を付与し、粗調整と微調整の機能を付加すること
のできる利得制御電圧を発生する直流利得制御装
置に関する。
Detailed Description of the Invention The present invention provides two different output characteristics to the control output characteristics of a gain control circuit by changing the magnitude of the DC control voltage applied to one control terminal. The present invention relates to a DC gain control device that generates a gain control voltage that can add coarse adjustment and fine adjustment functions.

利得制御回路は周知のように入力信号に対する
出力信号の大きさの比率を任意に変化させる機能
を有するものであり、たとえば、カラーテレビジ
ヨン受像機の色飽和度あるいは色相の制御のため
には不可欠な回路である。ところで、かかる利得
制御回路により利得制御をなすにあたり、粗調整
と微調整の機能の付加されていることが大切であ
る。ところで、色飽和度における粗調整の範囲
は、色が消えて白黒画面となるところから、色が
飽和してにじみが生じ画像がつぶれるまでの範囲
であり、一方、微調整範囲は色が飽和してにじみ
が生じるレベルよりも6デシベル程度低いレベル
における所望のレベル範囲である。
As is well known, a gain control circuit has the function of arbitrarily changing the ratio of the output signal to the input signal, and is essential for controlling the color saturation or hue of color television receivers, for example. It is a circuit. By the way, when performing gain control using such a gain control circuit, it is important that coarse adjustment and fine adjustment functions are added. By the way, the coarse adjustment range for color saturation is from the point where the colors disappear and the screen becomes black and white to the point where the colors become saturated and blurring occurs and the image is crushed.On the other hand, the fine adjustment range is the range where the colors become saturated The desired level range is approximately 6 decibels lower than the level at which smearing occurs.

また、色相の粗調整範囲は、通常、肌色を基準
とし、±30度を越える色相変化がもたらされる範
囲であり、一方、微調整の範囲は、通常、肌色を
基準とし、±7度程度の色相変化がもたらされる
範囲である。
In addition, the coarse hue adjustment range is usually a range that results in a hue change of more than ±30 degrees based on the skin tone, while the fine adjustment range is usually about ±7 degrees based on the skin tone. This is the range in which a hue change occurs.

通常の粗調整と微調整の関係は、まず、粗い調
整によつて調整範囲に近づけ、この後微調整によ
つて必要とされる細い調整を行うものであるが、
上記の色飽和度あるいは色相の調整などのように
粗調整の範囲と微調整の範囲が定められているも
のでは、それぞれの調整が独立したものとなる。
このような調整を行なうにあたり、従来の利得制
御装置では、粗調整用の回路と微調整用の回路の
双方を設け、これらの回路から得られる利得制御
用電圧を利得制御回路へ供給する回路構成が採ら
れていた。
The normal relationship between coarse adjustment and fine adjustment is that first, coarse adjustment is used to get closer to the adjustment range, and then fine adjustment is performed to make the necessary fine adjustments.
When a coarse adjustment range and a fine adjustment range are defined, such as the above-mentioned color saturation or hue adjustment, each adjustment is independent.
To perform such adjustments, conventional gain control devices have a circuit configuration that includes both a coarse adjustment circuit and a fine adjustment circuit, and supplies the gain control voltage obtained from these circuits to the gain control circuit. was taken.

第1図は、従来の利得制御装置における利得制
御用電圧発生部の構成を示す図であり、電源電圧
印加端子1と接地点との間に、固定抵抗2,3な
らびに可変抵抗4で構成される粗調整用の回路
と、半固定抵抗5、固定抵抗6,7および8、な
らびに可変抵抗9で構成される微調整用の回路と
を配置するとともに、両回路からの利得制御用電
圧を選択的に取りだすためのスイツチ手段10を
設け、その接点XまたはYの選択によつて利得制
御用電圧を利得制御回路11へ供給して利得制御
を行なわせる回路構成となつている。
FIG. 1 is a diagram showing the configuration of a gain control voltage generating section in a conventional gain control device, which is composed of fixed resistors 2, 3 and a variable resistor 4 between a power supply voltage application terminal 1 and a ground point. A coarse adjustment circuit consisting of a semi-fixed resistor 5, fixed resistors 6, 7 and 8, and a variable resistor 9 are arranged, and a gain control voltage from both circuits is selected. The circuit configuration is such that a switch means 10 is provided for taking out the gain control voltage, and by selecting the contact X or Y of the switch means 10, a gain control voltage is supplied to a gain control circuit 11 to perform gain control.

なお、近年各種の回路が半導体集積回路
(IC)化されるに至り、上記の利得制御回路もま
たIC化されるに及んでいるが、IC化される利得
制御回路は差動増幅器を主体として構成され、差
動入力の一方を上記の利得制御用電圧とすること
によつて差動増幅器を構成するトランジスタへの
信号電流の分流比を変化させ、利得制御が実行さ
れる。しかしながら、差動増幅器の利得制御端子
に印加され、差動増幅器を確実にスイツチ動作さ
せるための差電圧は±150mV程度であり、この
ような微小電圧を付与することのできる制御電圧
を第1図で示した利得制御用電圧発生装置によつ
て高精度で発生させることは極めて困難であり、
実際にはさらに制御電圧発生器を配置し、ここで
微小電圧への変換を行なつて差電圧として供給す
ることが行なわれている。
In addition, in recent years, various circuits have been integrated into semiconductor integrated circuits (ICs), and the gain control circuits mentioned above have also been integrated into ICs. By setting one of the differential inputs to the above-mentioned gain control voltage, the dividing ratio of the signal current to the transistors forming the differential amplifier is changed, and gain control is performed. However, the differential voltage that is applied to the gain control terminal of the differential amplifier to ensure the switch operation of the differential amplifier is about ±150 mV, and the control voltage that can apply such a small voltage is shown in Figure 1. It is extremely difficult to generate with high precision using the gain control voltage generator shown in
In practice, a control voltage generator is further provided, where the voltage is converted into a minute voltage and supplied as a differential voltage.

また、このようにして利得制御がなされる従来
の利得制御装置の制御電圧Vcpot.に対する出力
信号Vputの変化は第2図で示すようにほぼ比例
する関係にあり、微調整の範囲Aは、出力が零か
ら飽和するまでの粗調整の範囲Bの中にあり、し
かも、その範囲が極めて狭いため、テレビジヨン
受像機等における微調整用の回路は、視聴者によ
つては操作が不可能な関係を成立させ、オート
(自動)回路として調整ずみの状態で予め作り込
まれている。
Furthermore, the change in the output signal V put with respect to the control voltage V cpot of a conventional gain control device that performs gain control in this manner is approximately proportional as shown in FIG. 2, and the fine adjustment range A is , the output is within coarse adjustment range B from zero to saturation, and because this range is extremely narrow, some viewers may not be able to operate the fine adjustment circuits in television receivers, etc. It establishes possible relationships and is pre-built in an adjusted state as an automatic circuit.

本発明は、かかる従来の直流利得制御装置とは
全く異なり、電源電圧印加端子と接地点との間に
配置した1個の可変抵抗のみからなる可変直流電
圧発生回路部から得られる電圧の大小に応じて、
微調整ならびに粗調整のための利得制御電圧を発
生し、しかも、微調整時と粗調整時の利得制御回
路の出力特性を異らすことのできる直流利得制御
装置を提供するものである。
The present invention is completely different from such conventional DC gain control devices, and is capable of controlling the magnitude of the voltage obtained from a variable DC voltage generation circuit section consisting of only one variable resistor placed between a power supply voltage application terminal and a ground point. depending on,
The present invention provides a DC gain control device that can generate gain control voltages for fine adjustment and coarse adjustment, and can also make the output characteristics of a gain control circuit different during fine adjustment and coarse adjustment.

以下に図面を参照して本発明の直流利得制御装
置の構成ならびにその動作について実施例に基い
て説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a DC gain control device according to the present invention will be described below based on embodiments with reference to the drawings.

第3図は、本発明の直流利得制御装置の利得制
御用電圧発生部の構成を示すブロツク図であり、
電源電圧印加端子1と接地点との間に接続される
可変抵抗12、同可変抵抗12の摺動端子に繋る
電圧発生点13に得られる電圧のレベルを検出す
るレベル検出器14、同レベル検出器14からの
出力でスイツチ動作するスイツチ回路部15、差
動入力の一方が前記電圧発生点から供給され、他
方が直流バイアス供給回路部16から供給され、
前記スイツチ回路部15のスイツチ動作で選択的
にエミツタ電流源が接続されて動作する第1およ
び第2の差動増幅器171,172、およびこれ
らの差動増幅器の出力を合成し利得制御用電圧を
発生する利得制御電圧発生回路部18で構成され
ている。なお、19,20は利得制御用電圧の出
力される端子である。
FIG. 3 is a block diagram showing the configuration of the gain control voltage generating section of the DC gain control device of the present invention.
A variable resistor 12 connected between the power supply voltage application terminal 1 and the ground point, a level detector 14 that detects the level of the voltage obtained at the voltage generation point 13 connected to the sliding terminal of the variable resistor 12, and the same level. A switch circuit section 15 that operates as a switch based on the output from the detector 14, one of the differential inputs is supplied from the voltage generation point, the other is supplied from the DC bias supply circuit section 16,
The first and second differential amplifiers 171 and 172 are operated by selectively connecting emitter current sources by the switch operation of the switch circuit section 15, and the outputs of these differential amplifiers are combined to generate a gain control voltage. The gain control voltage generating circuit section 18 generates a gain control voltage. Note that 19 and 20 are terminals to which a gain control voltage is output.

以上の構成からなる利得制御用電圧発生部の動
作であるが、電圧発生点13に発生する電圧の大
きさ(レベル)に応じてレベル検出器14がレベ
ル検出動作を実行し、この検出結果に基づいてス
イツチ回路部15が動作する。スイツチ回路部1
5は2つの電流路をもち、これらのいずれか一方
が閉成状態にあるときには他方が開放状態となる
スイツチ動作を実行し、閉成状態にある側の電流
路を介して、第1の差動増幅器171または第2
の差動増幅器172のいずれか一方に対してエミ
ツタ電流源が接続される。第1および第2の差動
増幅器171と172の一方の入力電圧は電圧発
生点13に得られる電圧に基づいて発生させた等
しい電圧であり、他方の入力電圧は直流バイアス
供給回路部16から各別に供給される電圧であ
る。エミツタ電流源が接続された側の差動増幅器
が上記の差動入力に応じて動作し、この差動増幅
器のコレクタ回路に接続された利得制御電圧発生
回路部18で電圧変換がなされ、端子19と20
に利得制御用電圧が出力される。なお、端子19
と20は、利得制御回路(図示せず)の利得制御
電圧印加端子へ結合され、利得制御回路ではこの
電圧に応じた利得制御動作が実行される。
Regarding the operation of the gain control voltage generation section having the above configuration, the level detector 14 executes a level detection operation according to the magnitude (level) of the voltage generated at the voltage generation point 13, and the detection result is Based on this, the switch circuit section 15 operates. Switch circuit section 1
5 has two current paths, and when one of them is in the closed state, the other one is in the open state. dynamic amplifier 171 or second
An emitter current source is connected to either one of the differential amplifiers 172. The input voltages of one of the first and second differential amplifiers 171 and 172 are equal voltages generated based on the voltage obtained at the voltage generation point 13, and the input voltage of the other is supplied from the DC bias supply circuit section 16 to each input voltage. This is a separately supplied voltage. The differential amplifier connected to the emitter current source operates according to the above differential input, voltage conversion is performed in the gain control voltage generating circuit section 18 connected to the collector circuit of this differential amplifier, and the terminal 19 and 20
A gain control voltage is output. In addition, terminal 19
and 20 are coupled to a gain control voltage application terminal of a gain control circuit (not shown), and the gain control circuit executes a gain control operation according to this voltage.

以上ブロツク図を用いて本発明の直流利得制御
装置の構成と基本動作を説明したが、その具体的
な回路構成は第4図で示すようなものである。
The configuration and basic operation of the DC gain control device of the present invention have been explained above using the block diagram, and its specific circuit configuration is as shown in FIG.

すなわち、レベル検出器14は点13の電圧が
所定値以下であるか否かによつてトランジスタ2
1,22のいずれか一方にベースバイアスを印加
するべく動作する。トランジスタ21と22のコ
レクタは、抵抗23〜27とダイオード28およ
びトランジスタ29で構成される第1の直流バイ
アス供給回路のトランジスタ29のエミツタに抵
抗30,31および32,33を介してそれぞれ
接続されている。スイツチ回路部15はエミツタ
が共通接続され、ベースが抵抗30と31との接
続点ならびに抵抗32と33との接続点にそれぞ
れ接続されたトランジスタ34と35で構成され
ている。なお、上記のエミツタ共通接続点には第
1のバイアス回路中の抵抗26とダイオード28
の直列接続体の両端に生じる電圧がベースバイア
スとして印加されるトランジスタ36およびその
エミツタ抵抗37からなるエミツタ電流源が接続
される。基準バイアスを発生する第2の直流バイ
アス供給回路は抵抗38〜40で構成される。さ
らに、トランジスタ34のコレクタはトランジス
タ41,42および抵抗43,44で構成される
第1の差動増幅器のエミツタ共通接続点へ接続さ
れ、またトランジスタ35のコレクタはトランジ
スタ45,46および抵抗47,48で構成され
る第2の差動増幅器のエミツタ共通接続点に接続
されている。
That is, the level detector 14 detects the transistor 2 depending on whether the voltage at the point 13 is below a predetermined value.
It operates to apply a base bias to either one of 1 and 22. The collectors of the transistors 21 and 22 are connected to the emitter of the transistor 29 of the first DC bias supply circuit composed of resistors 23 to 27, a diode 28, and a transistor 29 via resistors 30, 31 and 32, 33, respectively. There is. The switch circuit section 15 is composed of transistors 34 and 35 whose emitters are commonly connected and whose bases are connected to a connection point between resistors 30 and 31 and a connection point between resistors 32 and 33, respectively. Note that the resistor 26 and diode 28 in the first bias circuit are connected to the emitter common connection point.
An emitter current source consisting of a transistor 36 and its emitter resistor 37 is connected to which the voltage generated across the series connection of is applied as a base bias. A second DC bias supply circuit that generates a reference bias is comprised of resistors 38-40. Furthermore, the collector of the transistor 34 is connected to the common emitter connection point of the first differential amplifier composed of transistors 41, 42 and resistors 43, 44, and the collector of the transistor 35 is connected to the common emitter connection point of the first differential amplifier composed of transistors 41, 42 and resistors 43, 44. The emitters of the second differential amplifier are connected to the common connection point.

第1の差動増幅器の一方のトランジスタ41の
ベースは、抵抗38と39との接続点にあらわれ
る電圧Vaがベースに印加されるエミツタフオロ
ワトランジスタ49のエミツタに接続された抵抗
50と51との接続点へ接続され、また、第2の
差動増幅器の一方のトランジスタ45のベース
は、抵抗39と40との接続点にあらわれる電圧
bがベースに印加され、トランジスタ49とは
逆極性のエミツタフオロワトランジスタ52のエ
ミツタに接続された抵抗53と54の接続点へ接
続されている。さらに、第1および第2の差動増
幅器の各他方のトランジスタ42と46のベース
は、ベースが共通接続されて電圧発生点13に接
続された相補極性のエミツタフオロワトランジス
タ55と56のエミツタに接続されている抵抗5
7と58の接続点ならびに抵抗59と60の接続
点へそれぞれ接続される。
The base of one transistor 41 of the first differential amplifier is connected to the resistors 50 and 51 connected to the emitter of an emitter follower transistor 49 to which the voltage V a appearing at the connection point between the resistors 38 and 39 is applied. Also, the base of one transistor 45 of the second differential amplifier is connected to the base of the voltage V b appearing at the connection point of the resistors 39 and 40, and has a polarity opposite to that of the transistor 49. The emitter of the follower transistor 52 is connected to a connection point between resistors 53 and 54 connected to the emitter of the follower transistor 52 . Further, the bases of the other transistors 42 and 46 of the first and second differential amplifiers are connected to the emitters of emitter follower transistors 55 and 56 of complementary polarity, which have their bases connected in common and are connected to the voltage generation point 13. resistor 5 connected to
7 and 58 and to the connection point of resistors 59 and 60, respectively.

制御電圧発生回路部は、ベースが共通接続され
第1の直流バイアス供給回路の抵抗23と24と
の接続点に接続された2個のエミツタフオロワト
ランジスタ61と62によつて構成されている。
トランジスタ61のエミツタにトランジスタ41
と45のコレクタが接続されるとともに、この点
に端子19が付設され、また、トランジスタ62
のエミツタにはトランジスタ42と46のコレク
タが接続されるとともに、この点に端子20が付
設されている。
The control voltage generation circuit section is composed of two emitter follower transistors 61 and 62 whose bases are commonly connected and connected to the connection point between the resistors 23 and 24 of the first DC bias supply circuit. .
Transistor 41 is connected to the emitter of transistor 61.
and 45 are connected, a terminal 19 is attached to this point, and a transistor 62
The collectors of transistors 42 and 46 are connected to the emitter of , and a terminal 20 is attached to this point.

以上の構成からなる本発明の直流利得制御装置
において、たとえばレベル検出器14により動作
状態の制御されるトランジスタ22が導通、トラ
ンジスタ21がしや断の状態になると、トランジ
スタ34のベース電位はトランジスタ29のエミ
ツタ電位と等しくなり、一方、トランジスタ35
のベース電位はトランジスタ29のエミツタ電位
を抵抗32と33とで分圧した電位となる。かか
るベース電位の変化により、スイツチ回路部を構
成する2個のトランジスタ34と35の一方、す
なわちトランジスタ34が導通状態となり他方の
トランジスタ35がしや断状態となる。したがつ
て、電流源用トランジスタ36は導通状態にある
トランジスタ34を介して第1の差動増幅器の側
へ接続され、第1の差動増幅器のみが動作状態と
なる。すなわち、第1の差動増幅器の構成主体で
あるトランジスタ41と42には、それぞれのベ
ースに印加される電圧に応じて電流源の電流が分
流し、そのコレクタに接続されたエミツタフオロ
ワトランジスタ61と62によつて電圧変換さ
れ、端子19と20に利得制御用電圧として出力
される。
In the DC gain control device of the present invention having the above configuration, for example, when the transistor 22 whose operating state is controlled by the level detector 14 becomes conductive and the transistor 21 becomes conductive, the base potential of the transistor 34 changes to the transistor 29. On the other hand, the emitter potential of transistor 35
The base potential of the transistor 29 is the potential obtained by dividing the emitter potential of the transistor 29 by the resistors 32 and 33. Due to this change in the base potential, one of the two transistors 34 and 35 constituting the switch circuit section, ie, transistor 34, becomes conductive, and the other transistor 35 becomes conductive. Therefore, the current source transistor 36 is connected to the first differential amplifier via the conductive transistor 34, and only the first differential amplifier becomes operational. That is, the current of the current source is shunted to the transistors 41 and 42, which are the main components of the first differential amplifier, according to the voltage applied to their respective bases, and the emitter follower transistor connected to the collector thereof is divided. The voltage is converted by 61 and 62 and outputted to terminals 19 and 20 as a gain control voltage.

上記とは逆に、トランジスタ21が導通、トラ
ンジスタ22がしや断の状態となると、スイツチ
回路部のトランジスタ35が導通し、一方、トラ
ンジスタ34がしや断するため、電流源用トラン
ジスタ36は第2の差動増幅器の側へ接続され、
したがつて、第2の差動増幅器が動作状態とな
り、トランジスタ45と46のベースに印加され
る電圧に応じて電流源の電流が分流し、これがエ
ミツタフオロワトランジスタ61と62で電圧変
換され、端子19と20に利得制御用電圧として
出力される。
Contrary to the above, when the transistor 21 is conductive and the transistor 22 is briefly disconnected, the transistor 35 of the switch circuit section is conductive, while the transistor 34 is briefly disconnected, so that the current source transistor 36 is turned off. connected to the differential amplifier side of 2,
Therefore, the second differential amplifier becomes operational, and the current of the current source is shunted in accordance with the voltage applied to the bases of transistors 45 and 46, and this is converted into voltage by emitter follower transistors 61 and 62. , is output to terminals 19 and 20 as a gain control voltage.

ところで、第1の差動増幅器の基準電圧はV
a、また、第2の差動増幅器の基準電圧はVbであ
る。したがつて、トランジスタ21と22の状態
が切り換わるときの電圧Vcとし、電圧発生点1
3に発生する可変電圧が0〜Vcの範囲のときト
ランジスタ21を導通、トランジスタ22をしや
断の状態に、一方、Vcを超え電源電圧Vccまで
の範囲のときトランジスタ22を導通、トランジ
スタ21をしや断の状態とするようにレベル検出
器14による制御動作を実行させるとともに、上
記の各電圧Vcc,Va,VbならびにVcの間にVcc
>Va>Vc>Vb>0の関係を成立させるなら
ば、電圧発生点13に得られる可変電圧が低レベ
ル(0〜Vc)時には、トランジスタ45と46
を構成主体とする第2の差動増幅器で決定される
制御特性をもつ出力特性が得られ、一方、高レベ
ル(Vcを超えVccまで)時には、トランジスタ
41,42を構成主体とする第1の差動増幅器で
決定される制御特性をもつ出力特性が得られる。
By the way, the reference voltage of the first differential amplifier is V
a and the reference voltage of the second differential amplifier is Vb . Therefore, the voltage at which the states of the transistors 21 and 22 switch is V c , and the voltage generation point 1
When the variable voltage generated at 3 is in the range of 0 to Vc , the transistor 21 is turned on and the transistor 22 is turned off.On the other hand, when the variable voltage generated at Vc is in the range of more than Vc to the power supply voltage Vcc , the transistor 22 is turned on. The control operation by the level detector 14 is executed so that the transistor 21 is turned off, and V cc is set between the above-mentioned voltages V cc , V a , V b and V c .
>V a >V c >V b >0, when the variable voltage obtained at the voltage generation point 13 is at a low level (0 to V c ), the transistors 45 and 46
On the other hand, at a high level (above V c and up to V cc ), an output characteristic with a control characteristic determined by the second differential amplifier mainly composed of transistors 41 and 42 is obtained. An output characteristic having a control characteristic determined by one differential amplifier is obtained.

第5図は、以上説明してきた本発明の直流利得
制御装置により得られる利得制御用電圧により利
得制御を行なつた場合の出力Vputと制御電圧Vcp
ot.との関係を示す図であり、微調整の範囲A
は、電圧発生点13に得られる制御電圧Vcpot
cを超えVccまでであり、一方、粗調整の範囲
BはVcpotが0〜Vcの範囲である。
FIG. 5 shows the output V put and the control voltage V cp when gain control is performed using the gain control voltage obtained by the DC gain control device of the present invention described above .
ot. This is a diagram showing the relationship between fine adjustment range A.
The control voltage V cpot obtained at the voltage generation point 13 exceeds V c to V cc , while the rough adjustment range B is a range in which V cpot is from 0 to V c .

ところで、図示するように、微調整の範囲Aと
粗調整の範囲Bにおける出力特性が相違している
が、かかる出力特性は第1および第2の差動増幅
器の構成要素である抵抗43,44ならびに4
7,48の抵抗値の選定により、差動増幅器の利
得を変化させることによつて得られる。すなわ
ち、図示する出力特性をうるためには、抵抗4
3,44の値にくらべて抵抗47,48の値を小
さく選定すればよい。
By the way, as shown in the figure, the output characteristics in the fine adjustment range A and the coarse adjustment range B are different; and 4
This can be obtained by changing the gain of the differential amplifier by selecting the resistance values of 7 and 48. That is, in order to obtain the output characteristics shown in the figure, the resistor 4
The values of resistors 47 and 48 may be selected to be smaller than the values of resistors 3 and 44.

なお、電源電圧Vccの温度ならびに温度変化に
対して回路動作の安定化をはかるためには、抵抗
30と32,31と33,43と44,47と4
8,50と57,51と58,53と59ならび
に54と60の値をそれぞれ等しく選定すること
がのぞましい。
Note that in order to stabilize the circuit operation against the temperature of the power supply voltage Vcc and temperature changes, resistors 30 and 32, 31 and 33, 43 and 44, 47 and 4 are required.
Preferably, the values of 8, 50 and 57, 51 and 58, 53 and 59 and 54 and 60 are chosen to be equal.

以上説明してきたところから明らかなように、
本発明の直流利得制御装置では、電源電圧Vcc
ら零ボルトまで変化する制御電圧によつて出力特
性の異る微調整と粗調整の双方の回路が形成され
しかも、出力特性を差動増幅器の構成要素である
抵抗の値の選定によつて決定することができるた
め、特別に周辺回路を設けることが不要となる。
また、本発明の直流利得制御装置は、可変抵抗1
2を除き全てIC化が可能な回路要素で構成され
ており、これをIC化することも容易である。さ
らに、従来の直流利得制御装置のように、機器内
へ組み込んだのち、微調整を行なつておく必要は
なく、したがつて、機器製作の工程から調整工程
を排除することができる。
As is clear from what has been explained above,
In the DC gain control device of the present invention, both fine adjustment and coarse adjustment circuits with different output characteristics are formed by the control voltage varying from the power supply voltage Vcc to zero volts. Since it can be determined by selecting the value of the resistor as a component, it is not necessary to provide a special peripheral circuit.
Further, the DC gain control device of the present invention has a variable resistor 1
All except 2 are composed of circuit elements that can be integrated into ICs, and it is easy to integrate them into ICs. Further, unlike conventional DC gain control devices, there is no need to make fine adjustments after incorporating the device into a device, and therefore, an adjustment step can be eliminated from the device manufacturing process.

なお、以上の説明はカラーテレビジヨン受像機
の色飽和度あるいは色相の制御を例に行なつた
が、本発明は、利得制御機能の付加される他の機
器に広く適用して同様の効果が奏される。
Although the above explanation has been made using the control of color saturation or hue of a color television receiver as an example, the present invention can be widely applied to other devices equipped with a gain control function to achieve similar effects. It is played.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の直流利得制御装置の構成を示す
図、第2図は同装置を用いた場合の出力特性曲線
を示す図、第3図は本発明の直流利得制御装置の
構成を示すブロツク図、第4図は本発明の直流利
得制御装置の具体的な構成を示す回路図、第5図
は本発明の直流利得制御装置を用いた場合の出力
特性を示す図である。 1……電源電圧印加端子、2,4,6〜8……
固定抵抗、3,9,12……可変抵抗、5……半
固定抵抗、10……スイツチ手段、11……利得
制御回路、13……制御電圧発生点、14……レ
ベル検出器、15……スイツチ回路部、16……
直流バイアス供給回路部、171,172……差
動増幅器、18……利得制御電圧発生回路部、1
9,20……利得制御用電圧出力端子、21,2
2……スイツチトランジスタ、23〜27……第
1の直流バイアス供給回路構成用の抵抗、28…
…ダイオード、29……第1の直流バイアス供給
回路構成用のトランジスタ、30〜33……電圧
分割用抵抗、34,35……スイツチ回路部構成
用トランジスタ、36……電流源用トランジス
タ、37,43,44,47,48,50,5
1,53,54,57〜60……エミツタ抵抗、
38〜40……基準バイアス発生用の第2の直流
バイアス供給回路を構成する抵抗、49,52,
55,56,61,62……エミツタフオロワト
ランジスタ。
FIG. 1 is a diagram showing the configuration of a conventional DC gain control device, FIG. 2 is a diagram showing an output characteristic curve when the same device is used, and FIG. 3 is a block diagram showing the configuration of the DC gain control device of the present invention. 4 is a circuit diagram showing a specific configuration of the DC gain control device of the present invention, and FIG. 5 is a diagram showing the output characteristics when the DC gain control device of the present invention is used. 1... Power supply voltage application terminal, 2, 4, 6-8...
Fixed resistor, 3, 9, 12... Variable resistor, 5... Semi-fixed resistor, 10... Switch means, 11... Gain control circuit, 13... Control voltage generation point, 14... Level detector, 15... ...Switch circuit section, 16...
DC bias supply circuit section, 171, 172... Differential amplifier, 18... Gain control voltage generation circuit section, 1
9, 20... Voltage output terminal for gain control, 21, 2
2...Switch transistor, 23-27...Resistor for first DC bias supply circuit configuration, 28...
...Diode, 29...Transistor for configuring the first DC bias supply circuit, 30-33...Resistor for voltage division, 34, 35...Transistor for configuring the switch circuit section, 36...Transistor for current source, 37, 43, 44, 47, 48, 50, 5
1, 53, 54, 57-60...emitter resistance,
38-40...Resistors forming a second DC bias supply circuit for generating reference bias, 49, 52,
55, 56, 61, 62... Emitter follower transistor.

Claims (1)

【特許請求の範囲】 1 可変直流電圧のレベルを検出するレベル検出
器、2つの電流路をもち、前記レベル検出器から
の出力で電流路のいずれか一方を閉成、他方を開
放するスイツチ動作を実行するスイツチ回路部、
同スイツチ回路部の各電流路を介して電流源へ二
者択一的に接続されるとともに、利得が異る値に
選定された第1および第2の差動増幅器、同第1
および第2の差動増幅器の各一方の端子に、前記
レベル検出器の切り換え動作実行時の可変直流レ
ベルより高い値の第1の基準電圧と、低い値の第
2の基準電圧との異る大きさの基準電圧を供給す
るバイアス供給回路、前記第1および第2の差動
増幅器の出力を合成し利得制御用電圧を発生する
利得制御用電圧発生回路を備えるとともに、前記
第1および第2の差動増幅器の他方の入力端子へ
前記可変直流電圧より得た所定の制御電圧を印加
してなることを特徴とする直流利得制御装置。 2 差動増幅器の基準電圧入力端子および制御電
圧入力端子と、バイアス供給回路の電圧発生点お
よび可変直流電圧発生点との間に同一構成のエミ
ツタフオロワ回路が配置されていることを特徴と
する特許請求の範囲第1項に記載の直流利得制御
装置。
[Claims] 1. A level detector that detects the level of a variable DC voltage, having two current paths, and a switch operation that closes one of the current paths and opens the other by the output from the level detector. The switch circuit section that executes
first and second differential amplifiers which are alternatively connected to the current source via each current path of the switch circuit section and whose gains are selected to have different values;
and a first reference voltage having a higher value than the variable DC level at the time of execution of the switching operation of the level detector and a second reference voltage having a lower value at each one terminal of the second differential amplifier. a bias supply circuit that supplies a reference voltage of the same magnitude; a gain control voltage generation circuit that combines the outputs of the first and second differential amplifiers to generate a gain control voltage; A DC gain control device characterized in that a predetermined control voltage obtained from the variable DC voltage is applied to the other input terminal of the differential amplifier. 2. A patent claim characterized in that an emitter follower circuit having the same configuration is arranged between the reference voltage input terminal and control voltage input terminal of the differential amplifier and the voltage generation point and variable DC voltage generation point of the bias supply circuit. The DC gain control device according to item 1.
JP15041179A 1979-11-19 1979-11-19 Dc gain control device Granted JPS5672509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15041179A JPS5672509A (en) 1979-11-19 1979-11-19 Dc gain control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15041179A JPS5672509A (en) 1979-11-19 1979-11-19 Dc gain control device

Publications (2)

Publication Number Publication Date
JPS5672509A JPS5672509A (en) 1981-06-16
JPS6228888B2 true JPS6228888B2 (en) 1987-06-23

Family

ID=15496355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15041179A Granted JPS5672509A (en) 1979-11-19 1979-11-19 Dc gain control device

Country Status (1)

Country Link
JP (1) JPS5672509A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58146115A (en) * 1982-02-25 1983-08-31 Mitsubishi Electric Corp Sound volume controller

Also Published As

Publication number Publication date
JPS5672509A (en) 1981-06-16

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