JPS6228885B2 - - Google Patents

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Publication number
JPS6228885B2
JPS6228885B2 JP55090234A JP9023480A JPS6228885B2 JP S6228885 B2 JPS6228885 B2 JP S6228885B2 JP 55090234 A JP55090234 A JP 55090234A JP 9023480 A JP9023480 A JP 9023480A JP S6228885 B2 JPS6228885 B2 JP S6228885B2
Authority
JP
Japan
Prior art keywords
terminal
circuit
transistors
resistor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55090234A
Other languages
Japanese (ja)
Other versions
JPS5723306A (en
Inventor
Yoshiaki Sano
Toshio Hanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9023480A priority Critical patent/JPS5723306A/en
Publication of JPS5723306A publication Critical patent/JPS5723306A/en
Publication of JPS6228885B2 publication Critical patent/JPS6228885B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は、音声帯域で使用される前置増幅系或
いは出力増幅系の集積化された増幅回路に係り、
特に1つの外部端子を電源リツプルの抑圧比改善
と音声出力遮断に共用した増幅回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated amplifier circuit for a preamplification system or an output amplification system used in the audio band.
In particular, the present invention relates to an amplifier circuit in which one external terminal is shared for improving the suppression ratio of power supply ripples and for cutting off audio output.

増幅器などを集積化する際、多機能化と外部端
子数の低減は矛盾した要求となる。第1図は最少
の外部端子と外付部品で構成した音声帯域の出力
増幅器の回路例で、入力端子Aに供給される音声
信号INを増幅して端子Dに出力する。Eは電源
端子、Cは接地端子で、端子D,C間に直流遮断
用のコンデンサC2と負荷RL(例えばスピーカ)
が外付けで接続される。Bも外付け用の端子で、
ここには該端子Bを交流的に接地しまた電源リツ
プルを抑圧する機能を持つコンデンサC1が外付
けされる。R1〜R4は抵抗、Q1〜Q3はトランジス
タ、VBは定電圧源、A1は増幅器であり、これら
はICチツプ内に集積化されたものである。端子
Aからの入力INは一定値のバイアス電圧VBに重
畳されて増幅器A1の+側入力に印加される。増
幅器A1の出力の一部は帰還抵抗R4を通して−側
入力に帰還されるが、この−側端子と端子Bとの
間には抵抗R4と共に帰還量を定める抵抗R3が接
続される。端子E,C間に接続された抵抗R2
よびダイオード接続されたトランジスタQ1
Q2、及び該Q2の電圧VBEをベース入力電圧とす
るトランジスタQ3は定電流源を構成し、これと
抵抗R3,R4とで出力端子Dの電位決定を行な
う。
When integrating amplifiers and the like, increasing functionality and reducing the number of external terminals are contradictory demands. FIG. 1 shows an example of a circuit of an audio band output amplifier constructed with a minimum number of external terminals and external components, in which an audio signal IN supplied to input terminal A is amplified and output to terminal D. E is the power supply terminal, C is the ground terminal, and between terminals D and C, connect a capacitor C 2 for DC cutoff and a load R L (for example, a speaker).
is connected externally. B is also an external terminal,
A capacitor C1 is externally connected here, which has the function of grounding the terminal B in an alternating current manner and suppressing power supply ripples. R 1 to R 4 are resistors, Q 1 to Q 3 are transistors, V B is a constant voltage source, and A 1 is an amplifier, which are integrated within the IC chip. The input IN from the terminal A is superimposed on a constant value bias voltage V B and applied to the + side input of the amplifier A1 . A part of the output of amplifier A 1 is fed back to the negative input through feedback resistor R 4 , and between this negative terminal and terminal B, resistor R 3 is connected along with resistor R 4 to determine the amount of feedback. . A resistor R 2 connected between terminals E and C and a diode-connected transistor Q 1 ,
Q 2 and a transistor Q 3 whose base input voltage is the voltage V BE of Q 2 constitute a constant current source, and the potential of the output terminal D is determined by this and resistors R 3 and R 4 .

即ち、この回路では図示しないが増幅器A1
出力段はプツシユプルであり、しかも単一電源で
動作するので出力は端子DとグランドCから取出
すことになり、そのまゝでは端子Dの直流電位が
不定であるので、帰還回路R3,R4、およびトラ
ンジスタQ3の経路で端子Dの電位決定を行な
う。今、トランジスタQ1〜Q3が同一形状でその
ベース、エミツタ間電圧VBEが等しく、またVB
=VBEであり、さらに増幅器A1の入力バイアス
電流が小さくオフセツト電圧が零であると仮定す
れば、増幅器A1の+側端子と−側端子の電位は
等しいので、端子Dの直流出力電位V0は、−側端
子の電位VBに抵抗R4による電圧降下分を加えた
値となる。ここで、抵抗R4,R3およびトランジ
スタQ3を流れる電流I4は抵抗R2およびトランジス
タQ1,Q2を流れる電流と等しいので、端子Dの
直流出力電位V0はは、 V0=VB+R4・I4 =VBE+R4・(VCC−2VBE)/R2 =R/RCC+(1−2R/R)VBE となる。従つて R/R=1/2 に設定すれば V0=VCC/2 となるので、増幅器A1の出力駆動がVCC側と
GND側で近似した飽和条件であれば出力波形は
正、負対称に飽和し、しかも電源変動に追随して
最適に制御される。
In other words, although not shown in this circuit, the output stage of amplifier A1 is push-pull, and since it operates with a single power supply, the output is taken from terminal D and ground C, and if this is done, the DC potential of terminal D will be Since it is undefined, the potential of terminal D is determined through the path of feedback circuits R 3 , R 4 and transistor Q 3 . Now, transistors Q 1 to Q 3 have the same shape and have the same base-to-emitter voltage V BE , and V B
= V BE and further assuming that the input bias current of amplifier A 1 is small and the offset voltage is zero, the potentials of the + and - terminals of amplifier A 1 are equal, so the DC output potential of terminal D is V 0 is a value obtained by adding the voltage drop caused by the resistor R 4 to the potential V B of the negative terminal. Here, the current I 4 flowing through the resistors R 4 and R 3 and the transistor Q 3 is equal to the current flowing through the resistor R 2 and the transistors Q 1 and Q 2 , so the DC output potential V 0 of the terminal D is V 0 = V B +R 4 ·I 4 =V BE +R 4 ·(V CC −2V BE )/R 2 =R 4 /R 2 V CC +(1−2R 4 /R 2 )V BE . Therefore, if R 4 /R 2 = 1/2, then V 0 =V CC /2, so the output drive of amplifier A1 is on the V CC side.
If the saturation conditions are similar on the GND side, the output waveform will saturate symmetrically in positive and negative directions, and will be optimally controlled by following power fluctuations.

一方、増幅器A1が充分な利得を有していれば
総合利得AVは帰還回路により決定され、 AV=1+R/R で与えられる。
On the other hand, if the amplifier A 1 has sufficient gain, the overall gain A V is determined by the feedback circuit and is given by A V =1+R 4 /R 3 .

ところで、直流電源VCCにリツプル電圧が重畳
しているとその変化は先ず抵抗R2およびトラン
ジスタQ1〜Q3からなる定電流源の電流値変化と
なつて現われ、これはコンデンサC1によりバイ
パスされ(平滑化され)るが、若干は端子Bの電
位変化として現われる。特にリツプル電圧が低周
波であるとコンデンサC1のバイパス効果が期待
できず、該リツプル電圧が抵抗R3,R4を通して
(R4/R3倍されて)出力端Dに現われることにな
る。この点を改善するためにトランジスタQ1
コレクタ端子に外部容量を付加して抵抗R2と共
に平滑回路を構成させ、端子Bに現われる電源リ
ツプルを低減させる方法があるが、これには該外
部容量を外付けするための外部端子が必要にな
り、しかもこれはリツプル抑圧率の改善だけを目
的としたものであるから、ピン数節減が要求され
るICには好ましくない。
By the way, when a ripple voltage is superimposed on the DC power supply V CC , the change first appears as a change in the current value of the constant current source consisting of resistor R 2 and transistors Q 1 to Q 3 , which is bypassed by capacitor C 1 . (smoothed), but some appears as a potential change at terminal B. In particular, if the ripple voltage has a low frequency, the bypass effect of the capacitor C1 cannot be expected, and the ripple voltage will appear at the output terminal D through the resistors R3 and R4 (multiplied by R4 / R3 ). In order to improve this point, there is a method of adding an external capacitor to the collector terminal of the transistor Q 1 and forming a smoothing circuit together with the resistor R 2 to reduce the power supply ripple appearing at the terminal B. This requires an external terminal for external connection, and since this is only intended to improve the ripple suppression rate, it is not desirable for ICs that require a reduction in the number of pins.

一般に多機能化、高集積化に伴ないICの所要
外部端子数は増加傾向を示すが、ICの寸法から
端子数には制約があり、しかもパツケージは標準
化されているので1ピン増加は2〜3ピンも多い
次のグレードのパツケージを要求することにな
る。従つて、リツプル抑圧率の改善に外部端子を
使用するとしても、その端子はできれば他用途に
も兼用されることが望ましい。端子も、電源端子
のように必らず常時使用されるもの、ある種の信
号入出力端子のように一時的に使用されるもの、
一方が使用される場合他方は必らず休止の状態に
あるものなど種々ある。特に後者の場合は一端子
を両者で兼用することが可能であることが考えら
れる。
In general, the number of external pins required for ICs tends to increase as ICs become more multi-functional and highly integrated, but there are restrictions on the number of pins due to the size of the IC, and since packages are standardized, an increase of 1 pin is 2 to 2. This will require the next grade package with more 3 pins. Therefore, even if an external terminal is used to improve the ripple suppression rate, it is desirable that the terminal be used for other purposes as well. Terminals also include those that are always used, such as power supply terminals, and those that are used temporarily, such as certain signal input/output terminals.
There are various types, such as when one is used, the other is always in a dormant state. Particularly in the latter case, it is conceivable that one terminal can be used for both.

本発明はかゝる観点でなされたもので、音声入
力を増幅する回路を集積化した増幅回路におい
て、チツプ内該回路に電源リツプル抑圧回路と直
流制御電圧で動作する音声遮断回路とを設け、ま
たチツプに部品外付け用の端子を設けて該端子
に、前記電源リツプル抑圧回路のコンデンサを外
付けすると共に前記音声遮断回路の入力端を接続
したことを特徴とするが、以下図示の実施例を参
照しながらこれを詳細に説明する。
The present invention has been made from this point of view, and includes an amplifier circuit that integrates a circuit for amplifying audio input, in which a power supply ripple suppression circuit and an audio cutoff circuit that operates with a DC control voltage are provided in the circuit within the chip. The chip is also characterized in that a terminal for externally attaching components is provided, and a capacitor of the power supply ripple suppression circuit is externally attached to the chip, and an input end of the audio cutoff circuit is connected to the terminal. This will be explained in detail with reference to.

第2図は本発明の一実施例を示す回路図で、第
1図と同一部分には同一符号が付してある。本回
路は第1図の回路に電源リツプル抑圧回路10を
設け、且つ外部的には端子Fを追加し、それにリ
ツプル改善用のコンデンサC3を外付けで接続し
たものである。なおこの端子Fには第3図bに示
すように出力遮断用のトランジスタQ9のベース
を接続し、端子Fに直流制御電圧を印加して該ト
ランジスタQ9をオンにし、出力遮断が可能なよ
うにしている。抑圧回路10はトランジスタQ4
〜Q7、ダイオードQ8および抵抗R5〜R7からな
り、ベース相互間を接続したpnpトランジスタ対
Q5,Q6およびnpnトランジスタ対Q4,Q7はそれ
ぞれ同一寸法であり、またR5=R7に設定されて
いる。トランジスタQ5,Q4および抵抗R5からな
る直列回路は電源VCCとアースGND間に直列に
接続されるだけであるが、これと並列なトランジ
スタQ6,Q7および抵抗R7からなる直列回路はト
ランジスタQ6,Q7の接続点(コレクタ)が端子
Bに接続される。トランジスタQ5,Q6のベース
はトランジスタQ5のコレクタに共通接続され、
またトランジスタQ4,Q7のベースはトランジス
タQ3のベースと共通に接続され、共に同じベー
ス電圧を受ける。この結線によりトランジスタ
Q5,Q6のコレクタ電流及びトランジスタQ4,Q7
のコレクタ電流が等しくなり、かつQ5,Q4のコ
レクタ電流は同一のものであるから、Q6のコレ
クタ電流I2はQ5,Q4のコレクタ電流I1に等しく、
更にQ7のコレクタ電流I3にも等しいことになる。
つまりトランジスタQ6のコレクタ電流I2が端子B
へ流入するように見えるがそれと等しい電流I3
トランジスタQ7を通して吸収されるので、端子
Bの電位が電流I2,I3、ひいては抑圧回路10の
影響を受けることはない。
FIG. 2 is a circuit diagram showing an embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals. This circuit is obtained by adding a power supply ripple suppression circuit 10 to the circuit shown in FIG. 1, and adding a terminal F externally to which a ripple improvement capacitor C3 is connected externally. Note that the base of a transistor Q9 for output cutoff is connected to this terminal F as shown in Figure 3b, and a DC control voltage is applied to terminal F to turn on the transistor Q9 , making it possible to cut off the output. That's what I do. The suppression circuit 10 is a transistor Q4
A pair of pnp transistors consisting of ~Q 7 , diode Q 8 and resistors R 5 ~R 7 , whose bases are connected together.
Q 5 , Q 6 and the npn transistor pair Q 4 , Q 7 have the same dimensions, and R 5 =R 7 . The series circuit consisting of transistors Q 5 , Q 4 and resistor R 5 is simply connected in series between the power supply V CC and earth GND, but the series circuit consisting of transistors Q 6 , Q 7 and resistor R 7 in parallel is connected in series between the power supply V CC and earth GND. In the circuit, the connection point (collector) of transistors Q 6 and Q 7 is connected to terminal B. The bases of transistors Q 5 and Q 6 are commonly connected to the collector of transistor Q 5 ,
Further, the bases of transistors Q 4 and Q 7 are commonly connected to the base of transistor Q 3 and both receive the same base voltage. This connection allows the transistor to
Collector current of Q 5 , Q 6 and transistors Q 4 , Q 7
Since the collector currents of are equal and the collector currents of Q 5 and Q 4 are the same, the collector current I 2 of Q 6 is equal to the collector current I 1 of Q 5 and Q 4 ,
Furthermore, it is also equal to the collector current I3 of Q7 .
In other words, the collector current I2 of transistor Q6 is at terminal B
The potential at terminal B is not influenced by currents I 2 and I 3 and therefore by the suppression circuit 10, since the current I 3 which appears to flow into but is equal to it is absorbed through transistor Q 7 .

これに対し電源VCCにリツプル成分があるとト
ランジスタQ2,Q3……のベース電位がそれに応
じて若干変動し、トランジスタQ3のコレクタ電
流が変動し端子Bにはリツプル成分に応じた電圧
変動が生じようとするが、この電圧変動に対し、
端子Fとアース間に接続したコンデンサC3並び
に端子FとトランジスタQ4のエミツタおよびダ
イオードD8のアノードとの間に接続した抵抗R6
が抑制動作をする。つまり、リツプル成分によつ
てトランジスタQ3に電流I4が流れるときはトラン
ジスタQ4のコレクタ電流も増大する。即ちQ2
Q3……のベース電圧が増大するとQ4のベース、
エミツタ、抵抗R5またはR6、コンデンサC3の経
路でQ4のベース電流が増大し、これがQ4のコレ
クタ電流増大をもたらす。この増分をI1′とする
と等量の電流I2′(電流I2の増分)が同じくトラン
ジスタQ6のコレクタから流出する。しかし、ト
ランジスタQ7は、ベース電位の増大でQ7ベー
ス、同エミツタ、抵抗R7の経路でベース電流が
若干増大するもののQ4のようにR6,C3を通る経
路はないので該増大は僅小にとどまり(本来
R5,R7は負帰還機能をもつ)、このためQ7のコレ
クタ電流は殆んどI3のままである。従つて、トラ
ンジスタQ6の増大したコレクタ電流I′2はB点に
流入する。これは電流I4と逆相であるから、抵抗
R6の値を設定して|I′2|=|I4|とすれば電流I′2
とI4は端子Bで相殺され、リツプルによる端子電
圧の変動は抑圧される。リツプルが逆極性のとき
はI4の極性が逆(Q3コレクタ電流減少)I′1,I′2
も逆極性つまりI1,I2減少であり(このときはQ4
のベース電位低下に加えてC3のR6,R5を通る放
電があつてQ4をオフ方向にドライブする)、Q7
コレクタ電流もベース電位低下に加えてC3
R6,Q8,R7を通る放電があるので減少するが、
その程度はQ8の電圧降下があるのでQ4ほど著し
くはない。この結果Q3のコレクタ電流の減少を
Q7による端子B回路からのI2,I3の差分吸収で補
償し、端子Bにリツプル電圧が現われるのを阻止
する。
On the other hand, if there is a ripple component in the power supply V CC , the base potential of transistors Q 2 , Q 3 , etc. will vary slightly accordingly, the collector current of transistor Q 3 will fluctuate, and terminal B will have a voltage corresponding to the ripple component. Fluctuations are about to occur, but for this voltage fluctuation,
Capacitor C 3 connected between terminal F and earth, and resistor R 6 connected between terminal F and the emitter of transistor Q 4 and the anode of diode D 8
acts as a suppressor. That is, when current I4 flows through transistor Q3 due to the ripple component, the collector current of transistor Q4 also increases. That is, Q 2 ,
When the base voltage of Q 3 ... increases, the base of Q 4 ,
The base current of Q 4 increases through the path of the emitter, resistor R 5 or R 6 , and capacitor C 3 , which causes an increase in the collector current of Q 4 . If this increment is I 1 ', an equal amount of current I 2 ' (an increment in current I 2 ) also flows out from the collector of transistor Q 6 . However, in transistor Q 7 , as the base potential increases, the base current increases slightly through the path between the Q 7 base, its emitter, and resistor R 7 , but unlike Q 4 , there is no path passing through R 6 and C 3 , so the base current increases. remains very small (originally
R 5 and R 7 have a negative feedback function), so the collector current of Q 7 remains almost the same as I 3 . Therefore, the increased collector current I'2 of transistor Q6 flows into point B. This is in reverse phase with the current I 4 , so the resistance
If the value of R 6 is set and |I′ 2 |= |I 4 |, then the current I′ 2
and I 4 are canceled out at terminal B, and fluctuations in terminal voltage due to ripples are suppressed. When the ripple has the opposite polarity, the polarity of I 4 is reversed (Q 3 collector current decreases) I′ 1 , I′ 2
is also opposite polarity, that is, I 1 and I 2 decrease (in this case, Q 4
In addition to the base potential drop of C 3 , a discharge passes through R 6 and R 5 of C 3 and drives Q 4 in the off direction), and in addition to the base potential drop, the collector current of Q 7 also
It decreases because there is a discharge passing through R 6 , Q 8 , and R 7 , but
The degree of this is not as significant as Q 4 because of the voltage drop in Q 8 . This results in a decrease in the collector current of Q3 .
The differential absorption of I 2 and I 3 from the terminal B circuit by Q 7 compensates and prevents ripple voltage from appearing at terminal B.

上述した増幅回路は外部的には端子Fが追加さ
れただけのもので、これにコンデンサC3を外付
けすればリツプル抑圧比が改善される。これに対
し、端子Fに一定の直流電位を与えるとQ4,Q7
抑圧回路10はないのと同じになり全体は第1図
と等価になる。そして第3図のような回路を付加
すれば端子Fを音声出力遮断機能にも兼用でき
る。同図aは端子Fに直流電位VSを与える回路
例で、スイツチSWをオンにすると抵抗Rを通し
て端子FがVSとなり、第2図のトランジスタ
Q4,Q7のエミツタ電位がいずれも上昇してトラ
ンジスタQ4〜Q7が全てオフとなる。同図bは第
2図の回路に付加される音声遮断回路20の回路
例である。該回路20は端子Aと定電圧源VB
の間に挿入された抵抗R8(省略も可)、この抵抗
R8の出力側を接地するトランジスタQ9、および
そのベース抵抗R9からなり、スイツチSWを閉じ
て端子Fを直流電位VSにするとトランジスタQ9
がオンとなり、端子Aからの音声入力INをアー
スへ引込む。従つて出力端子Dからの音声出力は
遮断される。これに対しスイツチSWを開放すれ
ばトランジスタQ9がオフとなるので音声入力IN
は増幅器A1へ導びかれ、同時に第2図の抑圧回
路10が動作可能となる。
The above-mentioned amplifier circuit has only a terminal F added externally, and if a capacitor C3 is externally attached to this, the ripple suppression ratio can be improved. On the other hand, if a constant DC potential is applied to terminal F, Q 4 , Q 7
It is the same as if the suppression circuit 10 were not provided, and the whole becomes equivalent to that shown in FIG. By adding a circuit as shown in FIG. 3, terminal F can also be used for the audio output cutoff function. Figure a shows an example of a circuit that applies a DC potential V S to the terminal F. When the switch SW is turned on, the terminal F becomes V S through the resistor R, and the transistor shown in Figure 2
The emitter potentials of Q 4 and Q 7 both rise and transistors Q 4 to Q 7 are all turned off. FIG. 2B shows an example of the audio cutoff circuit 20 added to the circuit shown in FIG. The circuit 20 includes a resistor R8 (optional) inserted between the terminal A and the constant voltage source VB , and this resistor.
It consists of a transistor Q 9 which grounds the output side of R 8 and its base resistor R 9. When the switch SW is closed and the terminal F is set to a DC potential V S , the transistor Q 9
turns on and draws the audio input IN from terminal A to ground. Therefore, audio output from output terminal D is cut off. On the other hand, if the switch SW is opened, transistor Q9 is turned off, so the audio input IN
is guided to the amplifier A1 , and at the same time the suppression circuit 10 of FIG. 2 becomes operational.

第4図はトランジスタQ1〜Q7の他の接続例
で、aはトランジスタQ2,Q3のエミツタにも抵
抗R10,R11を挿入したもの、bはトランジスタ
Q1をダイオード接続しないで用いたもの(抵抗
R10は省略可)cはダイオードQ8を用いる代りに
トランジスタQ4,Q7のエミツタ例に抵抗R′5
R′7,R12からなる直並列回路を並列したものであ
る。
Figure 4 shows another example of the connection of transistors Q 1 to Q 7 , where a shows resistors R 10 and R 11 are also inserted into the emitters of transistors Q 2 and Q 3 , and b shows the transistor
Q1 used without diode connection (resistance
( R10 can be omitted) Instead of using the diode Q8 , the resistor R'5 is used as the emitter of the transistors Q4 and Q7 .
This is a parallel series series-parallel circuit consisting of R′ 7 and R 12 .

以上述べたように本発明によれば、音声信号を
増幅する集積化された回路の1つの外部端子を、
音声遮断とリツプル抑圧比の改善に使い分けるこ
とができるので、ICチツプの多機能化に伴なう
外部端子数の増加を極力抑制し得る利点がある。
As described above, according to the present invention, one external terminal of an integrated circuit for amplifying an audio signal can be connected to
Since it can be used for both audio isolation and improvement of the ripple suppression ratio, it has the advantage of minimizing the increase in the number of external terminals that accompanies the multifunctionalization of IC chips.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は音声帯域で使用される従来の出力増幅
器の回路図、第2図は本発明の一実施例を示す回
路図、第3図a,bは第2図の増幅回路に音声遮
断機能を付加する際の外部および内部追加回路の
構成図、第4図a〜cは第2図の変形例を示す要
部回路図である。 図中、10は電源リツプル抑圧回路、20は音
声遮断回路、Fは制御用の外部端子、C3はリツ
プル改善用のコンデンサである。
Figure 1 is a circuit diagram of a conventional output amplifier used in the audio band, Figure 2 is a circuit diagram showing an embodiment of the present invention, and Figures 3a and b are the amplifier circuits in Figure 2 with an audio cutoff function. FIGS. 4a to 4c are main part circuit diagrams showing a modification of FIG. 2. In the figure, 10 is a power supply ripple suppression circuit, 20 is an audio cutoff circuit, F is an external terminal for control, and C3 is a ripple improvement capacitor.

Claims (1)

【特許請求の範囲】 1 一方の入力端に音声信号を入力され、他方の
入力端に帰還抵抗R3,R4回路を接続され、該帰
還抵抗回路には電源電圧に応じた直流電流が流さ
れて出力端Dを所望電位にされた集積化増幅回路
において、 直流制御電圧の印加または交流的な接地がされ
る端子Fと、 該端子Fに直流制御電圧が印加されたとき音声
信号線に接続されたトランジスタQ9がオンにな
り前記音声信号をグランドへ落して音声出力を消
滅させる音声遮断回路20と、 電源、グランド間に直列接続された第1、第2
のトランジスタQ5,Q4と抵抗R5および第3、第
4のトランジスタQ6,Q7と抵抗R7を有し、第
1、第3のトランジスタQ5,Q6はカレントミラ
ーに接続され、第2、第4のトランジスタQ4
Q7もカレントミラーに接続され、第3、第4の
トランジスタの直列接続点は前記帰還抵抗回路へ
接続され、第2のトランジスタQ4と抵抗R5の直
列接続点は前記端子Fへ接続され、前記端子Fが
交流的に接地されることにより前記出力端Dの電
位の電源リツプルによる変動を抑圧する回路10
とを備えてなることを特徴とする増幅回路。
[Claims] 1. An audio signal is input to one input terminal, and a feedback resistor R 3 , R 4 circuit is connected to the other input terminal, and a direct current according to the power supply voltage flows through the feedback resistor circuit. In the integrated amplifier circuit, in which the output terminal D is set to a desired potential, there is a terminal F to which a DC control voltage is applied or an AC ground is applied, and when a DC control voltage is applied to the terminal F, an audio signal line is connected to the terminal F. an audio cutoff circuit 20 that turns on the connected transistor Q9 and drops the audio signal to the ground to eliminate the audio output; and a first and second circuit connected in series between the power supply and the ground.
transistors Q 5 and Q 4 and a resistor R 5 and third and fourth transistors Q 6 and Q 7 and a resistor R 7 , and the first and third transistors Q 5 and Q 6 are connected to a current mirror. , second and fourth transistors Q 4 ,
Q 7 is also connected to the current mirror, the series connection point of the third and fourth transistors is connected to the feedback resistor circuit, and the series connection point of the second transistor Q 4 and resistor R 5 is connected to the terminal F. , a circuit 10 that suppresses fluctuations in the potential of the output terminal D due to power supply ripples by grounding the terminal F in an alternating current manner.
An amplifier circuit comprising:
JP9023480A 1980-07-02 1980-07-02 Amplifying circuit Granted JPS5723306A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9023480A JPS5723306A (en) 1980-07-02 1980-07-02 Amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9023480A JPS5723306A (en) 1980-07-02 1980-07-02 Amplifying circuit

Publications (2)

Publication Number Publication Date
JPS5723306A JPS5723306A (en) 1982-02-06
JPS6228885B2 true JPS6228885B2 (en) 1987-06-23

Family

ID=13992792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9023480A Granted JPS5723306A (en) 1980-07-02 1980-07-02 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS5723306A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106581U (en) * 1987-12-28 1989-07-18

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5060708B2 (en) * 2004-12-15 2012-10-31 パナソニック株式会社 High frequency integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106581U (en) * 1987-12-28 1989-07-18

Also Published As

Publication number Publication date
JPS5723306A (en) 1982-02-06

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