JPS6228845A - Software quality evaluation system - Google Patents
Software quality evaluation systemInfo
- Publication number
- JPS6228845A JPS6228845A JP60167579A JP16757985A JPS6228845A JP S6228845 A JPS6228845 A JP S6228845A JP 60167579 A JP60167579 A JP 60167579A JP 16757985 A JP16757985 A JP 16757985A JP S6228845 A JPS6228845 A JP S6228845A
- Authority
- JP
- Japan
- Prior art keywords
- bug
- testing process
- presuming
- quality
- bugs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は品質評価方式に係り、特にテスト(チェック)
工程を持つソフトウェアに好適な品質評価に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a quality evaluation method, and particularly to a test (check)
Concerning quality evaluation suitable for software with processes.
従来の発表及び文献(電気通信学会論文昭49−225
CD −44)情報処理学会第25口金国大会。Previous presentations and literature (The Institute of Electrical Communication Engineers paper 1972-225
CD-44) Information Processing Society of Japan 25th National Conference.
1g−1、IE−8)は、残バグ件数の推定又は摘出効
率に関するものか、品質の目標値管理については開発段
階と提供後のバグ件数といりた大雑把な区分での適用に
関するものである。すなわち、いずれも一つの方法論で
推定したものであり、4つの残バグ推定法を組合せて、
テスト工程の全般で精度の良い推定値を予測し、実積値
との比較・評価を自動的に行う例はない。1g-1, IE-8) are related to estimation of the number of remaining bugs or extraction efficiency, or regarding quality target value management, they are related to application in rough categories such as the development stage and the number of bugs after delivery. . In other words, all of them are estimated using one methodology, and by combining the four remaining bug estimation methods,
There is no example of predicting highly accurate estimated values throughout the testing process and automatically comparing and evaluating them with actual values.
本発明の目的は精度の高いソフトウェアの品質評価方式
を提供することにある。An object of the present invention is to provide a highly accurate software quality evaluation method.
本発明はソフトウェアの品質をいくつかある残バグ推定
法を組合せて精度の良い評価をする方式である。従来例
では残バグ推定法により、テスト工程毎に推定精度が異
なっており、使い方によって精度の面で問題があった。The present invention is a method for accurately evaluating software quality by combining several residual bug estimation methods. In the conventional example, the estimation accuracy differs depending on the test process due to the remaining bug estimation method, and there was a problem in terms of accuracy depending on how it was used.
そこで工程別に推定精度の高い時点をとらえて予測とし
て使い精度の高い評価を可能にした。組合せる残バグ推
定法及びテスト工程推移と組合せ方式は次紙のとおりで
ある。Therefore, we captured the points at which the estimation accuracy was high for each process and used them as predictions, making it possible to evaluate with high accuracy. The remaining bug estimation methods, test process transitions, and combination methods to be combined are as shown in the next paper.
組合せる残バグ推定法
■ 設計工程での品質要因に基づく作り込みバグ件数推
定法(テスト工程での摘出バグ累積件数との差から残バ
グ推定)
■ テスト工程での品質要因に基づく■の補正法(品質
要因と摘出バグ件数の関係から作り込みバグ件数推定の
補正)
■ 成長曲線あてはめによる残バグ件数推定法(テスト
工程の摘出バグ累積曲線に成長曲線をあてはめ、その飽
和値と実績値との差から残バグ推定)
■ 層別抽出データの一回抜取検査方式による残バグ推
定法(テスト項目のサンプリングにより摘出したバグ件
数から潜在バグ件数を推定:探針)
■〜■の推定法の特徴は表1のとおりであり、組合せた
方式はテスト工程の推移に対応して精度の高い推定法を
選択する。適用方法は第1図のとおりである。ただし現
実的には経験値に基づく他の推定値を考慮する。Combining remaining bug estimation method■ Method for estimating the number of built-in bugs based on quality factors in the design process (estimating remaining bugs from the difference with the cumulative number of bugs extracted in the testing process) ■Correction for ■ based on quality factors in the testing process method (correction of the estimation of the number of built-in bugs based on the relationship between quality factors and the number of extracted bugs) ■ Method for estimating the number of remaining bugs by fitting a growth curve (a growth curve is fitted to the cumulative curve of bugs extracted in the testing process, and its saturation value and actual value are calculated) (estimation of remaining bugs from the difference between) ■ Estimation method of remaining bugs using a single sampling inspection method of stratified data (estimate the number of potential bugs from the number of bugs extracted by sampling test items: probe) Estimation methods of ■ to ■ The characteristics are shown in Table 1, and the combined method selects a highly accurate estimation method in accordance with the transition of the test process. The application method is shown in Figure 1. However, in reality, other estimated values based on empirical values should be considered.
表1 テスト工程別推定値のf#度 〔発明の実施例〕 以下、本発明の一実施例を第2図により説明する。Table 1 f# degree of estimated value by test process [Embodiments of the invention] An embodiment of the present invention will be described below with reference to FIG.
実施例のソフトウェア製品名はSAMPL−01−〇〇
でプログラム名は8AMPLである。SAMPLの規模
は29.6にステップ、テスト回数は4回(テスト工程
は4工程: DD/UD 、CD 、8D、K)である
。The software product name of the example is SAMPL-01-〇〇 and the program name is 8AMPL. The scale of SAMPL is 29.6 steps, and the number of tests is 4 times (4 test steps: DD/UD, CD, 8D, K).
■ 設計工程での品質要因に基づく作り込みバグ件数推
定法は製品規模開発の新規性、高級言語使用率等の9ケ
の品質尺度から推定し、総バグ件数を予測した。その結
果摘出バグ件数の目標値はにステップ当り20件(絶対
件数で604件)を与えた。各工程のDD/UD :
454 、 CD :96、SD+50.に:4と設定
された。■ The method for estimating the number of built-in bugs based on quality factors in the design process estimated the total number of bugs based on nine quality measures such as the novelty of product scale development and high-level language usage rate. As a result, we set a target value of 20 bugs per step (604 bugs in absolute terms). DD/UD of each process:
454, CD: 96, SD+50. :4 was set.
■ テスト工程での品質要因に基づくバグ件数推定法(
第2図−(1)参照)では、にステップあたり28.2
8件(絶対件数837件)が予測された。■ Bug count estimation method based on quality factors in the testing process (
(see Fig. 2-(1)), 28.2 per step
Eight cases (absolute number of cases 837 cases) were predicted.
(詳細図第2図−(3)の目標値欄参照)■ 成長曲線
あてはめによる残バグ件数推定法では■と同様にステッ
プあたり28.3件が予測された。(詳細図第2図−(
3)のF R,CS T欄参照)■ 層別抽出データの
一回抜取検査方式による残バグ推定法ではにステップ当
り26.9件絶対件数(796件)(詳細図第2図−(
3)のQPの欄)この予測値をもとに実績との比較(充
足度)を行い評価する。すなわち、テスト工程前期では
■推定件数を目標値として使い、テスト工程が進むに従
い、推定精度の高い■及び■、■を使って、最終的にそ
れらの充足率を見て総合評価を加え、正常な潜在バグの
摘出を行わせるものである。(Refer to the target value column in Figure 2-(3) for details) ■ The method of estimating the number of remaining bugs by fitting a growth curve predicted 28.3 bugs per step as in ■. (Detailed diagram Figure 2-(
(Refer to column FR, CST in 3))■ In the remaining bug estimation method using the one-time sampling inspection method of stratified extracted data, the absolute number of bugs per step was 26.9 (796) (Detailed Figure 2-(
3) QP column) Based on this predicted value, compare it with the actual results (degree of sufficiency) and evaluate. In other words, in the first half of the testing process, ■ the estimated number of cases is used as the target value, and as the testing process progresses, ■, ■, ■, which have high estimation accuracy are used, and finally, by looking at the fulfillment rate of these, a comprehensive evaluation is added, and it is determined that the number of cases is normal. This allows you to identify potential bugs.
これにより、設計品質テスト方法の評価が自動的にわか
りやす(表示され、早期テスト工程でのバグ摘出促進に
効果がある。As a result, the evaluation of the design quality testing method is automatically displayed in an easy-to-understand manner, which is effective in promoting the detection of bugs in the early testing process.
本発明によれば、ソフトウェアについてテスト工程にお
ける摘出バグ件数の精度の良い目標値に基づき設計品質
・テストのやり方の異常検知かできるので、テスト工程
の早期に対策を講じて低品質出荷・納期遅延の防止に効
果がある。According to the present invention, it is possible to detect abnormalities in design quality and testing methods based on accurate target values for the number of bugs detected in the testing process of software, so countermeasures can be taken early in the testing process to ensure low-quality shipments and delayed delivery. It is effective in preventing.
第1図は本発明の一実施例の説明線図、第2図は同じ〈
実施例の説明図、第3図は同じく処理概要図、第4図は
機器構成を示す斜視図である。Figure 1 is an explanatory diagram of one embodiment of the present invention, and Figure 2 is the same diagram.
An explanatory diagram of the embodiment, FIG. 3 is a processing outline diagram, and FIG. 4 is a perspective view showing the equipment configuration.
Claims (1)
組合せて精度のよい評価をするソフトウェアの品質評価
方式であって、設計工程での品質要因に基づく作り込み
バグ推定法、テスト工程での品質要因に基づく作り込み
バグ推定法、成長曲線あてはめによる残バグ推定法、層
別抽出データの一回抜取検査方式による残バグ推定法の
4種の残バグ推定法を組合せることを特徴とするソフト
ウェアの品質評価方式。1. A software quality evaluation method that accurately evaluates software quality by combining several residual bug estimation methods, including a built-in bug estimation method based on quality factors in the design process, and a quality estimation method in the testing process. Software that combines four types of remaining bug estimation methods: built-in bug estimation method based on factors, remaining bug estimation method using growth curve fitting, and remaining bug estimation method using a one-time sampling inspection method of stratified extracted data. quality evaluation method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60167579A JPS6228845A (en) | 1985-07-31 | 1985-07-31 | Software quality evaluation system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60167579A JPS6228845A (en) | 1985-07-31 | 1985-07-31 | Software quality evaluation system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6228845A true JPS6228845A (en) | 1987-02-06 |
Family
ID=15852362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60167579A Pending JPS6228845A (en) | 1985-07-31 | 1985-07-31 | Software quality evaluation system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6228845A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0377151A (en) * | 1989-08-21 | 1991-04-02 | Fujitsu Ltd | Software quality simulator |
-
1985
- 1985-07-31 JP JP60167579A patent/JPS6228845A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0377151A (en) * | 1989-08-21 | 1991-04-02 | Fujitsu Ltd | Software quality simulator |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9317400B2 (en) | Code coverage rate determination method and system | |
JP2002071575A (en) | Defect inspecting and analyzing method and system therefor | |
JP5116307B2 (en) | Integrated circuit device abnormality detection device, method and program | |
JP6802122B2 (en) | Cause estimation method and program | |
KR101998972B1 (en) | Method of analyzing and visualizing the cause of process failure by deriving the defect occurrence index by variable sections | |
US6551847B2 (en) | Inspection analyzing apparatus and semiconductor device | |
US20030169064A1 (en) | Selective trim and wafer testing of integrated circuits | |
US7962302B2 (en) | Predicting wafer failure using learned probability | |
CN109102486B (en) | Surface defect detection method and device based on machine learning | |
JP3550105B2 (en) | Automatic detection and classification of wafer failure signatures | |
JPS6228845A (en) | Software quality evaluation system | |
CN109285138A (en) | Distributed processing system(DPS) and method for machine vision analysis | |
CN107315664A (en) | Video card automatic checkout system and method | |
JP2000222033A (en) | System and method for specifying abnormality cause | |
CN108931539B (en) | Detector self-checking method, device, medium and radiation type checking system | |
JP4255050B2 (en) | Image processing device | |
US20080215638A1 (en) | Operational qualification by independent reanalysis of data reduction patch | |
JP2000243794A (en) | Analysis of semiconductor wafer | |
JP2000321327A (en) | Apparatus and method for inspecting semiconductor device | |
US7346465B1 (en) | Method of testing the objects in a set to obtain an increased level of quality | |
KR102252326B1 (en) | Systems, methods and computer program products for automatically generating wafer image-to-design coordinate mapping | |
JP7163824B2 (en) | Server device, evaluation method and evaluation program | |
CN113642284B (en) | Method and device for examining circuit schematic diagram, and computer readable storage medium | |
KR20220115820A (en) | System, method and non-transitory computer readable medium for tuning sensitivies of, and determinng a process window for, a modulated wafer | |
WO2024095721A1 (en) | Image processing device and image processing method |