JPS62288065A - Thermal head driving circuit - Google Patents

Abstract

PURPOSE:To perform precise correction before delivery from a factory, by providing ROM to a thermal head to write correction data corresponding to the resistance value of each of head elements and correcting the driving pulse outputted from a shift register of the basis of the correction data. CONSTITUTION:In the writing of ROM9, a current is successively made to flow to each of head elements to be converted to the resistance value thereof and the correction rank of each of the head elements is determined. Voltage is applied to the gate of the electric field effect transistor 15 corresponding to one head element through a latch circuit by utilizing a shift register and a current is made to flow to fuses 14 from a terminal for predetermined data corresponding to the correction rank and, when the predetermined fuse 14 is fused, an H-signal is stored and, when not fused, an L-signal is stored and this operation is performed with respect to ROMs9 corresponding to all or the head elements to complete writing. A comparator 10 compares the correction data of ROM9 with the correction comparing data of a counter to output correction drive data to an AND circuit and outputs a drive pulse which is the combination of fundamental drive data and the correction drive data to each head element and, therefore, the irregularity in color density based on resistance value deviation is eliminated.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention "Industrial Application Field The present invention relates to a thermal head drive circuit equipped with a correction circuit for accurate color reproduction in a color printer with gradation, etc. .

[Summary of the Invention] The present invention provides a thermal head drive circuit in which drive pulses for each of a plurality of head elements are stored in a shift register, and the head element is driven based on the drive pulse of the soft register, comprising: A ROM is provided to record correction data corresponding to variations in the resistance values of each of the ROMs. Based on this correction data, the drive pulses output from the shift register are corrected, and the writing data terminal of the ROM is connected to a thermal head. By providing this, the thermal head drive circuit can be simplified, accurate correction can be made, and the manufactured thermal head can be corrected by itself, so that the thermal head can be corrected to the factory shipment W.

[Prior Art] For example, in a gradation color printer having a thermal head, in order to obtain color density depending on the driving time of the thermal head, the thermal l\rad drive is performed using a pulsed IJ modulation signal (PWM signal) according to the gradation information. A drive control circuit is known (Japanese Unexamined Patent Publication No. 115280/1983).

A conventional thermal head drive circuit that drives a thermal head using such a PWM signal, as shown in FIG.
The drive data corresponding to -, , -240 is thermal head 1.
The data is sent to soft register 6 located at 3. This Schiff)
・All spatula in register 6) ・Element Tl1-]~T! l
-140 drive data is sent, a slow lobe signal is sent from the counter 16 to the latch circuit 7, the latch circuit 7 latches the drive pulse of the shift register 6, and based on the drive data, each head element Tl1- 1-T)I-
240 is driven.

Various correction circuits are used in such a thermal head drive circuit in order to perform accurate color reproduction, and the head element T11-
]~Corrections such as compensation for the resistance value deviation of Tl+-240, substrate temperature compensation, or heat generating pixel number compensation are performed.

Conventionally, for example, a correction circuit was provided in the head control section 20 to perform correction before sending data to the thermal head 13.

[Problems to be Solved by the Invention] However, in the above-mentioned means, a drive pulse is created by superimposing correction data on basic drive data, and this drive pulse is sent to the soft register 6 of the thermosensitive l\tslζ 13. Therefore, the configuration of the head control $20 becomes complicated. Therefore, the thermal head drive circuit becomes complicated, and a high shift clock frequency is required during signal processing, which limits correction and prevents accurate correction.

Furthermore, since the above correction cannot be made unless the thermal head 13 is connected to the head control unit 20, the thermal head 13
The disadvantage was that it could not be corrected before shipping from the factory.

Therefore, the present invention can simplify the heat-sensitive l\rad movement circuit,
Another object of the present invention is to provide a thermal head drive circuit that can perform precise correction and can also correct the thermal head before it is shipped from the factory.

[Means for Solving the Problems] Therefore, the configuration of the present invention for achieving the two-legged objective is as follows:
In a thermal head drive circuit, the thermal head is provided with a plurality of head elements and a shift register that stores drive pulses for each of the head elements, and drives the head elements based on the drive pulses stored in the soft register. RO with a data terminal for writing on the thermal head
The present invention is characterized in that a ROM is provided with correction data corresponding to the resistance value of each of the head elements, and the drive pulse output from the shift register is corrected based on this correction data.

[Function] Therefore, since correction data is added to the basic drive data while it is being output from the shift register in the thermal head to the head element, the drive circuit does not become complicated and it is not necessary to use very high shift clock pulses. High-precision correction can be made without any problems. Furthermore, correction can be made using a heat-sensitive l\rad body using the data terminal for ROM writing.

[Example] Embodiments of the present invention will be described below based on the drawings.

In Figure 1, the printer has 256 dots vertically x 24 dots horizontally.
It is described as being able to produce 16 gradations on a 0-dot print screen.

The pulse generator 1 outputs a shift clock pulse from an output terminal a, and outputs a correction clock pulse from an output terminal a. The minimum correction time width is varied by varying the frequency of this correction clock pulse as described below.

The address counter 2 is supplied with a shift clock pulse from the pulse generator 1, and outputs an address signal for reading out the gradation data stored in the line memory 3. The address counter 2 outputs an address signal for reading out the gradation data stored in the line memory 3, and sends a Garry signal to the gradation counter 4 every time it counts 240. Output to.

The line memory 3 stores gradation data for one vertical line (1 dot - 4 pits), and in accordance with the address signal from the address counter 2, the gradation data is divided from the 1st dot to the 240th dot. The image data up to (4 pits) are sequentially output to the comparator 5 in parallel.

The gradation counter 4 is set to 4 for each gradation in order to compare the image data from the 1st dot to the 240th dot.
The human reference gradation is sequentially outputted to the comparator 5 from the 1st gradation to the 16th gradation.

The comparator 5 compares the gradation data from the line memory 3 with the reference gradation from the gradation counter 4, and outputs an H signal when the gradation data is greater than or equal to the reference gradation; When the signal is smaller than the gradation, the L signal is output to the thermal head 13 as basic drive data.The thermal head 13 includes a shift register 6, head elements TI-1-TH-240, and head elements TI-1-TH-240, as shown in detail in FIG. A latch circuit 7 and a correction circuit 8 are provided.

The software register 6 includes head elements T11-,-
It has a storage capacity capable of storing each drive data of T1 to Tl-240, and stores the drive data sent from the comparator 5 at a predetermined location using the soft clock pulse of the pulse generator 1.

In this embodiment, 240 head elements TH-1 to TH-240 are arranged in parallel, corresponding to 240 horizontal dots.

The latch circuit 7 latches the storage state of the shift register 6 when the Slobe signal is input manually, and this state is output to the correction circuit 8 described below. It also latches the next memory state when the next strobe signal is input manually. The strobe signal ('') is input to the address counter 2 every time 240 H and L signals are input to the soft register 6.
emanates from.

The correction circuit 8, as shown in detail in FIG.
Rad child Tl+-1~T) R, OM (
ReadOnly Memory) 9.

This ROM9 is EPRO, M, mask ROM.

Any electrically writable device such as a fuse ROM may be used, and in this embodiment, a fuse ROM is used. The ROM 9 has writing data terminals T, -T, . . . on the thermal head 13, and correction data corresponding to the resistance value of each of the thermal heads T11-1 to Tl-240 is written. This correction data in the ROM 9 is output to each comparator 10.

The specific configuration of r(0M9 is shown in FIG. 3, and this ROM
9 iJ, three fuses 14, and a storage capacity of 3 bits to divide the correction ranks into 8 ranks.

One end of these three fuses 14 is connected to a bus bar 16 which is connected to the data terminals T9 to Tll through a field effect transistor (FET) 15, and the other ends are connected to the ground terminal T12. ing. The fuse 1 of the other ROM 9 is connected to the bus bar 16 in the same way as above.
4 is connected.

The gate terminal of the field effect transistor 15 is connected to the output terminal of the latch circuit 7. When a voltage is applied from the latch circuit 7 to the gate of the field effect transistor 15 and applied to predetermined data terminals T, ~Tll, the fuse 14 connected to the data terminals T9 ~ Tl+ to which this voltage is applied is blown. .

One end of each fuse 14 is connected to the input end of the comparator 10 and connected to the power supply terminal T via a pull-up resistor 17. It is connected to the.

The counter 11 is operated by the correction pulse of the pulse generator 1 and outputs 8 ranks of correction comparison data to all the comparators 10. The minimum correction time width can be varied depending on the frequency of this correction clock pulse, and temperature correction and head element number correction are performed by varying this frequency.

This counter 11 is reset by the galley signal (ie, strobe signal) of the address counter 2.

The comparator 10 compares the correction data from the ROM 9 and the correction comparison data from the counter 11, and outputs an H signal to the AND circuit 12 when the correction comparison data is large.

The AND circuit I2 inputs the correction data from the comparator 10 and the basic drive data from the latch circuit 7, and outputs an H signal to the head element TI(-) only when both data are H signals.
1 to TH-240. Also, this AND circuit 12
is connected to an enable terminal T, and the operation timing is determined by an enable signal sent from this enable terminal T.

One end of each head element TH-] to Tl+-240 is connected to the AND circuit 12, and each head element TH-1 to TH
The other end of 240 is connected to the measurement terminal T.

FIG. 4 shows the mounted state of the thermal head I3. To briefly explain this, the head substrate 1 made of ceramic
240 head cords Tl+-1 to TH- at one end of 8
240 is burned in. This head element TH-1
- 240 AND circuits 1 in parallel in the column of T11-240
2. Latch circuit 7, comparator 10, ROM 9, etc.)・
'Circuit group A1 latch circuit group B1 shift register group C1 comparator group and ROM & control circuit group E are installed,
A correction counter 1 is installed near this ROM & control circuit group E.
1 is installed.

Further, a terminal group F is pattern-printed on the other end side of the head substrate 18, and this terminal group F is connected to each head element TH-1-
Measurement terminal T3 for measuring the current flowing through the TH-240, enable terminal T3 for sending an enable signal to the AND circuit 12, strobe terminal T3 for sending a strobe signal to the latch circuit 7, and shift register 6. A data terminal T5 is used to send a drive pulse. A shift clock terminal T5 is used to send a not clock to the shift register 6. A correction clock pulse and a reset carry signal (i.e., a strobe signal) are sent to the correction counter 11. Clock terminal T8 and reset terminal T7,
It consists of a power supply terminal T for ROM9 information, .

The operation of the above configuration will be explained below.

First, before the manufactured thermal head 13 is attached to a printer, R and OM 9 are written on the thermal head 13 alone.

Writing to ROM9 is performed using each head element TO-1 to TI (
-240 in turn, and convert the resistance value of each head element -'r-TI-"1 to TO-240 from the current flowing to the measurement terminal T1. From this resistance value, each head element TH-
1 to T11-240 are determined. -Head element T via latch circuit 7 using shift register 6
A voltage is applied to the gate of the field effect l transistor 15 corresponding to l1-1 to Tl-240, and a current is caused to flow from a predetermined data terminal T4 to the fuse 14 according to the correction rank to blow a predetermined fuse I4. . If the fuse 14 is blown, the I-1 signal will be stored, and if the fuse 14 is not blown, the L signal will be stored. This fuse 14 blowing operation is performed on all head elements TH-] to T11. -240
Writing is completed by writing to ROM 9 corresponding to .

Next, I will explain the operation of the thermal head drive circuit.
By reading data from the at-1 counter 2, the gradation data of each dot is sequentially sent from the line memory 3 to the comparator 5 from the I-th dot to the 240-th dot. The comparator 5 converts this gradation data into a reference gradation M (+gradation) from the gradation counter 4.
, and outputs basic drive data to the shift register 6 (for example, l, I, O, O, -1, O). The drive data for all of this horizontal 240 dot area is transferred to the shift register 6.
Once stored at a predetermined position, a strobe signal is input to the latch circuit 7, and the stored state is input to the AND circuit 12 of the correction circuit 8. Also, the comparator 5 moves to the second gradation comparison in response to the strobe signal, the next drive data is inputted to the shift register 6, and the recorded state is inputted to the AND circuit 12 in the same manner as above by the strobe signal. Ru. Therefore, the image data stored in the line memory 3 is
In the case of 1114, the P1 signal shown in FIG. 5(a) is output to the AND circuit 12.

On the other hand, the comparator 10 uses the correction data in the ROM 9 and the counter 1.
1 and outputs the corrected drive data to the AND circuit 12. Therefore, for example, if the correction data is 2
If it is a rank, a pulse signal as shown in FIG. 5(b) is output to the AND circuit 12.

The AND circuit 12 sends a drive pulse that is a combination of the basic drive data and the corrected drive data to the head element TH.
-1-TI-240, and in the example of two series, the fifth
Drive pulses as shown in Figure (c) are applied to the head element T11-
1 to T) l-7, 4 (Output to l. Drive) The pulse is increments for correction, eliminating unevenness in color density due to resistance value deviation.

In this embodiment, since the driving pulse is increments at predetermined intervals, the peak temperature due to heat generation is lowered and the lifespan of the head elements T)I-1, -TI(-240) is extended. have

[Effects of the Invention] As described above, according to the present invention, the head element and the shift register are provided in the thermal head, and the drive pulse is corrected in the section where the drive pulse is output from the shift register to the head element. , drive circuit power (without complication), and precise correction power (without using high-frequency shift clock pulses, etc.).

In addition, since the thermal head is equipped with a ROM and a data terminal for writing OM is installed on the thermal head, the thermal head can be corrected by itself before being installed on the printer. Moreover, according to the present invention, since the correction circuit can be built into the thermal head, the printer can be made smaller4, and design and manufacture can be made easier.

[Brief explanation of drawings]

1 to 5 show embodiments of the present invention, FIG. 1 is a block diagram of a thermal head drive circuit, FIG. 2 is a block diagram of the thermal head side of the thermal head drive circuit, and FIG. 3 is a fuse ROM. 4 is a mounting state diagram of the head board, and FIG. 5 is an output waveform diagram of each part of the thermal head drive circuit.
FIG. 6 is a block diagram of a conventional thermal head drive circuit. 6...Shift register, 13...Thermal head, TI (
-1-TI-240...Head element, T8~Tll・
・Data terminal.

Claims (1)

[Scope of Claims] A thermal head is provided with a plurality of head elements and a shift register for storing drive pulses for each of the head elements, and the head element is driven based on the drive pulses stored in the shift register. In the head drive circuit, the thermal head has an RO having a data terminal for writing.
A thermal head drive circuit characterized in that a ROM is provided with correction data corresponding to the resistance value of each of the head elements, and a drive pulse outputted from the shift register is corrected based on the correction data.