JPS62287778A - Signal transmitting method - Google Patents

Abstract

PURPOSE:To transmit various pieces of the descrambling information by using a digital signal train overlapped for a video signal period and transmitting the descrambling information. CONSTITUTION:During the special video signal period of a television signal, a digital signal train composed of a starting bit and an information bit continuous to it is overlapped and by the signal train, the descrambling information is transmitted. At the receiving side, after the received television signal is binarized by a binary circuit 1, the above-mentioned starting bit is detected by a starting bit detecting circuit 3. The second clock generating circuit 4 generates a sampling clock signal by the detecting information of the starting bit. A data reproducing circuit 2 reproduces a receiving data signal train and outputs it to a descrambling circuit based upon the above-mentioned sampling clock signal.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention Industrial Application Field The present invention is directed to direct satellite broadcasting, CATV, etc., particularly when a television signal is scrambled and transmitted, and the signal transmits the descrambled information. This relates to a transmission method.

2. Description of the Related Art Conventionally, descrambling information has been transmitted by AM modulating the audio carrier wave of a television signal. A signal reproducing circuit in this case is shown in FIG. In the figure, 101 is the audio IF
105 is a limiter, and 102 is an FM detection circuit. 103 is an AM detection circuit, 110 is a comparator, and 111 is a reference voltage source, which constitutes a descrambled information signal reproducing circuit 104. Television audio signals are transmitted by FM modulating audio carrier waves. Therefore, after the received audio IF signal is amplified by the audio IF amplification circuit 101 and passed through the limiter 105, the FM detection circuit 102
to perform FM detection and obtain audio. On the other hand, the descrambling information signal transmitted by AM modulating the audio carrier signal is obtained by converting the output of the audio IF amplification circuit 101 into an AM detection circuit 103.
After M detection, the reference voltage source 111 is detected by the comparator 110.
It is disulfide and regenerated compared to.

However, the band that can be occupied by the modulated audio carrier wave is narrow, and so much descrambling information cannot be transmitted. At most, it will only be the descrambling timing. There are multiple descrambling methods, and if you try to transmit their selection information, you will need to use other information means. Other information means include data transmission channels using a frequency band different from that of television signals, telephone lines, and the like.

Problems to be Solved by the Invention In such a conventional configuration, fine descrambling control is difficult. This is because the above-mentioned data transmission means is also used for transmitting other information (for example, setting the terminal's channel selection permission, etc.), so it is not possible to allocate much time to transmitting descrambled information. . Therefore,
Even if there are multiple receiving channels that require descrambling, the same descrambling method is used for all, or
The time interval at which the descrambling method is changed is on a weekly or monthly basis, making it difficult to perform detailed operations such as changing it for each program or channel.

Means for Solving the Problems In order to solve the above problems, the present invention superimposes a digital signal string having a start bit indicating the beginning of the data signal at the beginning of a specific video signal period of a television signal. At the same time as the transmission, the receiver includes a television signal binarization circuit, a start bit detection circuit, a first clock generation circuit, a second clock generation circuit, and a data reproduction circuit, and the receiver The start bit detection circuit detects a start bit from the output of the conversion circuit, and based on that information, the second clock generation circuit generates a sampling clock from the output of the first clock generation circuit, and based on that, the data reproduction circuit generates a sampling clock. The digital signal train is reproduced by the digital signal train.

Function The present invention provides a start bit at the beginning of a digital signal train, and after detecting the start bit in a receiver, the output of a first clock generation circuit is divided by a second clock generation circuit to generate the digital signal. When reproducing the digital signal, a sampling clock is generated at a timing with the most sampling shift margin, that is, a shift point of the digital signal and a sampling clock located in the center of the shift point, and the digital signal is reproduced.

Embodiment An embodiment of the signal transmission method of the present invention will be described below with reference to the drawings.

FIG. 1 is a waveform diagram showing signals of the signal transmission system of the present invention. A case is shown in which a digital signal string having a start bit at the beginning is superimposed on a video signal period of a specific horizontal period. When superimposing digital signal 1 as white signal and O as black signal, conversely, when superimposing digital signal 1 as black signal and O as black signal,
may be superimposed as a white signal. If the former is a positive logic superimposition method and the latter is a negative logic superimposition method, the start bit is 1 for positive logic superposition, and the start bit is O for negative logic superposition. On the signals superimposed together, the start bit becomes a white signal. Further, since it is necessary that the position at which the digital signal is superimposed has no influence on the image signal to be transmitted, it is preferable to set it at the vertical retrace period. The level to be superimposed as a white signal may be 100% white level or lower, and a 50% to 70% white level is preferable from the viewpoint of stability against noise and the like as a system.

FIG. 3 is a circuit configuration diagram showing a first embodiment of a signal reproducing circuit for reproducing a digital signal train sent by the signal transmission system of the present invention. In the figure, 1 is a binarization circuit, 2 is a data reproducing circuit, 3 is a start bit detection circuit, 4 is a second clock generation circuit, and 5 is a first clock generation circuit. The received and detected television signal is binarized by a binarization circuit l. From its output, start bit detection circuit 3
Detects the start bit at the beginning of the digital signal string. When the start bit is detected, the second clock generation circuit 4 generates a sampling clock having a lower frequency than the sampling clock output from the first clock generation circuit 5. This sampling clock indicates the sampling position with the best conditions for reproducing the transmitted digital signal string, and is generated by frequency-dividing the first clock. The data reproducing circuit 2 reproduces the received digital signal string using the output of the binarizing circuit 1 and the sampling clock generated by the second clock generating circuit 4.

Here, the start bit detection circuit 3 is initialized in advance with a horizontal synchronizing signal or an alternative thereof. If a digital signal string is superimposed with the positive logic, the first signal detected as 1 after the initialization is set as the start bit.

FIG. 3 is a circuit configuration diagram showing a second embodiment of a signal reproducing circuit for reproducing a digital signal train sent by the signal transmission system of the present invention. In the figure, 11 is a voltage comparator;
Reference numeral 12 denotes a reference voltage source, and the above constitutes a binarization circuit of 1. 21 is a D-FF, which constitutes the second data reproducing circuit. 31 is an inverter, 32 and 33 are ORs of negative logic inputs, and the above constitutes three start bit detection circuits. Further, 34 is an RS launch circuit composed of 0Rs 32 and 33.

Reference numeral 41 is a shift register, 42 is a frequency divider, and 43 is an inverter, thus configuring 4 second clock generation circuits. 5 is a first clock generation circuit.

Here, circuits with the same numbers as in FIG. 2 have the same functions as those in FIG.

FIG. 4 is a signal timing diagram for explaining the operation of FIG. 3. In the figure, fa) is the output of the binarization circuit 1, (b) is the output of the first clock generation circuit 5, (e) is the output of the start bit detection circuit 3, and (d) is the output of the shift register 41. , (e) is the output of the second clock generation circuit 4, and (f) is the output of the data reproduction circuit 2.

The operation of the second embodiment of the present invention will be described below with reference to FIGS. 3 and 4. The received and demodulated television signal is compared with the output voltage of the reference voltage source 12 by the voltage comparator 11 and binarized (Fig. 4(a)).
). The polarity of this output is inverted by an inverter 31, and the RS launch circuit 3 is composed of negative logic inputs 0R32 and 33.
Enter 4. The RS latch circuit 34 is reset in advance by a negative horizontal synchronizing signal or a signal replacing it. The RS latch circuit 34 is set at the leading edge of the start bit output from the binarization circuit 1 (Fig. 4 (C
)).

On the other hand, the first clock generation circuit 5 outputs a first clock having a frequency eight times higher than the transmission frequency of the transmitted digital signal string (FIG. 4(b)). The output of the start bit detection circuit 3 is sent to the first bit in the shift register 41.
(FIG. 4(d)),
Enter the clear input of the frequency divider 42. In the frequency divider 42, after the clear input becomes high level, that is, four clocks after the start bit is detected,
Start frequency division of the first clock. Frequency divider 42 is 1/4
A frequency divider, the polarity of which is inverted by an inverter 43,
Output as a sampling clock (Figure 4 (el)
).

The D-FF 21 takes in the output of the binarization circuit 1 at the rising edge of the sampling clock and outputs it as a data signal (FIG. 4 ()).

Assuming IMHz as the transmission frequency of the data signal to be transmitted, approximately 50 bits of digital signal including the start bit can be superimposed within the approximately 50 μsec video signal period shown in FIG. Even if it is superimposed only on a specific period of 1 vertical period, it is possible to transmit a digital signal of about 3000 bits per second. At this time, the first clock generation circuit 5 outputs a first clock of 8 MHz. Further, the occupied frequency band of a digital signal train with a transmission frequency of IMHz may be from 15 ktlz to about 500 Hz, and is not susceptible to deterioration in the television signal transmission path.

As described above, by providing a start bit at the beginning of the digital signal string as shown in Fig. 1 and transmitting it while superimposing it on the video signal period of a specific horizontal period, the data as shown in Figs. 2 and 3 can be transmitted. The signal train can be reproduced with an hour wheel circuit configuration.

Effects of the Invention As described above, according to the present invention, the digital signal string is superimposed in a simple signal format in which a start bit is provided at the beginning of the digital signal string to be transmitted during the video signal period of a specific horizontal period. By doing so, the receiver can also reproduce the digital signal string with a simple circuit that detects the start bit and generates the sampling clock. Furthermore, the amount of information that can be transmitted is necessary and sufficient for descrambling information such as video signals in satellite broadcasting and CATV, and it becomes possible to select and switch descrambling methods for each channel and each program. Therefore, it becomes possible to construct a scrambling and descrambling system with higher confidentiality.

[Brief Description of the Drawings] Fig. 1 is a waveform diagram showing the transmission signal format of the present invention, Fig. 2 is a circuit configuration diagram showing the first embodiment of the present invention, and Fig. 3 is a waveform diagram showing the transmission signal format of the present invention. FIG. 4 is a circuit configuration diagram showing the embodiment, and FIG. 4 is a signal timing diagram explaining the operation of the second embodiment of the present invention.
The figure is a circuit configuration diagram showing a conventional example. 1...Binarization circuit, 2...Data reproduction circuit, 3...Start bit detection circuit, 4...
...Second clock generation circuit, 5...First
clock generation circuit, 11... voltage comparator, 12... reference voltage source, 13゜43...
...Inverter, 21...o-FF, 32.3
3...Negative input 0R534...RS latch, 41...Shift register, 42...
・Frequency divider. Name of agent: Patent attorney Toshio Nakao 1 person Figure 1 Section 2 Section 1-2 @ conversion circuit 2 --- data reproducing circuit 3 --- ZDART bit comparison 8 circuit 4 --- 1 second clock Generation circuit 5-1 clock ordering circuit 34-RS latch circuit Fig. 3

Claims (3)

[Claims] (1) A signal transmission method characterized in that a digital signal sequence having a start bit indicating the beginning of a data signal is superimposed and transmitted at the beginning of a specific video signal period of a television signal. (2) The signal regeneration circuit of the receiver includes a television signal binarization circuit, a start bit detection circuit, a first clock generation circuit, a second clock generation circuit, and a data reproduction circuit, The start bit detection circuit detects a start bit from the output of the binarization circuit, and based on that information, the second clock generation circuit generates a sampling clock from the output of the first clock generation circuit. 2. The signal transmission method according to claim 1, wherein the data signal string is regenerated by a data reproducing circuit. (3) The signal transmission method according to claim 1 or 2, wherein the digital signal string to be transmitted is descrambling information of a television signal.