CA1248625A - Key signal transmitting method for scrambling a tv picture - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE A TV signal scrambling method employs level compression of selected horizontal flyback sections to prevent synchronization at the receiver. Key signals are transmitted along with the TV signal to be used in descrambling the picture, and are generally superposed on the horizontal synchronizing signal portion. The key signal is encoded before transmission so as to prevent unauthorized tapping which might otherwise occur if the key signal was separated and analyzed.

Description

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1 BACKGROUND OF ~HE INVENTION
. . _ The present invention relates to a method of scrambling TV pictures in TV broadcasting, including both wireless and wired (cable) broadcasts, in which the TV picture is scrambled so as to become unviewable in the state received by a receiver unless the scrambled image is aorrected into the original picture by a specific method. More particularly 7 the invention i5 concerned with a method of transmitting a key signal for de-scrambling, wherein~ when the key signal is transmitted for the de-scram-bling, the key signal is processed by code conversion to avoid any tapping (i.e. unauthoxized reception of the original signal.
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BRIEF DESCRIPTION OF THE DRAWINGS-....
- Fig. 1 is a schematic illustration o a conventional CATV system, Fig. 2 is a waveform chart showing the principles of the scrambling method in accordance with khe invention;
Fig. 3 is a waveform chart of a horizontal synchronizing signal to which a key signal for de-sarambling has been added;
Fig. 4 is an enlarged waveform chart oE the horizontal synchronizing signal shown in Fig. 3, Fig. 5 is an illustration of the state of des-truction o~ the picture in accordance with -the invention;
Fig. 6 is an illustration of the section of destruction of the pickure;

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l Fig. 7 is a schematic illustration of the appli-cation o an embodiment o the invention to A CAI'V system;
Fig. 8 is a block diagram o an encoder incor-porated in the embodiment of the invention;
Fiy. 9 is a block diagram of the internal structure of a main box;
Fig. 10 is a block diagram o~ the decoder;
Fig. 11 is an illustration of a random number for scrambling and the state of processing of the same;
Fig. 12 is a timing chart showing the change in the signals in parts o the encoder and the picture signal in l (one) field;
- Fig. 13 is a timing chart showing the changes of signals in parts of the encoder in the interval bet-ween horizontal synchronizing signals, as well as the state in which a key signal has been added;
FigO 14 is a timing chart showing the changes of signals in parts of an encoder and the pic-ture signal ater level compression;
Fig. 15 is a kiming chart showing the changes of signals in parts of the decoder in l (one) field;
Fig. 16 is a timiny chart showing the changes of signals in parts of the decoder in a period inter mediate between horizontal synchronizing signals, as well as the picture signal after de-scrambling;

s 1 Fig. 17 is a waveform chart showing the picture signal as actually modulated by a carrier wave, showing the relationship between level compression and the level expansion; and Fig~ 18 is a waveform chart of the picture signal as actually modulated by a carrier wave, showing the relationship between the addition and removal of the data signal.
In a conventional TV broadcasting services, ~10 either by wireless or cable,programs can be watched on normal, standard TV sets, within respective areas covered by service networks, by reproducing TV
pictures as received. However, it is necessary to make it possible to view TV programs only on TV
:15 sets owned by specific subscribexs, but not by others with respect to paid TV broadcasting services.
Particularly, in CATV broadcasting services capable of . providing various programs, the operation of such CATV

Jt z stations is dependent on the fees paid for programs, so that the segre~ation of subscribers is essential. For that reason, transmitters of programs require a scrambling method which manipulates the pictures transmitted so that the~ cannot be reproduced as normal pictures if received as they are.
Firstly, a ~ATV system will be outlined hereullder with reference to Fig. l.
This system has a unique chargeable pragram broadcasting function.
Fig. 1 shows -the entire CATV system. This system comprises a center 1 and thousands and thousands of ~erminal equipment units 28 connected therewith by means of coaxial cables. From the center 1 is laid a trunk line cable 3 on which are installed at predetermined points a trunk line amplifier 4 and a branch box, respectively. From this branch box 5 are drawn a plurality of branch cables 6, and each branch cable 6 is provided at predetermined points with a branch amplifier 7 and a tapoff 8, respectively. From each tapoff 8 are dra~na plurality of sub-branch cables 9; each termi.nal thereof is drawn in-to a household 2. The terminal equipment 28 in each household 2 comprises a main box lO, a TV set 11 and a control box 12. The terminal of a sub-branch cable 9 is connected to the main box 10, the TV set ll and the con-trol box 12. That is, the center 1 and every terminal unit 28 in subdivisioned households are intercon~

nected in a Christmas -tree manner.
Outside the aforementioned center 1 is erected a receiving antenna 13, and this is connected to a demodulator in a source group 1~. In this source group are a video-disc player 16, video-tape recorder 17, studio 18 and so Eorth.
A modulation transmi-ttiny part 19 that receives signals Erom the source group 14 comprises two systems: one consists of an IF modulator circuit 20, a scrambling circuit 21 and an up converter circuit 22; and the other, an IF modulator circuit 23 and an up converter circuit 24. Respecti~e out--puts from the up converter circuits 22 and 24 are connec-ted to the trun~ line cable 3. The trunk line cable 3 is also connected to a data transmitter/receiver set 25 that communic-ates with each main box 10. To the data transmitter/~eceiver set 25 is connected a computer 26 to which is connected peripheral equipment 27 including a printer, display, etc.
The opera-tion of this CATU system will now be described. Turning ON the TV set 11 and operating the control box 12 to select a desired channel enables pictures to be supplied to the TV set 11 through conversion, by means of the main box 10, of a frequency for said channel into that for an idle channel. Type of channels selectabLe by means of the control box 12 comprise:
(A) retransmissions for receiving programs as they are;

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(B) self-sustained programs (free of charge); and (c) chargeable programs.
Each group has several channels, respectively, thus making a total of some 20 - 30 or more selections available.
(A) Retransmission:
Electromagnetic waves received by the receiving antenna 13 are demodulated by means of the demodula-~.or 15 and delivered to the modulation transmitting section 19~
The signal is thenmodulated in the IF modulator circuit 23 and the modulated signal is raised to a specific f~equency in the up converter circuit ~4. This signal, having been modulated and positioned to a specific channel, is transmit-ted by way of the trunk line cable 3, branch cables 6 and ..he sub-branch cables 9 to the households 2 and is received by the TV sets 11 through the medium of the termina1 equip-men-t 28.
(B) Self-sustained Program:
These programs inc].ude wea-ther Eorecasts, news-wires, stock quota-tions and the like. Recorded programs regenerated by the video-disc player 16 or the video-tape recoxder 17 and live programs produced i.n the studio 18 are transmitted to the trunk line cable 3 upon being ~odulated and subsequently converted into a frequency for a specific channel in the IF modulator circuit 13 and the up converter 24, respectively. These programs are Eree or charge regard--16;~5 '1 ,~

less or the number of times of reception or hours thereof, and each household may receive these programs upon monthly payment of a base fee.
(C) Chargeable Programs:
These programs include ne~ly produced motion pictures and other specific programs. Recorded programs~e regenerated on the video-disc player 16 or the video---tape recorder 17, and live programs produced in the studio 1.8 are modulated in the IF modulator circuit 20, follo~ed by addin~ to the video signal a specific synchronizing signal in the scrambling circuit 21, to manipulate the picture signals so that they will not appear as normal pictures upon reception of the same as they are. The frequency of the signal is then raised in the up converter circuit 22 to that for a specific channel and the signal is then sent to the trunk line cable 3. Each household 2 desiring to watch -this chargeable program may be able to do so by demodulating the received signals into normal video signals in the main box 10. For reception or chargeabla programs, the fees are calculated on a pre-established basis and are added to the monthly base fee on a bill..
I'he aforementioned center 1 and the terminal equipment 28 of every household 2 are connected by means of coa~ial cables, but unless the reception of pictures on certain channals by households 2, is periodicaLly verified, ' ;
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the fair operation of a CATV system cannot be expected because, ir. not, discrimina-tion between chargeable and Lree of charye accounts based on programs received is not feasible.
For this purpose the data transmitter/receiver set 25 is provided to determine the signals being received during a retrieval time (so-called polling) by transmitting a ret.r.ieval signal at a certain time interval, calling main boxes 10 in every terminal unit 28 using a unique address number ~ssi.g.~ed to each main box 10. Each main box 10, in response to the polling signal, gene~ates an answer as to the channel through which pictures are being received, and transmits it bac~ to the data transmitter/receiver set 25. The data received by the data transmitter/receiver set 25 are put through da.ta processing by the computer 25 and are displayed on or printed out by the peripheral equipment 27. ~olling is carried out at a certain time interval (several-tens of second thus making i-t possible to sum ratings, etc. at once. Some programs invite participation by the audience; in which the audience maY be able to answer, while watching on the TV sets 11, the question asked in the proyram by operating the control oox 12. The answers (data) are sent to the center 1 through the coaxial cables.
For certain prograrns in conven-tionaL TV broadcast-ing, video signals transmitted Erom the center 1 are scrambL-ed (privacy transfer). In order to receive these scrambledpictures as normal, a descrambling process is required at g l each terminal unit 28 to demodulate the same into regular picture signals. If the scrambling process is primitive and very easily de-scrambled, wiretapping may not be prevented. A high level scrambling method for preventing ready wiretapping has been in demand for the operation of TV signal transfer systems.
Hitherto, in scrambling broadcasts, a method called the "gray sync method" has been popularly used in which the modulation level of the horizontal synchronizing signal is changed in the RF stage of the transmitting side. In this method, a sine-wave encoding signal of a phase which is inverted from the modulation phase is transmitted together with the modulated picture signal.
At the receiving side, the scrambled picture signal is demodulated in accordance with this encoding signal to effect de-scrambling. This method, however, imposes the following problems:
(l) Noise or distortion is liable to occur in the de-scrambling side because o~ the use of analog type processing.
(2) The scrambling and de-scrambling processes are too simple to perfectly prevent tapping.
To obviate these problems, a method has been proposed by the present inventors in U.S. Patent ~,~22,745 issued on March 30, 1982 in which the modulation level of a specific hor.izontal synchronizing signal is changed by a digital technique ,3 ~; ~

lo 6~5 to thereby effect scrambling.
More specifically, in this proposed method, only the horizontal flyback sections of the picture signal are level-compressed to preven-t synchroniza-tion of the image. In de-modulation, only the horizontal flybac]c.
sections are level-expanded in a stepped mannerO 'rhe horizontal flyback sections in which level compressi.on and expansion are effected can be selected -freely ancl are changed periodically i.n accordance with a false randolr 1~ number, to thereby make it impossible to attain s~rl~hro:rliza~
tion. In this case also, in order -to permit the recei.viny slde to effect de-scrambling, a key signal (digital code) is transmitted at the same frequency as the carrier frequency, and the scrambled picture signal is de-modulated : 15 by -this key signal. For persons who wish to tap the TV
picture, however, it is quite easy to de-scramble the pic-ture assuming knowledge of the manner of sending the key siynal. In addition, if such persons have suitable peripheral equipment, they can effect de-scrambling in all systems employing the same scrambling method. That is, peripheral equipment used for de-scrambling in one district can also be used for de-scrambling in other districts. rrhus~ it is possible to enjoy the TV broadcasts of different broadcasting companies using -the peripheral equipment for any one of -these companies, provided that 8~;~5 .

these companies make use of the same scrambliny method.
Thus, the conven-tional scrambling method could not complete-ly prevent the tapping of TV broadcasting.
SUMMARY OF THE INVE~TION
Under these circumstances, the present invention seeks to provide a key signal transmitting method for -the scrambling of a TV picture, capable of eliminating the opportunity of tapping and reducing the interchangeability of systems to thereby prevent the tapping of TV broadcas-~sO
According to the invention, these is provided a method in which the picture-signal is scrambled by a predetermined method and, at the same time, the code of the key signal is converted by a predetermined code conver-sion method, the key signal after code conversion being transmitted together with the scrambled picture signal, so that the key for de-scrambling cannot be obtained solely by the separation and analysis of the key signal.

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DETAILED DESCRIPTION OF THE P~EFERRED E~BODIMENT~
Fig. 2 shows the waveform of the video signal ~or the scrambling method according to the present invention, wherein the video signal is modulated by a carrier. In this video signal are positioned a horizontal synchronizing signal at a 100% level oE percentage modulation in relation to the ?eak carrier; a video signal of the deepest black at about a 70% modulation level; and a video signal of the most whi-te at about a 12.5% level. Consequently, this indicates that with color shades for black and white in a picture being .~M modulated in the range of 12.5 - 70~, only the horizontal synchronizing signal takes a position a-t the largest amplitude of 100%, and is possible to use it for timing synchronization of the scanning lines, upon separating the horlzontal synchronizing signal. A waveform indicated by solid line A in the video signal shown in Fig. 2 represents the condition before being scrambled; the waveform in broken lines B', the condition after being compressed by the level compression involved in the scrambling, where only the horizontal flybacX line section varies toward the direction of the white level, having a lower percentage modulation, while other video slgnalportions remain unchanged with respect to percentage modula-tion, indicating that only the horizontal flybacX line section has been compressed upon level compression. In the horizontal ElybacX line section are a horizontal synchronizing signal C modulated to 100%, ;, .

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and at a shoulder portion having a slightly lower percentage modulation than that for the horizontal synchronizing signal C is added a color burst signal D.
Fig. 3 shows the waveform of a signal obtained by adding, to a picture signal, a de-scrambling key signal in accordance with the scrambling method of the invention.
It will be seen that key signals E in the form of a digital code are added to the horizontal portion of the horizontal synchronizing signal C of the picture_signal. More specifically, the key signals E are added to the horizontal synchronizing signals of a plurality of lines following vertical flyback sections. These portions do not normally appear on the TV screen, so it is not necessary to effect level compression of horizontal flyback sections added to the key s~gnals.
Fig. 4 shows an enlarged horizontal flyback line section of Fig. 3, with the data signal E, being a digital code of 6 bits, added to the flat section on top of the horizontal synchronizing signal C. This data signal E defines the first bit in the si~ as the s-tart bit; the bits from the second to the fifth, the da-ta bits; and the 6th bit, the parity bit. The start bit here indica-tes -the beginniny of data, and the parity bit is used for checkirlg a bit error in the data. '~hese data bits indicate the condition of scrambling currently under ~,Jay, and wlll aJ.so be used as keys when descrambling will take place.
Reception b~ the TV sets 11 of scrambled video signals as transmitted ~,~ith level compression performed on these hori~ontal line sections prevents the synchronizing sepaxator circuits in the T~' sets 11 from separating horizontal synchronizins signals ~, thus failing to synchroni7e the reproduced pictures, resulting consequently in garbled pictures. Upon descrambling, on the other hand, only the horizontal retrace line sections processed through level compression are brought back to the original level of the video signals, so -that the synchronizing signals can be separated, resulting in pictures normall~ demodula-ted.
Because no treatment ~as performed on the picture signal portions of the video signals treated in the scrambling process, no noise or distortion takes place in the reproduc-ed pictures through demodulation, ~aking possible the -- 1s ~ 2~j reception or pictures of as hiyh ~uality as those of ordinary TV programs not processed through scrambling and descra~ling.
The destruction caused to the transmitted pictures is explained hereunder with reference to Fig. 5.
Fig. 5(a) shows schema-tically a normal picture before the scrambling process; Fig. 5(b) shows an exampLe o~
pictures reproduced by a TV set 11 upon reception of ~ideo signals processed through scrambling, as received. In the scrambling method of an embodiment according to the present invention a picture frame is vertically divided into eight sections (not equally in this embodiment), and each section is reproduced in a manner re~lecting whether the horizontal flyback line section (the portion C in Fig. 3) was ~ubjected to lev;el compression, so that horizontal syncnronizing signals C in some sections are subjected to level compression but others are not. As a consequence, portions with the horizontal ~ly~acX line sections subjected to level compres-sion and those which have not coexist within one picture.
Those portions with the horizontal rlyback retrace line section having been subjected to level compression are not svnchronized, so tha-t portions of the picture flow in a la-teral direction, making the picture unrecognizable as a whole. Whether or not the provision of level compression of the horizon-tal flybacX line section is eIfected in each section from I to VIII, respectively, in a picture frame -16~

divided into eight parts is determined by random number information, so the decision is not always the same. The random num~ers that determine those horizontal retrace li.ne sections to be subjected to l.evel compression are periodical-ly (at very short intervals) changed, so that no scrambli.ng setting in an identical condition takes place continuo~lsl.y.
Consequently, the scrarnbling process causes pictures in a given section to be continuously unstable on the ~FV sc::reeLl, and pictures reprocluced ~ithout descrambling are as indica-~.ed ~y the bro~en lines ~n Fig. 5(b), flowing in a disturbed picture changing upon switching of the random numbersl causiIly the picture to move continuously. Therefore, ~he pic-tures, even if still origi.nally, keep varying violen-tly on the Ttl screen, disturbed to the extent so as to be unwatchable as they are, if reprocLuced in the scrambled condition. Informa-tion as to the hori.zontal ret~ace line sections haviny been subjected to level compression in sections I - VIII is trans~
mitted to the termi.nal equipment 28 by means of the data bit shown in Fig. 4, and the reading out of this data bit enables the decoder to initiate descrambling.
Dividing a picture frame into eight sections is merely an example and the division may be freely set to any proper value, for example, four or sixteen.
Fig. 6 schematically shows the relationshi.p hetween the video signals and the screen of a TV receiver some of the scanning lines produced by the video signals do not appear on the receiver, and these are represented by a dozen or so horizontal scanning lines hidden above the screen and forming a vertical flyback (blanking) line section, those horlzontal scanning lines before the horizontal flyback and behind thereof, and line sections of respective scanning lines hidden beyond the left hand side of the TV screen. To some horizontal synchronizing signals C immediately after the vertical flyback line sec-tion in the video signals are added the aforementioned key signals E. To the vertical flyback line sections and the parts to which the key signals is added, no level compres-sion for scrambling is provided. Thus these signals are constructed so that the horizontal synchronizing signals C
may be easily separated together with the key signals E
at the decoder in order to make it possible to readily recognize the descrambling key signals ~ontained in the horizontal synchronizing signals. Other picture portions excepting the part with added vertical flyback line sec~:ions and key signals, as aforementioned, are divided into eight sections, and each of them is determined by a random nu~ber whether to be subjected to level compression between horizontal flyback line sections or be left as it is. The key signals E added to the horizont--18~ 8~

al synchronizing s:ignals C in several scanning l.ines containing vldeo information and immediately after the aroremen-tioned ver_ical fl~back line section discriminate those portions that have been provided -~ith "gra~ sync"
depending on the level, for example, with "0" and "l"
meaning "~ithout level compression" and "with level compres--sion", respectively, and provide expansion with the ~oriY.ont-al flyback line section in the portion corresponding i.o the signal "l" to enab:Le the TV set to separate the hori~o~.tal synchronizing signal C. Providing these scrambling processes in sequence with respective fields demodu1ates a picture in a normal state.

Now, a exemplitive embodiment according to the present invention will be explained hereunder with respec~
to Fig. 7 et. seq.
Fig. 7 shows an exemplary embodiment of the scrambling system according to the present invention as applied to a CATV system, wherein the identifical components to those in Fig. l have identical reference numbers for the purpose or avoiding duplication in description.
Between an IF modulator circuit 20 and an up con-verter circui-t 22 .is provided an encoder 30 or scrambling.
Between a sub-branc:h cable 9 and a TV set ll are provided a main box 31 with a built-in decoder, and to this main box 31 is connec-ted -the con-trol box 12.

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Fig. 8 shows the internal structure of the encoder 30. The IF signal is inputted through a brancher 42 and is outpu-t through a coupler 43 and a switching amplifier circuit 44. The brancher 42 has two bxanching terminals to which connected are a limi-ter circuit 45 and a picture detection circuit 46. To the limiter circuit 45 is connected a mixing circuit 47, the output of which is inputted to a phase.comparator circui-t 48 including a low~
pass filter. The output of the phase comparator circuit 4 is connected to a VCO 49 whose end is connected to one of the input terminals of a mixing circuit 57. The mi~lng circuit 47, phase comparator circuit 48 and VCO 49 in combination constitute a PLL. The output of the VCO 49 is delivered to the coupler 43 through a gate circuit 50 (switching circuit) and a band-pass filter 51. The output of -the picture signal detection circui-t 46 is input to a horizontal synchronization separation circuit 52 adapted to separate the horizon-tal synchronizing signa]
fr.om the p.icture signal, and also to a vertical synchroniza-tion separation circuit 53 adapted to separate the verticalsynchronizing signal from -the same.
The output of the horizon-tal synch separation circuit 52 is connected to one of the input terminals of a phase comparator circui-t incorporating a low-pass filter.
The output of the phase comparator circuit 54 is inputted -20~

to a ~CO 55, the output of which is delivered successively to a quadri-demultiplier 56 and a 1/160 demultiplier 57.
The output from -the 1~160 demultiplier is delivered to both a line counter 58 and the other input terminal o~ the phase comparator circuit 54.
The output of -the vertical synch separation cix-cuit 53 is inputted to a line counter circuit 58 and a random number generating circuit 59, which successively produces false random numbers. Reference numeral 60 designates a timing generation circui-t adapted to produce timing signals for controlling the operations of every part of the encoder 30. The timing generation circuit 60 receives the counter output 61 from the 1/160 demultiplier 57, which is composed of a plurality of flip-flops, each of which can produce an outpuk, as well as the counter output 62 from the line counter circuit 58.
The random number output 63 from the random number generating circuit 59 is connected to a memory processing circuit 64 and a code conversion circuit 65.
The data output 66 from the memory processing circuit 64 is connected to a shift register 67. The code conversion circuit 65 is composed of, for example, an ROM (Read Only Memory) and is adap-ted to eect conversion of a digital code in accordance with a predetermined procedure. The conversion output 68 from this con~ersion circui-t 65 is -21- ~ 2~

dellvered to a memory circuit 69. The timing outputs 70 and 71 from ~he timing generation circui-t ~0 are connected -to the memory processing circuit 64 and the memory circuit 69, while the output b from the timing genera-tion circuit 60 is i.nputted to -the shift register circuit 67. On the other hand, an AND gate clrcuit 72 receives the outputs c and d from the timing generation circuit 60, as well as the output from the shift register 67. The output from the AND gate circuit 72 is received as the control signal for the gate circuit 50. The outputs a and g of the -~imi.ng yeneration circuit 60 and the output f from the memory circuit 69 are received by an AND gate circuit 73, the output of which is inputted as a control signal into a switching amplifier circuit 4~.

Fig. 9 shows the interior of aforementioned main box 31 in Fig. 7, wherein the sub-branch cable 9 connects inside the main box 31, to a converter 80 for frequency conversion, outputs from the co.nverter 80 are defined -to be for a specific channel (for example, channel 2), outputs from -this convert:er 80 connect to the decoder 81 functioning for descrambling, and the decoder 81 is connected to the TV set 11 shown i.n Fig. 7. The control box 12 for selecting a channel for receiving pictures therethrough connects, inside the main box 31, to a control logic ~lnit 82, and signals for selection of channels from the control logic unit 82 connect to the arorementioned converter 80.
Fig. 10 shows the details of the internal structure of the decoder 81 shown in Fig. 9. The picture signal including an audio signal from the converter 80 is delivered to a TV receiver 11 through a brancher 85, a switching amplifier circuit 86 which can vary the amp]ific-ation factor in two stages and a trap circuit 87 The signal 'oranched by the brancher 85 is received by a detection circuit 88, the output of whlch is delivered to a data demodulation circuit 89, a horizontal synch separation circuit 90 and a vertical synch separation circuit 91. The processed output 94 from a memory processing circuit 93 is inputted to a code conversion circuit 95.
The code conversion circuit 95 can convert the digital code into the original key signal by a procedure reverse to that performed by the code conversion circuit 65. The code conversion circuit 95 and -the shif-t register circuit 97 are connected to each other through a key signal output 96.
The outputs from -the horizontal synch separation circuit 90 and the ver-tical synch separation circuit 91 are delivered, respecitvely, to a counter circuit 98 and a line counter circuit 99 as reset signals. Re~erence numeral 100 designates an oscillation circuit making use of a quartz oscillator and adapted to output a stable -23~

frequency which i.s 160 times ~s high as that of the horizontal synchronizing frequenc~v. The output of this oscillation circ~i-t lO0 is delivered -to -the counter circuit 98 which periodicall~ delivers a coun-t output P to the line counter circuit 99. Numeral 101 designates a timing generation circuit adapted to produce and output timing signals for controlling every part of the deeoder 91~
The timing generation clrcuit lOl receives the countex outputs 102 and 103 from the counter circuit 98 and i:he line counter circuit 99. The timing output 104 from the timing generation circuit 101 is delivered to -the memory processing circuit 93. A signal n from the timing generation circuit lOl is delivered to the shift register circuit 97. The output _ from the shift register circuit 97 and signals i and 1 from the timing generation circuit lOl are received by an AND gate circuit 105. An output n from the AND gate 105 is received by -the switching amplifier circuit 86. A signal k from the timing generation circuit 101 is delivered -to the -trap circuit 87.
The operatlon of the clescribed embodiment is as follows.
Firstly, the exemplary embodiment is outlined in rela-tion with Fig. 7. Video signals from -the IF
modulator circuit 20 entering the encoder 30 are so process-ed therein -that i-t will not be possible to reproduce 6;~i normal pictures from them as received, and the signals are modulated by the up converter 20 -to a frequency for a certain channel. At the terminal unit, the decoder 81 in the main box 31 demodulates and converts the codes of the key signals for clescrambling delivered together wi.th the video signalsfrom the center l, to resto.re the normal key signal, and descrambles the scrambled video signa:l.s in accordance wit:h the key signals to demodulake them into normal video signals.

The encoder 30 takes -two actions: one is to provide speciEic horizontal synchronizing signals wi-th level compression; and the other is to provide specific horizontal synchronizing signals with added key si.gnals for descramb~ing.

Referring to Fig. 8, the picture signal (IF input) delivered by the IF modulator circuit 20 is delivered through the brancher 42 and the coupler 43 to the switching amplifier circuit 44 in which it is amplified using one of two amplification factors. Amplifica-tion is effected with the greater amplification factor unless a control signal from -the timing generation circuit 60 is received. The thus amplified signal is delivered to the up convertor 22 as a scrambled picture signal (IF output). A par.t of the picture signal branched in the ~rancher 42 is sent -to the limiter circuit 45 in which the ampli-tude of this signal s is limited to eli.minate -the AM modulation component, so tha-t only the picture carrier wave is delivered to the mixing circuit 47 so as to be mixed with the output of the VCO 49 The mixed output is delivered to -the phase comparator circuit 48 to stabilize the oscilIation frequency of the VCo 49. I-t is recalled tha-t -the mixing circuit 47, phase comparator circui.t 48 and the VCO in combination constitu'ce a PLL circuit. The oscillation wave of the output from the VCO 49 has a frequency somewhat lower than the frequency of the pictuxe carrier wave of the llmiter 45. Namely, the frequency o~ the carrier wave is about 45.75 L~HZ while the frequency of the oscillation wave is about 45.75 - 2.5 MHz. The mixing circuit 47 outputs the difference of both input frequencies as a beat frequency of about 2.5 MHz.

This beat frequency is delivered to the phase comparator circuit 48. The phase comparator circuit 48 receives a reference output from the quadri-demultiplier 56, the reference output being of a frequency of about 2.5 MHz, which is 160 times as high as the hori~on-tal synchronizing frequency. The output from the quadri-demultiplier circuit 56 has a frequency which is an integral multiple of the frequency of the horizontal synch signal.
The phase compara-tor circuit 48 operates to obtain coincidence of the phase with the output signal from the quadri-demultiplier 56. The beat frequency of ,.

the phase comparator circuit 48 is phase-locked and fed back to the VCO 49. Therefore, the frequency of the output from the VCO 49 is lower than the frequency of the carrier wave by a predetermined value and the beat frequency is phase--locked with respect to the reference signal formed by thehorizontal synchronizing signal. In consequence, the oscillation frequency and phase are held stably. The frequency of the VCO 49 constitutes a sub-carrier wave fOL
the digital data added to the horizontal synch signalO

The output of the VCo 49 is received by the gate circuit 50. The image signal from the brancher 42 is detected by the detection circuit 46 and is delivered as the signal waveform for amplitude variation to the horizontal synchronization separation circuit 52 and the vertical synchronization separation circuit 53, and the horizontal and vertical synch signals are separated by respective circuits 52 and 53. The horizontal synchronizing signal is delivered to the phase comparator circuit 54 while the vertical synchronizing signal is delivered to -the line counter circuit 58 as the rese-t signal. The output from the phase comparator circuit 54 is received by the VCO 55.
The output from the VCO 55 of a frequency of about l0 MHz is inputted to the phase comparator circuit 54 -through the quadri-demultiplier 56 and -the l/160 demultiplier 57.
The phase compara-tor circuit 54 detects the offset of the -27- ~2~

output of the VCO 55 and the horizontal synchronizing signal from each other -to make the phase of -the oscillation wave from the VCO 55 coincide wi-th the phase of the horizontal synchronizing signal. Namely, phase locking i-s effected by th.e PLL. The oscillation frequency of VCo 55 is about lO MHz whlch is 4 x 160 times as high a~
the interval A (63.6 ~sec) of the horizontal synchxonizing signal. The wave oscillated from the VCO 55 is demul~:iplied by the quadri-demultipl`ier 56 into a fre~uency of about ~;5 MHz, and is inputted to the phase comparator circui t 48.which operates to attain a coincidence of phase between the output from VCO 49 and the beat frequency formed by the picture carrier wave. Thus, the horizontal synchroniz~
ing signal included in the picture carrier wave attains perfect synchronization or coincidence of phase between the phase of the VCO 55 and the phase of the beat frequency formed by the output of the VCO 49 and the picture carrier wave.
The outputs from the 1/160 demultiplier 57 and the line counter 58 are delivered to the timing ~eneration circuit 60 by means of the counter outputs 61 and 62, respectively. The timing generation circuit 60 produces a timing signal as an instruction signal for controlling -the operation of the encoder 30. The random number generat-2S ing circult 59 produces false random numbers of 8 bits -28- ~ 6~

at each receipt of the signal from the vertical synch separation circuit 53. This signal is received once for each field. The random number signal is delivered by means of the random number output 63 to the memory processing circui~ 64 and -the code conversion circuit 65. Therefore, the memory processing circuit successively memorizes anew random number for each field of the picture, and delivers the memorized random numbers in accordance with the instruc~
tions given by the timing output 70 as a data signal.
The memory processing circuit 64 processes the random number data signals coming fro~ the random number generator 59 of 8 bits into random numbers of 4 bits. The memory processing circuit 64 then puts a start bit at the starting end of each random number of 4 bits and a parity bit on the tail end of the same. The 8-bit random number output 63 is also subjected to a code conversion by a predetermined procedure, and is delivered to the memory circuit 69 as an 8 bit conversion output 68. The memory circui-t 69 successively memorizes the random number for each field of the picture sur~ace. Then, in the memory circuit 69, each bit of -the converted random number of 8 bits is delivered to a corresponding one of 8 sections of the picture section-ed in accordance with -the instruc-tions from the data bus 71.
Fig. ll schematically shows the mutual relation-ships and differences among the operation of the random number generation circuit 59 and the operations of the memory processing circuit 64, code conversion circuit 65 and the memory circuit 69. I'he random number generating circuit 58 generates random numbers of 8 bits. The random number is composed of "l"'s and "0"'s. The level 'i:L'~
indicates that the horizontal flybaek seetion is level-compressed, while "0" indicates that level-compression of the horizonta;l flyback seetion is not rnade. The random number inputted to the memory proeessing circuit 6~ is processed into a number of 12 bits, with a start bit and a pari-ty bit annexed to the starting and traili~g ends of each four bits. The signals of 12 bits are then successively inputted to the shift register circuit 67.
lS This shift register circuit proeesses each 12-bit signal in two operations, i.e., 6 bits each time, to produce the random number. On the other hand, the code conversion circuit 65 effeels code conversion of -the 8-bi-t random number in aecordanee wi-th a predetermined proeedure. The thus converted random numbers of 8 bits are stored in the memory circuit 69, and each bit of this signal is alloted to eaeh of 8 sections of the pieture, to thereby effeet the determination as to whether the horizontal flyback section of eaeh of the 8 pieture sec-tions should be made or not. The outputs of the AND gate circuits 72 and 73 ~2~

take the level of "1" or "0" depending on the states of the signals a, _, c, d, g and the timing outputs 70, 71 from the timing generation circuit 60, to thereby make the shiEt register c.ircui-t 67 output the data signal.
The control of the encoder 30 by the timing generation circuit 60 causes the following operations of the encoder 30.
(A) Alloting of level-compression to horizontal f.lyback sections of portions where the picture signal is sectioned into a field:
(B) Addition of a de-scrambling key signal to the horizontal synchronizing signal:
(C) Level-compression of horizontal synchronizing slgnals of specific picture regions alloted by the random number.
These three operations proceed simultaneously.
Each of these three opera-tions will be explained more fully hereinunder wi-th reference to a timing chart.
(A) Alloting of level-compression to horizontal flyback sections:
Fig. 12 shows the timings of the signals in one field. More specifically, the upper part shows the 8 sections of picture in each field, as well as -the signals d, e, f, while the lower part shows a picture signal. The timings in the upper and. lower parts coincide with the timing of the start of the fields. The picture signal in the lower part of Fig. 12 is shown in a larger scale.
(l) ¢ommencement of counting by the vertical synch signal;
The ver-tical synchronizing signal inputted through the picture detection circuit 46 is separated by the vertical synch separation circuit 53. The line counter circuit 58 is resei at a timing of 3H (H being a hoxizontal synchronizing period) from -the rise of the vertical synchro~
nizing signal. At the.same time, a new ràndom number is generated by the random number generating circuit 59.
At this moment, the line counter circuit 58 starts to count the demultiplied output from the 1/160 demultiplier 57.
(2) Sectioning of the field;
As a result of commencement of the counting by the line counter 58, the horizontal synchronizing periods H
are counted, and the field is sectioned into 8 sections I
to VIII, one each time 32 periods E~ are counted.

(3) Outputting of the signal for scrambling;
The converted random number of 8 bits is s-tored in the memory circuit 69 through the code conversion circuit 65. Then, the random number signals ~ of respective secti.ons are ou-tputted in accordance with the instruc-tions of the data bus 71. Assume here that a random number expressed by (1,0,1,1,1,0,0,1) is outputted from the random number generating circuit 59.- This random number is converted by the code conversion circuit into a signal which is e~pressed by (1,1,0,1,0,0,1,1). The converted random num~er is inputted into the memory circuit 69 whic.h in turn delivers one "1" or "0" signal to each of the 8 sections in a synchronous manner in accordance with trle instructions given by the data bus 71. When this signa:l _ takes a level "1", the corresponding horizontal flyback section is level--compressed, whereas, when the signal ~ is "0", the horizontal flyback section is not processed but~:
is outputted in -the original state.

(4) Period of addition of the data signal;
As stated before, the line counter cir-cuit 58 counts the horizontal synchronizing periods H. Thenurnbers of the successive horizontal synchronizin~ signals, which rise in successive horizontal synchronizing periods H, are represented by L, starting with No. 0 (zero) which is the horizontal synchronizing signal at which the line counker circuit 58 is rese-t. The Nos. L of the horizontal signal counted by the line counter circuit 58 are delivered to the timing generating circuit 60.
The timing generation circ~lit 60 operates to main-tain the signal d at -the level "1" within the period between 16L and 27L-and clelivers the same to the AND ga-te circult J

-33~

72. It is, thecefore, possible to add the de-scrambling key signal to the horizontal synchronizing signals within the period between 16L and 27~. A detailed explanation will be given later as to how the key signal is actually added. The addltion of the da-ta can be made -to each of the 12L immediately after the ending of the vertical flyback section. In this embodiment, by way of e~ample, the key signal Eor de-scrambling is added only to 16L a~d 17L. It is possible to repetitionally add the key sig~als to other horizontal synchronizing signals of lOL to ensure a more complete transmission and reception of the dataO

(5) Control of the scramble of the picture signal;
The signal g takes the "1" level only within the period of between 28L and 239L. ~h,is signal g of "1"

level is delivered to the AND gate circuit 73. Thus, when the signal g takes the "O" level, the output from the A~D
gate circuit necessarily takes the "O" level, regardless of the signal f for level compression of the horizontal flyback section. Thus, no processing is performed within the periods between O and 27L and after 2~0L, so that the outpu-t g of the AND gate circui-t 73 takes the "O" level ln these periods even if the signal f takes the "1" level.
Thus, in these periods, the picture can be received as it is. However, since most of the picture surface is scrambled, it is not possihle to correctly view the picture unless .,

6~

de-scrambling processing is conducted.
(6) I,evel compressi.on of -the horizontal flyback section;
The signal for controlling the switching ampli.fier circuit 44 is supplied from the AND gate 73. The AND
gate circuit 73 prodwces an output of "1" le~el only wher all of the signals a, f and g are received simultaneousl~
When these three signals are inputted simultaenously, ~he AND gate circuit: 73 operates to lower the amplitude of the switching circui.t 44 to lower the amplificatio,~n factor of the switching a~lplifier circuit 44 to thereby effect -the level-compressionof the horizontal flyback section. An explanation of the level-compression will be given later.
(B) Addition of.' the de-scrambling key signal to the horizontal synahronizing signal:
The scxambling processing by level compression of the horizonta!l flyback section is effected by the encoder 30, while a decoder 81 necessita-tes a de-scrambling key signal for reproducing the correct picture. ~n explanation will be made hereinunder as to how the key signal is added with specific reEerence -to Fig. 13,. whic.h is a timing chart for adding this key signal to the horizontal synchronizing signal. The picture signal in the upper part is the IF
signal in the s-t.ate before being input to the encoder 30, while the picture signal in the lower part is the IF signal -35~

after being output from the encoder 30. In this embodiment, the period between adjacent horizontal synchronizing signals is divided into 1/160 sections, and each signal is outputted using the -timing of l/160 as the reference clock.
(1) Formation of the oscillation wave for -the data signal;
As sta.ted before, the PLL circuit is composed of the mixing circ~Lit 47, phase comparator circuit 48 and the VCO 49. The frecIuency produced by the phase comparator circuit 48, about 2 5 M~z lower than the picture signal carrier wave, is stably supplied by the VCO 49 to the gate circuit 50. The~ oscillation wave of VCO 49 serves as a sub-carrier wave for the key signal.
(2) Formation of constantly generated signals;
The -ti.ming.genera~ion circuit 60 receives clocX
signals on the basis of the horizontal synchronizing signal from the l/160 clemultiplier 57 and the line counter circuit 58. The phase of the frequency of the 1/160 demultiplier circuit 57 is made to coincide with the phase of -the oscillation wave from the VCO 49 by means of the phase con~parator circuits 48 and 54. To this end, i-t is necessary to employ signa:Ls b, c and h which are outputted at constant periods regardless of other signals. These signals b, c and h are based on the fall of e which falls in response to the rise of a horizontal synchronizing signal outputted v~ ~

~2~8~

from the horizontal synch separation circuit 52,ar~d takes the "0" level over a period of 12H/160. The signal b is pro-duced around the center of the horizontal synchronizing signal, and serves as the shift lock for -the shift register circuit 67. The signal b is outputted for a period of 6 (six) cycles of the clock haviny a frequency whlch is 160 times as hi.gh as that of the horizontal synchronlzlncJ
frequency. On the other hand, the sigr-lal c is used for opening the AND gate circuit 72, and is generated within the per.iod of t:he ou*puttlng of the signal b at the .same timing as the latter. The signal h is the 1/150 demultipli-ed output from the 1/160 demultiplier 67. The signal h falls when the horizontal synch separation signal e falls and rises substantially at the midst of each horizontal synchronizing signal. The line counter circuit 58 is made to count up when the signal _ rises. These signals_/ c and h are produced constantly.
(3) Signals produced for adding key signals;
The k:ey signal is added not -to all of the horizont-al synchronizing signals but only to the horizontal synchronizing signals of specific posi-tions, which are at 16L and 17L in the described embodiment. To -this end, the timing generation circuit 60 produces a signal d which indicates the horizontal synch signals to which the key signal is to be added. The signal _ takes the "1" level ~, 6~i only when the da-ta signal is added to a specific horizontal synchronizing signal. The change of level from "l" to "0"
and vice versa is made when-the signal h rises, so as not to adversely affect the horizon ~ synchronizing signal. In ~e illustrated e~x~i-ment, ~e signal "d" ~ssumes-the "l" level in the periods oE ~he horizontal synchronizing signals 16L and 17L.
(4) Addition of the key signal to the hoxizonta:L
synchronizing signal;
As stated before, the gate circuit 50 receives the s~b-carrier wave from the VCO 49, while the AND ~a-te circuit 72 receives the signals c and d, as well as the output from the shift register circuit 67. The shift register circuit 67 receives the signal b. The output from the gate circuit 72 assumes the "1" level only when all of the signals c and d and the output from the shift register circuit 67 are received. The shift register circuit 67 successively receives 6 (six) cycles of signal b, and the data signals of 12 bits derived from -the memory processing circuit 64 are successively output-ted.
Therefore, da-ta sisgnal (lllOlO) is delivered to the AND
gate circui-t 72 for the horizontal synchroni.zing signal 16L, as shown in Fig. 11. The gate circuit 50 is opened and closed by -the output from the shift register circuit 67, and delivers -the sub-carrier wave from the VCO 49 through the band pass filter 51 to the coupler ~3 in one cycle of -38- ~ 25 the clock frequency, which is 1~0 times as high as the horizontal synchronizing -Erequency per bit. In consequence, a burst signal of the sub-carrier wave is superposed on thehorizontal synchronizing signal, and the envelope of the thus formed horizontal synchronizing sigrial forms a sine wave of one cycle per bit. Thus, a sine wave corresponding to (111010) is added to the horizontal synchronizing signal l~L. Similarly, the da-ta signal (100111) shown in Fig. 11 is added to the horizon-tal synchronizing signal 17L. For subsequent horizontal synchronizing signals starting with 18L, the AND gate circuit 72 does not operate because the signal d takes the "0" level, so that no data signal i5 added to these horizontal synchronizing signals.

5 (C) Level compression of horizontal synchronizing signals of specific regions as alloted by random numbers.
As s'hown in Fig. 5(b), the TV picture surface is divided into 8 sections. The random number generated by -the random number generation circuit 59 determlnes whether each of these ,ections ls -to be scrambled or not. The scrambling is made by effecting level-compression of the horizontal synchronizing signal of portions where the picture is to be destroyed. This level-compxession opera-tion will be explained hereinunder with reference to Fig. 14. The waveform of the picture signal before L8~

inputting to the encoder is shown in the upper part, and the waveform o:E the picture signal as output from the encoder is shown in -the lower part of this figure.
(1) Signals produced cons-tantly;
The timing generation circuit 6~ constantly outputs the control signal to the memory circuit 69 l:hrollgh the data bus 71. Upon receipt of this control signal from the timing generation circuit 60, the memory circuit 75 successively outputs the random number of 8 bits delivered by the random number generation circuit 59, as the signal f. More specifically, as shown in Fig. 12, the random number of 8 bits is successively outptted as the signal f for time lengths each.of 32H, and the signal f continues to take the "1" or "0" level during each time length 32~I. The change of the level of the signal f is made at a timing coinciding with the timingof the rise of the signal k and apart from the horizontal synchronizing signal. In addition, -the signal _ of "1" level is produced in one field within the period between 28L and 239L.
(3) Level compression of horizontal flyback section;
As el~plained before, the AND gate 73 receives signals a, f and g. When all of the signals a, f and g take the "1" level, the output ~ from the AND ga-te circuit

7.3 takes the "1" level.to lower the amplification factor 'L~L~
-40~

of the switching amplifier circuit 44. Therefore, as shown in the lower lef-t part of Fig. 14, the horizontal synchroniz-ing signal is level-compressed, in the portion of the horizontal flyback section (33/160H) between a moment 7/160H
ahead of the rise -thereof and 26/160H after the rise of the horizontal synchronizing signal, to the "gray" level t:o effect the so-called "gra~-synch" processing. However, when either of the signals f and g is changed to the "0"
level, the output from the AND gate circuit 73 is changed to "0" even though the signal a is being received.
Therefore, level compression is not effected. In conse~uence, as shown at the central portion in Fig. 14, the picture si in the horizontal flyback section corresponding to this period is outputted from the switching amplifier lS circuit 44 without compression.
Thus, in the encoder 30, a key signal for de-scrambling is added to the picture signal and, at the same time, the signal in selected horizontal flybac]c sections~
is level-compressed to effect the scrambling of the picture. Therefore, at -the receiverside, it is necessary to de-modulate -the scrambled picture by means of the decoder 81. The decoder 81, therefore, is required to perform the following processiny.

(D) pick-up of the key signal for de-scrambling and analysis of the same:

-41- ~2~

(E) Removal o~ the key signal added to the horizontal synchronizing signal:
(F) Level expansion of the level-compressed fly-back sections.
~ de-tailed explanation will~be given hereinunder as to each of the processing steps mentioned above4 The picture signal inputted to the decoder 81 i.5 transmitted to the brancher 85 and, thereafter, deli~ered to the TV receiver 11 through the switching amplifier circuit 86 and through the trap circuit 87, respectively~
The switching amplifier circui~ 86 has two amplication factors. Namely, a high amplification factor is achieved when the signal n from the AND gate circuit 105 takes the "1" level. On the other hand, the trap circuit 87 performs its trapping action only wh~en the signal k takes the level "1". The picture signal delivered by the brancher 85 to the picture detection circuit 88 is detected bv the latter, and is delivered to the horizontal synch separation circuit 90 and the vertical synch separation circuit 91 which are adapted to deliver the horizontal synchronizing signal and the vertical synchronizing signal -to -the counter circuit 98 and the line counter circuit 99, respectively. The line counter circuit 99 is reset by -the output from the vertical synch separation circuit 91. The reset signal is delivered a-t a timing of 3H after the rise of the vertical synchroniz---42~

iny signal, as in the case of the,encoder 30. The coun-ter circuit 98, reset by the signal r from the horizontal synch separation circuit 90, counts a stable frequency (2,5176 MHz) from the oscillation circult 100 -to precisely divide the interval of -the horizontal synchronizing signal into 160 sections, and delivers the counter output 102 to the timing circuit 101. The output p (1/160 demultiplied output) of the counter circuit 98 is delivered to the line counter circuit 99. The output p is one similar to -the signal h of the 1/160 demul*iplier circuit 57 of the ,-aforementioned encoder 30, and rises at a timing substantially in the midst of the interval between adjacent horizontal synchronizing signals. The line counter circuit 99 counts the number of rises of the output _. The counter circui-t 98 can maintain exact timing by the 1/160 demultiplic-ation of the wave oscillated from the oscillation circuit 100, even when horizontal synch separatio.n is not conducted due to level compression of -the picture signal in the horizontal flyback section due to scrambling~ By means of the counter output,s 10~ and 103, signals are delivered by the counter circuit ~8 and the l.Lne counter circui,t 99 to the timing circuit 101, which then analyzes these signals to issue the signals 1, k, 1, s and -the timing output 10 to thereby control the timing of the operations of every part of the decoder 81. More specifically, -the _~3_ ~ ~ ~8~5 -timing circuit 101 produces the signal 1 which -takes the "l" level in the period between 28L and 239L, the signal s for sectioning the picture surface at each 32H after the start, the signal k which is generated when the horizontal synchroni~ing signals 16L and 17L are present, and the signal ~ produced in the horizontal flyback section o-f each synchronizing signal.
The operations (D), (E) and (F) mentioned above will be explained more fully with reference to timing charts (D) Pick-up and analysis of the key signal for de-scrambling:
The data de-modulation circuit 89 separates the data signal containing the key signal from the picture signal detected by the picture detection circuit 88 and picks up the same. The data signal is then delivered to the memory processing circuit 93 by means of the data output 92. The data signal outputted from the da-ta demodulation circuit 89 is a signal of 12 bits includ;lng;start bits and parity bi-ts. The memory pxocessing circuit 93, therefore, operates to output the 8 bit key signal (11010011) shown in Fig. 12, after the removal of the startand parity bits.
The demodulated key signal, however, does n~-t correspond to the state of scrambling of -the picture surface and, therefore, it is not possible to demodulate the picture 2~
~4 signal with this key signal. Therefore, the processed output 9~ is delivered -to the code conversion circuit in which code conversion is made -to change this signal into a key signal expressed by (1,0,1,1,1,0,0,1). This key signal, after code conversion, corresponds to the ssrambled picture surface. The 8-bit key signal after the code conversion is delivered to the shift register circuit 97, which outputs this converted key signal in bit-by-bit fashion each time the signal s is received.
(E) Removal of the key signal added to the horizhntal synchronizing signal:
As explained ~efore, the data signal shown in Fig. 4 is added to the horizontal synchronizing signals 16L, 17L. The reproduced picture surface may be adversely affected by the da-ta signal if these horizontal synchronizing signals are received by the TV receiverdirectly. It is, therefore, necessary to get rid of this data signal within the decoder 81. To this end, the timing generation circui-t 101 delivers to the trap circuit 87 the signal k which takes the "1" le~el only for the period of 11~/160. Upon receipt of this signal k, -the trap circui-t 87 operates to remove the data signals from the horizontal synchronizing signals 16L and 17L. The signal k is applied only to the horizontal synchronizing signal -to which the data signal has been added, and is no-t generated in the periods of ~45~ ~ 6~

other horizontal synchronizing signals. The left part in Fig. 16 shows the process o~ removal o~ the data signal ~y the signal k. Namely, the waveform in the upper part of Fig. 16 shows the picture signal before inputting to the decoder 81, while the waveform of the picture signal outputted from the decoder 87 is shown in the lower part of Fig. 16.
(F) Level expansion of the picture signal in the level-compressed horizontal flyback .section:
As s-tated beforer the encoder 30 has effected level-compressionof the horizontal flyback period of the portion of the picture to be destroyed. Therefore, the decoder 81 is required to effect level expansion of the horizontal flyback section of the level-compressed portion by means of the analyzed ~ey signal. The level e~pansion is effected by the output from the shift register circuit 97 and the signals 1 and 1 from the timing generation circuit.
(1) Signalsproduced constantly;
The horizontal synch separati.on circuit 90 delivers to the counter circuit 98 -the signal r, the level of whlch falls concurrently with -the rise of the horizontal synchronizing signal, the horizontal flyback section of which is not level-compressed. The counter circuit 98 is -46~

reset by the fall of -this signal r to effect 1/160 demulti-plication of the oscillation output from the oscillation circuit 100. The counter circuit 98 then delivers the 1/160 demultiplied signal p to the line counter circuit 99 and a counter output 102 to the timing generation circuit :L01.
The line counter circuit 99 counts the line No. corresponding to each horizontal scanning line through the counting of the signal p, and delivers the counter output 103 to the timing generation circuit lOlo The timing generation cir-cuit 101 constantly~produces the signal i which takes the"1" level over a period of 29~/160 starting from a moment SH/160 ahead of the fall of the signal p and 24H/160 behind the same. The period 29H/160 is the period of the level expansion, which is shorter than the period 33H/160 of the level compression shown in Fig. 14.
(2) Signals produced during level expansion;
The signal 1 is delivered by the timing generation circuit 101 to the AND gate 105 in response to the output from the line counter circuit 99. The signal 1 takes the level "1" in the period between 28L and 239L, and the level of -this signal 1 rises or falls concurrently ~ith the rise of -the signal p. The level expansion of the horizontal synchronizing signal is not conducted in periods other -than the period in which the signal 1 takes the level "1". The signal _ indica-tes the de-scrambling ~ey ~47~

signal from the shift register 97 in terms of "1" or "0".
- Namely, level expansion is conducted when the same takes the level "1". The signal m is shifted ~y the signal s outputted from the timing generation circuit 101 at each - 32H. For instance, a code-converted 8-bit signal such as "10111001" is outputted bit by bit for each 32H. The signal m is held during the period 32H.
(3) Level expansion (de-scrambling) of -the horizontal synchronizing singal;
As stated before, the AND gate circuit 105 receives the signals ~, 1 and m. When all of these signals ~, 1 and m take the level "1", the AND gate circuit 105 deIivers a signal of "1" level to the switching amplifier circuit 86 to thereby increase the amplification factor of the switching amplif.ier circuit. The switching amplifier circuit 86 can so operate only in the period of 29H/160 in which the signal i takes the level "1". This period in the period of the horizontal synchronizing signal is expanded to the original level so that -the horizontal synchronizing signal may be separated by -the T~ receiver.
The level-compressed horizontal flyback section is shown at the upper central portion of Fig. 16, while the horizont-al flyback section level-expanded to the original level is shown at-the center of thelower portion of the same figure.
As will~ be seen from Fig. 16, valleys of periods of 2~ l60 -48~ 6~5 are formed at both sides of the level-expanded horizontal flyback section. These valleys, however, do not adversely affect the separation of the horizontal synchronizing signal nor the picture surface because they are~a-t -the white level side. When the signal m takes the level "0" t the AND gate circult 103 does not deliver the signal -to the switching amplifier circuit 86. However, since level~
compression of the horizontal flyback section was nok made by the encoder 30 in this period, it is possible to separate the horizontal svnchronizing signal even if outputted to the TV receiver wi~hout level expansion.
As a result of the series of operations explained above, the picture signal from the encoder 30 to which the key signal has been added and which was level-compressed in selected horizontal flyback sections is de-scrambled and the key signal is eliminated therefrom. Furthermore, level expansion is effected on the selected horizontal flyback sections torecover the picture signal to -thereby permit the TV receiver to reproduce the correct picture.

Figs. 13, 14 and 16 schematically illuskrate the level-compression, level expansion and -the addition and removal of the data signal, respectively. The picture signals in these figures are of differen-t waveforms from that of the waveform modulated by the carrier wave in the described embodiment. In other words, the actual picture ~ , 49~ 625 signal involves the carrier wave as shown in Fig. 17.
More specifically, Fig. 17(a) shows the waveform of the IF input signal which has not been processed, while Figs. 17(b) and 17(c) show the waveforms after level-com-pression and after level expansion of the horizontalflyback section, in relation to time. On the other hand, Fig. 18(a) shows the waveform of the horizontal synchroniz-ing signal to which the data signal is added by the encoder 30, while Fig. 18(b) shows the waveform after the removal of the data signal by the trap circuii 87.
Fig. 18(c) shows the waveform of the timing for actuating the trap circuit 87, in relation to time.
The method of the invention, constructed as hereinbefore, offers the following advantages.
(1) Since the scrambled picture signal does not accord with the transmitted key signal for de-scrambling, tapping is made difficult due to the code conversion function.
(2) Interchangeability between a plurality of systems can be eliminated by differentiating the code conversion means, even if these systems make use of an identical scrambling system. Therefore, the picture cannot be received correctly among different systems even if the same peripheral equipment is used.
T~us, according to the invention, it is possible to prevent tapping to a satisfactory degree.

Claims (8)

WHAT IS CLAIMED IS:

1. In the scrambling of a TV picture in which the degree of modulation of a specific part of the TV picture signal is altered from the degree of modulation of the orignal signal to prevent normal viewing of the correct picture, and wherein a key signal for de-scrambing is added to the horizontal synchronizing signal of the TV image,a key signal transmitting method, comprising; converting the code of said key signal using conversion means adapted to convert the code of said key signal under a predetermined condition; and transmitting said key signal by adding the same to said horizontal synchronizing signal after said code conversion.

2. A method as claimed in claim 1, wherein at least a portion of said TV picture is divided into a plurality of sections, and each section is independently altered in said modulation degree.

3. A method as claimed in claim 2, wherein said modulation degree is altered by level compressing selected horizontal flyback line sections to prevent normal recep-tion at a TV receiver.

4. A method as claimed in claim 1, wherein said key signal comprises a signal of a plurality of bits superposed on a selected portion of said horizontal synchronizing signal.

5. A method as claimed in claim 4, wherein said key signal is added to the horizontal synchronizing signals of a plurality of lines following vertical flyback sections of said picture signal.

6. A method as claimed in claim 4, including randomly generating said key signals in an encoder using a random number generating circuit, synchronously with vertical synchronizing signals of said picture signal.

7. A method as claimed in claim 1, including converting the code of said key signal using a ROM adapted to effect conversion of a digital code in a predetermined manner.

8. A TV picture scrambling device, comprising; means for altering the degree of modulation of a specific part of the TV picture signal from the degree of modulation of the original signal to prevent viewing of the original picture, means for generating a key signal for de scrambling said picture, means for adding said key signal to a horizontal synchronizing signal of the TV picture signal, means for converting the code of said key signal, said converting means being adapted to convert the code of said key signal in a predetermined manner, and means for transmitting said key signal by adding the same to said horizontal synchronizing signal after said code conversion.