JPS594285A - Transmitting method of key signal in scrambling of television picture - Google Patents

Abstract

PURPOSE:To improve the confidentiality, by transmitting a key signal with a scrambled video signal so that the descrambling is not attained only with the separation and analysis of the key signal as it is, for eliminating the inerception and the interchangeability of system. CONSTITUTION:A video signal inputted to an encoder 30 from an IF modulating circuit 20 is scrambled at the encoder 30 for being processed so as not to reproduce normal picture as it is, and modulated into a specific channel frequency at an up-converter 22. The encoder 30 performs two operations; one is the level compression of a specific horizontal synchronizing signal, the other is the addition of a key signal for descrambling to the specific horizontal synchronizing signal. A terminal device 28 demodulates the key signal for descrambling transmitted with the video signal from the center 1 with the decoder in a main box, the code conversion is done for the restoration into the normal key signal, the scrambed video signal is descrambed according to the key signal and applied to a television receiver 11 as the normal video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that if you are on the broadcasting service of TV tJ5 (transmission (including both wireless transmission method and wired transmission method)) and receive the broadcast as it is, you will not be able to view the video normally. Regarding a method for scrambling television images that can be restored using a predetermined method and a normal image can be viewed, when adding a key signal for descrambling to a scrambled video signal, Can this key signal code be converted and stolen easily? Regarding the method.

With conventional television broadcasting services, whether wireless or wired, within the range covered by the service network, it is possible to play back images and watch programs as is on a standard television receiver. Ah, I-ko. However, in recent years, with the commercialization of 11 TV broadcasting services, TV programs can only be viewed on the TV receivers of specific subscribers, and TV programs cannot be viewed normally on other TV receivers. The need has arisen. In particular, the J3 CATV system, which provides cable TV broadcasting services and provides a large number of programs, relies on fee collection for its business, so differentiation based on viewers (secret means) has become even more important. . For this reason,
On the side that transmits programs, there is a need for a scrambling method that does not allow the video to be played back normally even if the video is received in its original state after being subjected to specific processing.

First, C A is a form of TV program broadcasting system.
An overview of the l-V system will be explained with reference to FIG. This CATV system has unique features for paid Gake 11 broadcasting.

FIG. 1 shows the entire CATV system. This system consists of one center 1 and several thousand terminal devices 28 connected by coaxial cables. A trunk cable 3 is drawn out from the center 1, and a line amplifier 4 and a branch 5 are provided at predetermined locations on the trunk cable 3. A plurality of branch cables 6 are drawn out from this branch 5, and each branch cable 6 is provided with an extension amplifier 1 and a tap-off 8 at a predetermined location. A plurality of branch cables 9 are drawn out from each tap-off 8, and the terminals of each branch cable 9 are drawn into each home 2. Terminal device in each home 2 Main box 10
The terminal of the branch cable 9 is connected to the main box 10, and the television receiver 11 and the control box 12 are each connected to the main box 10.

In other words, the center 1 and each household 2 are arranged like a Christmas tree.
The terminal devices 28 are segmented and connected.

A receiving antenna 13 is erected outside the center 1, and the receiving antenna 13 is connected to a demodulator 15 in the source 8Y14. This source group 14 includes a video disc player 1G and a video cheap player 1G.
1, Stan No. 18 etc. The modulation sending unit 19 that receives the signal from the source 8Y14 consists of two types of systems: an IF modulation circuit 20, a scrambling circuit 21,
There is a system for an upconverter circuit 22, an IF modulation circuit 23, and an upconverter circuit 24, and the outputs of the upconverter circuits 22 and 24 are connected to the main cable 3, respectively.

Furthermore, a data transmitter/receiver 4jll [25] that communicates with each main box 10 is connected to the trunk cable 3, a Compico-926 is connected to the data transmitter/receiver 25, and a printer, display, etc. are connected to the computer 2G. The surrounding stations @27 are connected.

Next, the operation of this CATV system will be explained.

TV receiver [Turn on 1111 and control box 1]
2 to select the desired channel, the main box 10 attempts to receive the image from channel 17, which is not aired. The signal is frequency-converted into a channel and supplied to the image receiving +M11. ” control box 12
The types of channels that can be selected can be divided into the following groups: (A) Retransmission of TV radio waves as they are, (B) Independent programs (free), and (C) Right-handed programs. Each group has several channels, and a total of 20 to 30 culms can be selected.

(Δ) Retransmission 0 The television radio waves received by the receiving antenna 13 are demodulated once by the demodulator 15 and sent to the modulation transmitter 19. The modulated signal (No. 75 is increased to a specific frequency by the up-converter circuit 24) and is modulated by the IF modulation circuit 1 to circuit 23. is transmitted to the home 2 via the trunk cable 3, branch cable 6, and branch cable 9, and is transmitted to the television receiver 11 via the terminal device 28.
image is received.

(B) Independent programs such as weather forecasts and Futabasu programs, recorded programs by the video disc player 16 and video cheap recorder 11, and live programs produced in the studio 18 are provided by the IF modulation circuit 23 and the up-converter circuit. 24, the frequency is converted to a specific channel, and the signal is transmitted to the trunk cable 3.

This program is free of charge regardless of the number of times it is watched or the time, and each household 2 can watch it for a basic monthly fee.

(C) Programs on the right 131 New I1 movies and specific programs, recorded programs by video cheap disk play 1716, video cheap play''-da17, and live programs produced by Stan'A18 are I6-F: The image signal is modulated by a modicolate circuit 20, and a specific synchronization signal is added to the image signal by a scramble circuit 21, so that the image signal is processed so that it will not become a normal image even if it is received as is. Next, an up-inverter circuit 22 increases the frequency of the signal to the frequency of a specific channel 17 and sends it to the main cable 3. When each household wants to receive a right-handed program, the signal sent in the main box 10 is demodulated into a normal image signal and transmitted to the television receiver 11, so that it can be viewed on a normal screen. can. If you receive this right-handed program, you will be charged a preset fee, and you will be charged a special usage fee in addition to the basic usage rate for the fa month.

The center 1 and the terminal equipment 28 of each home 2 are connected by a coaxial cable, but if you do not know which channel the home 2 is receiving at a particular time, it is difficult to distinguish between paid and free programs. Therefore, fair operation of the CATV system cannot be expected.

For this reason, the data transmitter/receiver 25 sends out a search signal at regular intervals, calls the main box 10 of each terminal device 28 with its individual address number, and checks which channel is being received at the time of the search. This is called polling.

Therefore, the main box 10 outputs a response indicating which channel is being received at that time, and sends it to the data transmitter/receiver 25. The received data of the data transmitter/receiver 25 is processed by the computer 26, and the peripheral device 2
Displayed or launched by 1.

Since this polling is performed at regular intervals (every several to several tens of seconds), viewership ratings and the like can be compiled immediately.

In addition, some programs involve viewer participation, allowing viewers to operate the control box 12 and respond to the questions in the program while watching the television receiver 11. data) is sent to Intercenter 1 via a coaxial cable.

In this conventional television broadcasting service, the video signal sent from center 1 for a specific program is scrambled (
In order to properly receive this scrambled video, disk crumple processing must be performed on the terminal device 28 side, and there are some things that must be adjusted to the normal video signal. Eavesdropping cannot be prevented if the processing is very basic and descrambling is extremely easy.In order to operate a television video transmission system soundly, it is necessary to use advanced technology that does not easily allow eavesdropping. A scrambling method was required.

In the conventional scrambling method, the modulation level of the horizontal synchronization signal of the video signal at the R stage on the transmitting side is changed.The so-called "Gray sync method" is often adopted, and the phase of the modulation is changed along with this modulated video signal. It sent out an encoded signal of a sine wave that was inverted. On the receiving side, the Ic is scrambled according to this encoded signal.
In this case, descrambling was performed by demodulating the video signal. In this conventional gray sink method, (1
) On the descrambling side, a process involving analog processing is used, which tends to cause noise and distortion.

(2) Since the scrambling and descrambling processes are simple, confidentiality is relatively low and eavesdropping is likely to occur.

9- There were drawbacks such as.

For this reason, a method of scrambling by applying digital technology and changing the modulation level of a specific horizontal synchronizing signal has been proposed.

In other words, only the horizontal retrace section in the video signal is level-compressed so that the video cannot be synchronized, and when demodulating, only the horizontal retrace section is level-expanded in steps, and then , it is possible to select a horizontal retrace interval at any position and compress and expand the level, and by changing the selected horizontal retrace interval periodically with pseudo-random numbers, it is possible to prevent images from becoming out of synchronization. was. Even in this case, since the receiving side can descramble, a key signal (digital code) is sent out at the same frequency as the carrier frequency of the video signal, and the scrambled video signal is demodulated using this key signal. However, once the person making the eavesdropper knows how to send out the key signal, it is easy to restore the corresponding screen, and if they have a proper terminal device, they can scramble using the same method. This makes it possible to use a common terminal device in a system in one area, and to descramble the terminal equipment used in one area's system even if it is used as is in another area's system. For this reason, if broadcasting system companies with different management lines use the same method to scramble programs, no matter how many companies' terminal equipment is used, the programs will be successfully descrambled and the programs will be scrambled! It was possible to write a message, and there was a low degree of secrecy.

In view of the above-mentioned drawbacks, the present invention scrambles the video signal using a predetermined method, and at the same time converts the key signal into a code using a predetermined conversion method. It is possible to transmit and separate the key signal as it is, perform FIv analysis, and prevent it from being descrambled in the -1 node, thereby eliminating eavesdropping and system compatibility, and improving confidentiality of TV images. This invention provides a key signal sending method in scrambling.

Next, the rjji of the present invention]! L! The outline is explained below in Figure 2.

FIG. 2 is a waveform diagram of a video signal in the scrambling method according to the present invention, where the video signal is modulated by a carrier wave. This video signal has a modulation degree of 10 for the peak carrier noise.
The horizontal synchronization signal is located at a level of 0%, the maximum black video signal is located at a level close to 70% modulation, and the modulation degree is 1.
The maximum white image (G is located at a level close to 2.5% E1. Therefore, the black and white shading on the screen is 12.5~
AM modulation will be performed in the range of 70% modulation depth, and only the horizontal synchronization signal will be located at the 100% modulation depth, which has a large amplitude, so only the horizontal synchronization signal will be separated to start the scanning line. It can be used as a timing to change the period to lljl period. This 1'! Solid line A' in the video signal shown in Figure 2
The waveform shown in r shows the state before the scrambling process. The horizontal gIF becomes lower and fluctuates toward its own level, and the modulation degree of other image signal parts does not change at all.
Only the iA section portion is level-compressed. , cum,
100% modulation is applied to the horizontal flyback section.Horizontal synchronization No. 18C
The colorverse 1-signal is added to the waste portion whose modulation degree is slightly lower than that of the horizontal synchronous transmission signal C. Next, FIG. 3 shows a waveform in which a key signal for descrambling is added to video No. 16 using the scrambling method of the present invention. A key signal E is added. This key signal is added to the horizontal synchronizing signal of multiple lines after the vertical retrace interval and is added to the horizontal synchronizing signal of the multiple lines after the vertical retrace interval. No compression is performed. Figure 4 is an enlarged view of the horizontal retrace section shown in Figure 3 above.
A key signal E, which is a digital code of bits, is also added. This key No. 15 E has the first bit out of six bits as a start bit, the second to fifth bits as a data bit, and the sixth bit as a parity bit. Here, the start pitch 1- is the data 1
3- Indicates the beginning, and the parity bit is used to check for pit errors in the data. This data bit indicates the state in which scrambling is being performed, and is used as a key during descrambling. If this horizontal retrace interval is received at the level L [reduced and scrambled video 1i (, J) as it is with a telephoto receiver, the synchronization separation circuit of the TV reception IR will not be able to separate the horizontal synchronization signal C and will not reproduce it. The screen that has been descrambled cannot be synchronized, and the screen is garbled.However, if it is descrambled,
In this case, only the level-compressed horizontal retrace interval portion is level-expanded and returned to the original video signal level, so the synchronization signal can be reduced and the image can be demodulated normally. Since the image signal part of the scrambled video signal is not processed, the demodulated and reproduced screen will not have any noise or distortion, and will be normal without going through the scramble and descramble process. You can watch high-quality video similar to that of TV programs.

Next, the state of screen destruction will be explained with reference to FIG. Figure 5 (A) schematically shows a normal screen before scrambling, and Figure 5 (1) shows an example of a screen where the scrambled video signal is played back as is on a television receiver. It shows. In the scrambling method of this embodiment, the screen is divided vertically into 8 parts (not equally divided in this embodiment), and each partitioned section is divided into 8 separate horizontal retrace sections (part C in Figure 3). Horizontal synchronization (fi
8 G <*level compressed +), and the other sections are level compressed and the original video signal is transmitted without being level compressed. For this reason, within one image, the horizontal retrace section may not be treated as a level-compressed portion, and the video may flow horizontally because synchronization cannot be achieved in the level-compressed portion of the horizontal retrace section. The entire image becomes unrecognizable. Also, 8
Whether or not the level of the horizontal retrace section of each section 1 to 'i1 divided into sections is subjected to level compression is determined by random number information and is not always specified. Therefore, the random numbers used to determine level compression or non-level compression in this horizontal retrace section are changed periodically (over a very short period of time), and the scrambling settings are not always the same. Depends on processing
C The image of that section is not always constant on the TV screen,
As shown by the broken line in Figure 5 (0), the screen played back without descrambling changes its flow due to the switching of random numbers from the destroyed video number, and is constantly in motion, even if the original video is Even if it is a still image, it will be played scrambled and if you turn it over, it will fluctuate wildly on the screen, and if it is left as it is, the IA
It has been destroyed to the point that it cannot be heard. Information on which part of the horizontal retrace section divided into eight sections 1 to
The f-TA bit is transmitted to the terminal device (decoder) side, and reading this f-TA bit enables the decoder to perform descrambling at J'3. It should be noted that dividing the screen into 8 parts is just one example, and the screen can be freely set to any suitable value between 4 and 16 parts, for example.

Figure 6 schematically shows the relationship between the video signal and the screen of the television receiver, and shows that some of the total scanning lines of the video signal are not displayed on the screen F. These include the vertical retrace section of more than ten horizontal scanning lines hidden at the top, the horizontal scanning lines before and after it, and the horizontal retrace section of each scanning line hidden on the left side of the screen F. Some of the horizontal synchronizing signals C immediately after the vertical retrace interval in the video signal have the above-mentioned key signal E added to them, but the vertical retrace interval and the scanning line of the part where data is added (=l) (e.g. t, f12
H level) is not subjected to any level compression processing for scrambling, and the horizontal synchronizing signal C can be separated and taken in as it is along with the key signal E, and the data signal is not affected by the descrambling that exists in the data signal. The structure is such that the key number 15 can be easily identified. The other image parts, excluding the vertical retrace interval and the part to which data has been added, are divided into 8 parts as described above, and the level of the horizontal retrace interval is compressed using random numbers for each part, or it is left as is.
will be determined. Horizontal 113rd period signal C of several scanning lines containing video information of the line immediately after the vertical retrace interval mentioned above.
It is determined which part is gray synced by the key signal E added with "0", for example.
It is assumed that the signal of ``1'' is level-compressed, and the signal of ``1'' is level-compressed, and the horizontal retrace section is expanded for the part corresponding to the signal of ``1'', and the horizontal synchronizing signal C By sequentially performing this descramble processing for each field, the screen can be demodulated normally.

Next, a specific embodiment of the present invention will be explained with reference to FIG. 7 and subsequent figures.

Since FIG. 7 shows an embodiment in which the scrambling method of the present invention is applied to a CA TV system, the same constituent members as those in FIG. Said I
An encoder 30 for scrambling is interposed between the F modulation circuit 20 and the upconverter circuit 22. Further, a main box 31 containing a built-in decoder is interposed between the branch cable 9 and the single TV receiver 66111, and the control box 12 is connected to the main box 30.

18- FIG. 8 shows the internal configuration of the encoder 30 described above. Input from IF double signal splitter 42, combiner 43,
It is output via the switching amplifier circuit 44. A limiter circuit 45 is connected to the terminal branched by the brancher 42.
A video detection circuit 46 is connected to the limiter circuit 45.
is connected to a mixing circuit 47, and the output of the mixing circuit 41 is connected to a phase comparison circuit 48 (including a low pie filter).
The output of the phase comparison circuit 48 is input to the VCO 49. The output of C049 is connected to one input terminal of the mixing circuit 57, and the mixing circuit 41 and the phase comparator circuit 4
8. PLL is formed by VC049. V
The output of CO49 is gate circuit (switching circuit) 50
The signal is input to the combiner 43 via a 1-band pass filter 51. The output of the video detection circuit 46 is input to a horizontal synchronization separation circuit 52 that separates the horizontal synchronization signal from the video signal and a vertical synchronization separation circuit 53 that separates the vertical IUJ signal.

The output of this horizontal synchronization separation circuit 52 is connected to one input terminal of a phase comparison circuit (which has a built-in low-pass filter) 54, and its output node j is input to the VCO 55, and the VCO
,'+517) Output GJ, 4 frequency divider circuit 5G, 160
The signals are sequentially input to the frequency dividing circuit 51. The output of the 160 frequency divider circuit 57 is input to the other input terminals of the line counter circuit 58 and the phase comparator circuit 54, respectively.

Further, the output of the vertical synchronization separation circuit 53 is supplied to a line counter circuit 58 and a random number generation circuit 59 that sequentially generates pseudo-random numbers.
is being entered. Reference numeral 60 denotes a timing generation circuit that outputs a timing signal that controls the operation timing of each part of the encoder 30.
0 frequency divider circuit (multiple flipflops [consisting of one block, the frequency division output of each Noritzflop can be output separately) 51
Counter output horn 61 from 91213923 circuit 58
The non-counter output 62 of is input. The random number output 63, which is the output j of the random number generation circuit 59, is sent to the memory processing circuit 64.
is connected to the code conversion circuit 65, and the memory processing circuit 6
4 output data output horn 66 is a shift register circuit 67
It is connected to. This code conversion circuit 65 is, for example, RO
M (Read only lylemoly), etc., converts the digital code according to a preset procedure, and the conversion output 68 of this code conversion circuit 65
is input to the memory circuit 69.

Further, the timing output cuff 0.71 from the timing generation circuit 60 is connected to the storage processing circuit 64 and the storage circuit 69. In addition, the output of the timing generation circuit 60 is sent to the shift register circuit 67 by J3, the outputs c and d of the timing generation circuit 60 and the shift 1 to register circuit 67.
The output of the AND gate circuit 72 is input to the AND gate circuit 72, and the output of the AND gate circuit 72 is input to the gate circuit 50 as a control signal. And timing generation circuit 60
The outputs a and g of the memory circuit 69 and the output Jf of the memory circuit 69 are respectively input to an AND gate circuit 73, and the output of the AND GO 1-circuit 73 is input to the switching amplifier circuit 44 as a control signal.

FIG. 9 shows the inside of the main box 31 in FIG. The output of this inverter 80 is connected to a decoder 81 that performs a descrambling action, and the decoder 81 is connected to a TV receiver (G1 machine 11) shown at 21- in FIG. The control box 12 for selecting the image reception tunnel is connected to the control logic 8 in the main box 31.
The channel selection signal from the control logic 82 is connected to the above-mentioned inverter 80.

Next, FIG. 10 shows in detail the internal structure of the decoder 81 of FIG. 9. The video signal from the converter 80 (
(including audio signals) is transmitted via a splitter 85, a switching amplifier circuit 86 that can change the amplifier to two stages, and a trap circuit 87. It is connected to 11111. The signal branched by the splitter 85 is input to a detection circuit 88, and the output of the detection circuit 88 is input to a data demodulation circuit 89, a horizontal sync separation circuit 90, and a vertical sync separation circuit 91, and is then input to J3.
The output of the data demodulation circuit 89 is input to a storage processing circuit 93 through a γ-data output 92, and the processing horn 94 of the storage processing circuit 93 is input to a code conversion circuit 95.

The code conversion circuit 95 can convert the digital code and restore it to a regular key signal using the reverse procedure of the code conversion circuit 65 described in 11 above. It is connected with the key signal output 9G. As a reset signal to the output μ counter circuit 98 of the horizontal $111 separation circuit 90,
The vertical synchronization separation circuit 91 inputs a reset signal to the line counter circuit 99, respectively. In addition, 100 is +00 Yu (approximately 2
．． 5M H7) output stable frequency? The output of the excavation circuit 100 is input to a counter circuit 98, and the signal P periodically counted and output from the counter circuit 98 is input to a line counter circuit 99. Reference numeral 101 denotes a timing generation circuit which forms and outputs a timing number 15 for controlling each part of this dataer 91. , 103 are input manually, and the timing output 104 from the timing generation circuit 101 is input manually to the memory processing circuit 93, and the signal 11 from the timing generation circuit 101hSI is input to the shift register circuit 97, and the signal 11 from the timing generation circuit 101hSI is input to the shift register circuit 97 output) Jwl and the signals j and Q from the timing generation circuit 101 are respectively input to the circuit 105 to the AND gate circuit 10.
5 is input to the switching amplifier circuit 8G, and furthermore, the signal k from the timing generation circuit 101 is input to the trap circuit 87.

Next, the operation of this embodiment will be explained.

First, the outline of this embodiment will be explained with reference to FIG.
[Input from modicolate circuit 20 to encoder 30
This video signal is scrambled by the encoder 30 (
The signal is processed so that a normal screen cannot be reproduced as it is, and is modulated by an up-inverter 22 to the frequency of a specific channel. In the terminal device 28, the decoder 81 in the main box reproduces the descrambled key signal sent from the center 1 along with the C signal (*(3) and converts the code into a regular key signal. The scrambled video signal is descrambled according to the key No. 15, and is supplied to the television receiver 11 as a normal video signal.

Next, (1) the recorder 30 performs two operations; (1) compresses the level of a specific horizontal synchronization signal;
One is to add a 4-21 number for descrambling to a specific horizontal synchronization number 411.

In FIG. 8, if the video signal input from the IF modulator 1 circuit 20 is less than the IF large input II, the brancher 42. Combiner 4
3, and the switching amplifier circuit 44 selects one of the two amplification levels ff ((amplifies at a lower amplification level than normal only when the control signal from the timing generation circuit 60 is transmitted). The amplified and scrambled video signal 1F output) is input to the up-converter 22. A part of the video signal branched by the splitter 42 has its amplitude limited by the limiter circuit 45 and loses its AM modulation sound, and only the video carrier wave (carrier) is input to the mixing circuit 41 and mixed with the output horn of VC049. The output thereof enters the phase comparison circuit 48 to stabilize the oscillation frequency of the VCO 49.

(A PLL circuit is formed by the mixing circuit 47, the phase comparator circuit 48, and the VCO 49.) The oscillation wave of the output of this VCO 49 has the frequency of the video carrier wave of the limiter 45 (approximately 45.75 M I-I Z ), and the mixing circuit 4715 outputs the difference between these two input frequencies as a beat frequency (about 2.5Ml-1z), and the beat frequency is a phase It is transmitted to the comparison circuit 48. This phase comparison circuit 48
The standard output (160 times the horizontal synchronization frequency, approximately 2.5M l-I Z ) from the 4-frequency divider circuit 56 is input, and the output of this 4-frequency divider circuit 56 is the horizontal synchronization signal. The frequency is an integral multiple of the frequency of , and the phase comparator circuit 48 operates so that the phase matches the output signal of the 4-frequency divider circuit 56, and the Be 1 to frequency of the phase comparator circuit 48 are phase-locked and fed back to the VC049. has been done. Therefore, the output of the VCO49 is a predetermined frequency lower than the video carrier wave, and this beat frequency is phase-locked to the reference signal, which is the horizontal synchronization signal, so that the oscillation frequency and phase are stable. is maintained.

The frequency of this VCO49 becomes the subcarrier of the digital data signal that is added to the horizontal synchronization signal, and this
The output of 9 (also input to the gate circuit 50).The video signal from the splitter 42 is detected by the video detection circuit 46, and the signal waveform of the amplitude fluctuation is ``horizontal synchronization component N1''.
It is transmitted to the circuit 52 and the vertical synchronization separation circuit 53, and is separated into a horizontal synchronization signal and a vertical synchronization signal by the respective circuits 52 and 53, and the horizontal synchronization signal No. 43 enters the phase comparison circuit 54.
The vertical synchronization number is input to the line counter circuit 58 as a reset signal. The output of the phase comparison circuit 54 is input to the VC○55, and the output of this vCQ55 (frequency is approximately 10 MHz) is input to the phase comparison circuit 54 via the 4 frequency divider circuit 56 and the 160 frequency divider circuit 51. C,
The phase comparator circuit 54 detects the deviation between the horizontal synchronization signal and the output of the VCO 55, and converts the optical wave of the VCO 55 into a horizontal direction IVj.
The phase of the signal jH is matched (phase locked by PLL). The R oscillation frequency of the VCO 55 is 4x160 times the horizontal synchronization signal interval A (63.6 μsec) (
The output wave of this VCO 55 is divided by the 4 frequency divider circuit 56 and becomes approximately 2.5M+-12).
The frequency is input to the phase comparator circuit 48, and the phase comparator circuit 48 also matches the phase of the beat frequency formed by the output of the -CVCO 49 and the video carrier wave. In other words, the phase of the CO 55 and the phase of the beat frequency formed by the output of the VCO 49 and the video carrier are completely matched by the horizontal synchronizing signal included in the video carrier. The outputs of the 160 frequency divider circuit 57 and the line counter circuit 58 are input to the timing generation circuit 60 as counter outputs 61 and 62, respectively, and this timing generation circuit 60 inputs the outputs of the 160 frequency divider circuit 57 and the line counter circuit 58 to the timing generation circuit 60.
Outputs a timing signal that instructs the operation of the

In addition, the random number generation circuit 59 generates an 8-bit pseudo-random number from the vertical synchronization separation circuit 53 (each time No. A is input (one signal is input to one field)), and outputs the random number signal as a random number. 63 to the memory processing circuit 64 and code conversion circuit 65. Therefore, the memory processing circuit 64 sequentially stores new random numbers for each field on the screen and stores them as instructed by the timing output cuff 0. The memory processing circuit 64 internally processes the random number data signal from the random number generation circuit 59, divides the 8-bit random number into 4-bit parts, and outputs each 4-bit random number as a data signal. A start bit is added to the front of the bit random number, and a parity bit (=J) is added to the rear.

Further, the 8-bit random number horn 63 inputted to the code conversion circuit 65 is set, the code is converted in a certain procedure, and the code is transmitted as an 8-bit conversion output 68 to the storage circuit 69.
9 sequentially stores new converted random numbers for each field on the screen. In the memory circuit 69, the data bus 71
8 for each division of the screen divided into 8 according to the instructions of
The resulting random number will be output one bit at a time.

FIG. 11 shows a random number generation circuit 59, a storage processing circuit 64, and a code conversion circuit 65. 3 schematically shows the relationship and difference in operation of the memory circuit 69. FIG. The random number generation circuit 59 generates an 8-bit random number, and the random number is composed of a combination of "1" and "0", where "1" means to indicate the level compression of the horizontal retrace interval, and "0"'' means that the horizontal retrace section is not compressed (it is written as it is). The random number input to the memory processing circuit 64 is processed into 12 bits by adding a start bit and a parity pit before and after every 4 bits, and this 12-bit signal is sequentially input to the shift register circuit 67. However, this shift register circuit 61 processes each 6 bits twice and outputs a random number. Further, the code conversion circuit 65 converts the 8-bit random number in a predetermined manner to eliminate the correlation between the random numbers in the conversion process. This converted 8-bit random number is stored as is in the storage circuit 69, and each pip]~ is assigned to a television screen divided into 8 sections, and the level of the horizontal retrace interval of each section is compressed. Settings are being made to enable or disable the

Then, the signal a output from the timing generation circuit 60
, b, c, d, g, timing output J70.71 causes the output of AND gate circuit 72.73 to be "1" or rO
J, and the shift register circuit 67 is operated to output a data signal.

The operation of each part of the encoder 30 by the timing generation circuit 60 includes: (1) Assignment of level compression processing to the horizontal retrace section of the section divided into 1 field screen.

(B) Horizontal opening II (Add one signal to 30- due to descrambling during n9 (=j).

(C) Level-compress the horizontal synchronizing signal in a specific area of the screen assigned by a random number.

These operations proceed in parallel, and each will be explained below along with timing charts 1 to 3.

(c) Allocation of level compression processing for the horizontal retrace section of the section divided into one field screen.

Figure 12 shows the timing of each signal in one field. The upper part shows the 8 divided screen areas and signals d, f, g, and q in one field, the lower part shows the video signal, and the upper part shows the video signal. The timing at the bottom corresponds to the scoot timing in the field, but the video signal at the bottom is shown enlarged.

(1) Start counting with vertical 10j Hakugo.

The vertical synchronization signal inputted from the video detection circuit 46 is separated by the vertical synchronization separation circuit 53, and the vertical synchronization signal is separated by the vertical synchronization separation circuit 53, and the line 2 is detected at the vertical synchronization (31-1 (+-1 is the horizontal synchronization period) from the rise of signal d).
Rehit the 13929 circuit 58 and simultaneously issue random numbers 4
One circuit 59 generates a new random number. From this time, the line counter circuit 58 starts counting the frequency-divided output of the 160 frequency divider circuit 51.

(2) Field division Then, when the line counter circuit 58 starts counting, the horizontal synchronization period 1-1 is counted, and the field is divided into eight divisions from 1 to 2 every 32+-1.

(3) Output of signal for scrambling The 8-bit converted random number stored in the storage circuit 69 via the code conversion circuit 65 is processed by commands from the data bus 71.
A random number BS is sent to each section of the section (4). For example, as shown in FIG. 11, "1.1, Oll,
When the random number “O, Oll, 1” is output from the random number generation circuit 59, the code conversion circuit 65 converts it into “1.0.1.1”.
．． 1.0.0.1'', and this converted random number is input to the storage circuit G9, and according to the instructions on the data bus 71, one ``1'' or ``0'' is stored in each of the corresponding eight categories. ” signals are output with synchronized timing. When No. 18 f is rIJ, the horizontal retrace section at that time is compressed, and when No. 18 is "0", the horizontal retrace section is output as is without any processing. There is.

(4) Data signal addition period As mentioned above, the line counter circuit 58 has a horizontal synchronization period of 1
-1, each horizontal synchronization period 1 is counted with the time when the line counter circuit 58 is reset as the 1st OT.
- Number 1j4J for the horizontal synchronization rising above, that't
It is indicated by number i. In this way, 7 circuits 5
The number l- of the horizontal synchronizing signal that has been counted in step 8 is output to the timing generation circuit 60.

In the timing generation circuit 60, L'3 from 1st discharge to 27L
The signal d is set to the level "1" and sent to the AND gate circuit 72. Therefore, a descrambling key signal "f" can be added to the horizontal synchronizing signal between 16L and 27L. The addition of this key signal will be explained in detail later.

(Note that the horizontal synchronizing signal that can be added to (-J) is available for each of 121-1 immediately after the end of the vertical retrace interval, but in the tree embodiment, it is only possible for 16L and 171 because it is descrambled. Add key number 4M of 33-1.Horizontal synchronization of other 101-1 (
It is also possible to transmit and receive data perfectly by repeatedly adding a key signal to item ii. ) (5) Control of video signal scrambling The horizontal synchronizing signal is between 281 and 239L.
The signal is then supplied to the AND gate circuit 13. Therefore, when the signal g is rOJ, the output of the AND gate circuit 73 is always I'OJ, and is unrelated to the signal f for level compression in the horizontal flyback section.

Therefore, no processing is performed between 0 and 271 and after 2401J, and even if No. 15 is 1, the output g of the AND gate circuit 73 becomes rOJ during this period, and the image remains unchanged. Image reception can be covered. However, since most of the screen is scramped, both images cannot be viewed normally unless disk lamp processing is performed.

(6) Level compression of horizontal flyback section.

A signal for controlling the switching amplifier circuit 44 is supplied from the AND gate circuit 73.
3, when signals a, t, and Q are input at the same time, only 34- outputs a "1" signal, and when these three signals are input, the AND gate circuit 73 lowers the amplification degree of the switching amplifier circuit 44. , the horizontal blanking interval is level compressed (this level compression will be explained later).

(B) Add a key signal for disc ramp to the horizontal synchronization signal.

The encoder 30 performs level compression in the horizontal retrace section and performs scrambling processing, but the f'-da 81 side requires a descrambling key signal to reproduce normal video. is a timing chart that explains the process of adding this +Li signal to the horizontal synchronization signal, and this explains the addition of the key signal.The video signal in the upper row is an IF signal before 30 human power, The lower video signal is the IF (g) after the encoder 30 output. In this example, the horizontal synchronizing signal is divided into 160 equal parts, and each signal is output using the 17160 timing as a reference clock. ing.

(1) Formation of oscillation wave for data signal coding
A PLL circuit is formed by O49, and a frequency approximately 2.5 Mt11 lower than the video signal carrier wave is stably supplied by VC049 to the gate circuit 50 in the phase comparator circuit 48, and the oscillation wave of this VCO49 is becomes the subcarrier of the key signal.

(2) Formation of a signal to be constantly generated The timing generation circuit 60 receives a clock (g) based on horizontal synchronization No. 15 from the line counter circuit 58, such as the 160 frequency divider 51, and the 160 frequency divider 51. The frequency of 57 is connected to the phase comparator circuit 48.54.
The phase is made to match the oscillation wave of O49.

For this reason, the timing generation circuit 60 always outputs the i signals b, c, and l+ at a constant time with reference to the horizontal synchronizing signal, regardless of the input of other signals. These signals S, C, and H fall at the rising edge of horizontal synchronous signal No. 13 outputted from the horizontal synchronous separation circuit 52, and are based on the falling edge of ia signal e, which remains at the rOJ level for a time of 12/1601''. First, signal 0 is generated near the center A4 of horizontal synchronous signal 15, and is the signal clock of register circuit 67 to shift 1, and this signal has a frequency of 160 times the horizontal synchronous frequency. When E1 is clicked, 6#j cycles are output. Further, the signal C is for opening the AND gate circuit 72, and is generated at the same time as the period when k4@b is being output. Signal 11 is a 160 frequency divider circuit 67
The line counter circuit 58 starts counting at the rising edge of this fa signal. It will be uploaded. These signals b,
c and l+ are constantly generated.

(3) Signal generated to avoid adding key signal Next, the key signal is generated in all horizontal cycles 1. -I is not added to the horizontal synchronization signal, but only to the horizontal synchronization signal of 16.171 in this example. Therefore, the timing generation circuit 60 outputs 1, 1d, which specifies the horizontal synchronizing signal to add this key 15. This i number d becomes "1" only when a specific horizontal synchronization (data number 13 is added to j number), and that 1-1" or I
The timing for switching to OJ is the time η when the I signal rises, and it is set at a time when the horizontal synchronization signal F A is not affected. In this example, horizontal synchronization 1 of 16.171
At the time of number 5 (number a and d are "1".

(4) Adding a key signal to the horizontal synchronization signal As mentioned above, the gate circuit 50 receives the subcarrier from VCO4Q, and the AND gate circuit 12 receives No. 15 C1d and shift 1-
The output of the register circuit 67 and the shift register circuit 61 each receive a signal.

The gate circuit 72 receives signals c, d and the shift register circuit 6.
When all the outputs of 7 are input at once, the node j is designated as rlJ.The shift register circuit 67 is sequentially inputted with 6+l cycles of signals, and the 12-bit signal sent from the memory processing circuit 64 is input to the shift register circuit 67. The data signals are sequentially output 1' at the timing of the signal l). Therefore, as shown in FIG. 11, a data signal of "111010" is output to the AND gate circuit 72 in response to the horizontal synchronization signal of IGl, and therefore the gate circuit 50 is opened at the output of this shift register circuit 67. , closes, and outputs the subcarrier from the VC049 to the coupler 43 via the pan 38-band bus filter 51 during one cycle of a clock frequency that is 160 times the horizontal opening frequency per pin 1. The burst signal of the -C subcarrier is also transmitted to the horizontal synchronization number 15, and one envelope of the horizontal synchronization number 15 formed is a sine wave with one cycle per bit.

In this way, horizontal synchronization of 16 [r i 11
Add a sine wave corresponding to "010". Similarly,
Horizontal synchronization number 15 of 17L has rlool as shown in Figure 11.
A data signal of "ll" is added. 18 "In the subsequent horizontal synchronization signals, the AND gate circuit 72 that causes the signal d to become "0" does not operate at all, and no data signal is added.

0) Level compression of the horizontal direction of a specific area of the screen assigned by a random number.

As shown in Figure 5 (b), the television screen is divided into eight sections.
Whether or not each partitioned portion is scrambled is determined by a random number generated from the random number generation circuit 59. Then, the scrambling level compresses the horizontal synchronizing signal of the part that destroys the image. The operation of this level compression will be explained with reference to FIG. The video signal at the top of the figure is the waveform before being input to the encoder, and the video signal at the bottom is the waveform output from the encoder.

(1) The signal timing generation circuit 60 always generates signals from 7/160H in front to 26/IGO in the rear based on the rising edge of the horizontal synchronization signal.
A signal a that becomes "1" is always output between I-1, and while the horizontal synchronization signal 46 is being generated, the signal a is always synchronously output to the AND gate 73. As mentioned above, it is constantly output.

(2) Signals generated during level compression The control Ij's number is output from the timing generation circuit 60 to the storage circuit 69 via the data bus 71, and the storage circuit 75 uses the control signal from the timing generation circuit 60 to generate random numbers. The random numbers of 8 pins 1- received from the generating circuit 59 are sequentially sent out as a signal f. This I1" outputs an 8-bit random number sequentially in each period divided into 321-th υ as shown in FIG. The output is maintained for 1". The switching timing of the signal f is the rising timing of the signal, and is at a position 1111 K in the horizontal direction, which is away from the signal. Also, as shown in FIG. 12, Imu-g outputs the 1h number of "1" at 281- and 239L at 17f-old.

(3) Level compression of horizontal flyback section As mentioned above, the AND gate circuit 73 has (No. 8 a).

[, q are input respectively, 4'LE No. a, f, g
When both are "1", the AND gate circuit 73 sets the output signal q to "1" and lowers the amplification degree of the switching amplifier circuit 44. For this reason, as shown on the lower left side of FIG. 14, the corresponding horizontal synchronization 1. ) (other rising front 7/160H to rear 26/1601-1 horizontal blanking section (33/160' I-1) was level compressed and moved to a gray level, resulting in so-called gray sync. However, when either the human input signal f or 9 becomes rOJ, the AND gate circuit 73 changes its output to 0'' by the switching amplifier circuit 44 (without compression, the horizontal retrace section corresponding to that position as shown in the center of FIG. 14 is output from the switching amplifier circuit 41-44 as is) Become.

In this way, on the encoder 30 side, a key signal for descrambling is added to the video &(,=i), and a specific horizontal retrace section is level-compressed and scrambled. - On the decoder 81 side, the destroyed video must be demodulated.The processing performed within the decoder 81 includes: (D) Capture and analysis of the key signal used for descrambling.

(E) Removal of key No. 155 added to the horizontal synchronization signal.

F Level expansion of level compressed horizontal retrace section.

Examples include each process.

Each process will be explained in detail below.

The video signal input to the decoder 81 passes through a splitter 85, a switching amplifier circuit 86, and a trap circuit 87, and is transmitted to the television receiver 11.

The switching amplifier circuit 86 has a two-stage amplification degree, and the amplification degree is high when the signal 0 of the ant game 1 to the circuit 105 is "1", and the trap circuit 87 traps only when the signal k is "1" 42-. Determine the effect of J to the splitter 85 is input to the video detection circuit 88, and the I video (No. 75 is detected and input to the horizontal synchronization branch circuit 9o and the vertical synchronization separation circuit 91, and the horizontal synchronization I= and vertical synchronization (I) are detected, respectively. i5 is output to the counter circuit 98 and line counter circuit 99. In the line counter circuit 99, the vertical synchronization separation circuit 91
It is reset to 1 by the output of . Similar to encoder 3o, this reset signal is applied from the rising edge of vertical synchronization signal 1M
It is output at the Hth time. In addition, after the counter circuit 98 is reset by No. 48 r of the horizontal synchronization separation circuit 90, the stable I frequency (2,5175M) is output from the oscillation circuit 100.
HI > is counted, the horizontal synchronization fti interval is divided into exactly 160 equal parts, and the J counter output 102 is transmitted to the timing circuit 101 . Also, the output j of the counter circuit 98
p (160 frequency divided output) is input to the line counter circuit 99. This output p is 160 of the encoder 30 mentioned above.
The signal is similar to that of the frequency dividing circuit 57, and rises approximately at the center of the horizontal synchronization number 15 and the horizontal synchronization number 15, and the line counter circuit 99 counts this rise. Even if horizontal synchronization separation is not performed due to level compression in the horizontal retrace interval associated with scrambling processing, the counter circuit 98 can continue to maintain accurate timing by dividing the oscillation wave of the oscillation circuit 100 by 160. can. timing circuit 1
01 is transmitted from the counter circuit 98 and line counter circuit 99 by counter outputs 102 and 103 (8
The various signals j, Q, s and the timing output 104 direct all operations of the decoder 81. At this time, the timing circuit 101 is 28L~
Signal p of "1" between 239L and 32 from star 1
A signal S for the screen division is output to 11to, a signal 1d k is output at the time of the horizontal synchronizing signal of 16 and 17L, and a signal j is output during the horizontal retrace section of each signal synchronizing signal.

Next, while referring to the timing chart, perform (D) as described above.
, ([E), and l: will be explained in detail.

(D) Capture and analysis of key signals used for descrambling.

The data demodulation circuit 89 separates and captures the data signal (including the 4-1 signal) in the video signal detected by the video detection circuit 88 described above, and sends the data (a) to the storage processing circuit 93 via the data output 92. 1-Full demodulation circuit 89
Since the output signal is 12 bits including a start bit and a parity bit, this storage processing circuit 93
Excluding the start bit and parity bit, outputs the 18-bit key No. 1a r11010011J shown in FIG. 12. However, this demodulated 4/2 signal does not correspond to the scrambled state of the screen, and remains unchanged (and cannot be descrambled. For this reason, the processed output 9
4 is input to the code conversion circuit 95, and is converted into ``-code'' to become [1
, 0, 1, 1, 1, 0, 0, 1'', and this converted key signal corresponds to the scrambled screen. The 8-bit key signal converted into 2'-code is input to the shift register circuit 97, and the shift register circuit 97 outputs the converted key No. 16 one bit at a time for each input horn of No. ij S. I can do it.

(E) Removal of the key signal added to the horizontal synchronization signal.

As mentioned above, the horizontal synchronization signal of 16.171 has a data signal as shown in FIG.
Because of the issue, it may have a negative effect on the reproduced image.
This data signal must be removed within the decoder 81. Therefore, in the timing generation circuit 101, 16.1
It is between 11/IGO+-1 from the rising edge of the horizontal synchronizing signal according to the horizontal synchronizing signal of 71.
- Output to the wrap circuit 81. Using this signal k, the trap circuit 87 removes data No. 18 added to the horizontal synchronizing signals of 16L and 17L.

Since this signal is applied only to the horizontal synchronization signal to which the data signal is attached, it does not occur at the time of other horizontal synchronization signals. The part in parentheses on the left side of FIG. 16 shows the process in which the data signal is removed by the signal k. The waveform in the upper row of FIG. 16 shows the video signal before it enters the decoder 81, and the waveform in the lower row shows the video signal [a] output from the datater 87.

(F-) Level expansion of level compressed horizontal retrace section.

As mentioned above, since the encoder 30 compresses the level of the horizontal flyback section in the part that destroys the image, the f''-der 81 compresses the level of the horizontal retrace section in accordance with the analyzed key signal. Level-expand the horizontal retrace section of /, <1.
I have to. For this level expansion, the output of the shift 1 register circuit 97 and the timing generator 11j of the timing generation circuit 101 are used.
No.j.

It is acted upon by Ω.

(1) The No. 15 horizontal synchronization separation circuit 9o, which is always generated, outputs to the counter circuit 98 a horizontal synchronization signal (r) whose level is not compressed in the horizontal retrace interval (the signal r falls to γ at the rising edge of the ffi signal). The counter circuit 98 is reset when the signal r falls, divides the oscillation output of the oscillation circuit 100 by 160, and divides the oscillation output of the oscillation circuit 100 by 160,
A signal p whose frequency has been divided by 160 is sent to a nine circuit 99, and a counter output 102 is sent to a timing generation circuit 101). The line counter circuit 99 counts the line number corresponding to each horizontal scanning line by counting the signal p, and outputs the counter output 103 to the timing generation circuit 101. This timing generation circuit 101 always outputs a signal j, and 24/16 signals from the front 57716014 to the rear 57716014 centering on the falling timing of the signal j 14.
The period of 2'9/160 to 1 of 0 to 1 becomes tJrIJ, and this period of 29/160 to 1 becomes the level expansion period of 111], and the level compression period of 33/160 shown in Fig. 14. The time is shorter than H.

(2) A that occurs during level expansion: 1
In No. 1z and No. p, the timing generation circuit 101 is connected to the AND gate circuit 105 by the output of the line counter circuit 99.
This signal q is output from 28 to 239L.
It is a signal of "1" during the period, and rises or falls at the rising timing of the signal p. When this No. 15 Ω is other than "1", the level of the horizontal synchronization ffi signal is not expanded. No. 18 m indicates the descramble output from the shift register circuit 91, i. In the case of rOJ, the level is not expanded.This signal m
4, the timing generation circuit 101 outputs the signal S every 321-l.
One hit (every 32 days) of an 8-bit signal converted to the code like 1001J is output, and the signal m is converted to 321-1.
The output is maintained during the period of IJ.

(3) Horizontal synchronization signal level expansion (descrambling) As mentioned above, the AND gate circuit 105 receives the signal j.

Q and II+ are input, and when each signal j, Q, and m are all "1", the AND gate circuit 105 outputs a signal of "1" to the switching amplifier circuit 86, and the amplification degree of the switching amplifier circuit 86 is Increase. The switching amplifier circuit 86 operates for a period of 29/16 when the signal j is "1".
This period is the horizontal retrace interval, and the level-compressed horizontal periodic signal is amplified until the horizontal synchronization (I signal can be separated) in the television reception 1II, and the level is amplified until the signal i can be separated. The level is extended to the height.1st
The upper center of Figure 6 shows the level-compressed horizontal flyback section,
The center of the lower row shows a horizontal retrace section where the level is expanded and returned to the original state. In addition, as shown in the lower half of Figure 16, whisker-shaped valleys of 2/1601-1 are formed on both sides of the horizontal retrace section where level extension has finished, but these are located on the own level side. horizontal synchronization (it does not affect the separation of No. 1m, and it does not have any negative effect on the screen. Also, when No. 15l is rOJ on January 19th, the AND gate circuit 103 is switched No signal is output to the amplifier circuit 86, but when this signal M is [0], it is in the encoder 30 at a3 and the level compression of the horizontal retrace interval is not performed, so it is output as is to the television receiver 11. However, horizontal synchronization (Ei) can be separated.

According to the series of instructions mentioned above, the decoder 81 adds the key signal sent from the encoder 30, descrambles the level-compressed video signal in a predetermined horizontal retrace interval, removes the key signal, and then adds the key signal sent from the encoder 30 to the decoder 81. The video signal is restored so that the television receiver 11 can reproduce a normal image by level-expanding the horizontal flyback section.

Next, in Figures 13, 14, and 16 of the previous section, level compression, level expansion, and addition and removal of data I5 and I1 of the video signal are schematically explained, respectively. The video signal in the figure is different from the waveform modulated by the carrier wave in the embodiment, and the timing thereof is shown. Therefore, in reality, 1j shown in FIG.
Similarly, each video signal includes 1JR32i wave 50- (carry 17). Figure 17 (A) shows the waveform of the IF input signal that has not been processed, (1) shows the level compression of the horizontal retrace section and the I waveform, and Q\) shows the level expansion of the horizontal retrace section. The graph shows the waveforms obtained and their temporal comparison. In addition, in FIG. 18 (a), the encoder 30 converts the f-ta signal into a waveform added to the water H (7th period signal 8), and in FIG. 18 (b), the data signal is removed by the trap circuit 87 of the decoder 81. The waveform (
1\) shows the waveform of the timing at which the wrap circuit 87 is activated to 1, and also shows a temporal comparison thereof.

Since the present invention is configured as described above, (1) the scrambled video signal and the key signal for descrambling match; ! ㅂ, Eavesdropping cannot be done easily.

(2) Even if multiple systems employ the same type of scrambling method, by changing the code conversion means, there is no need to replace Ti between the systems, and the same type of terminal equipment can be used. Even if you use it, images cannot be received properly as is.

This is a scramble method with high confidentiality.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of a conventional CΔTV system; Figure 2 is a waveform diagram showing the principle of the scrambling method according to the present invention;
A waveform diagram of the horizontal synchronization signal with the number (= J added, Figure 4 is the number in Figure 3) An enlarged waveform diagram of the horizontal synchronization No. 15 part, Figure 5 shows the image destruction situation in the present invention. '!ll explanatory drawing, Fig. 6 is an explanatory drawing showing the division of screen destruction, Fig. 7 is a schematic diagram of an embodiment of the present invention applied to a CATV system, and Fig. 8 is an illustration of the above-mentioned encoder. Figure 9 is a block diagram showing the configuration inside the main box, Figure 10 is a block diagram showing the configuration of the decoder in the main box in detail, and Figure 11 is a random number for scrambling and its Fig. 12 is a timing chart showing the relationship between signal changes in each part of the encoder and video signals in one field, and Fig. 13 shows changes in signals in each part of the encoder between horizontal IiU period signals. A timing diagram showing the state in which the key (No. 5 is added), Figure 14 shows the changes in the (Li) of each part of the encoder between the horizontal synchronizing signals and the level-compressed video No. 15. The timing chart shown in Fig. 15 shows the changes in the signals of each part of j'-da in one field.J timing output-1-1 Fig. 16
Between 1 horizontal synchronization signal, A3T is applied, changes in each part of the decoder occur, and ice crumple occurs. Figure 17 shows the actual relationship between level compression and level expansion. Figure 18 is a waveform diagram showing the state of video signal No. 18 modulated by a carrier wave. Figure 18 is a waveform diagram showing the relationship between addition and removal of a data signal and the state of a video signal actually modulated by a carrier wave. be. 1... Rental, 2... Home, 3... Main line couple, 4... Main line amplifier, 5... Branch, 6... Branch cable, 7... Extension amplifier, 8...・Tap A)
, 9... branch cable, 10... main box,
11...TV receiver lL12...'nl-[-1-le box, 13...receiving amplifier, 14...source group, 15...demodulator, 1G...hide A disc player, 17...Video Cheapure” - Evening, 1
8... Stan A, 19... Modulation sending section, 20...
IF modulator circuit, 21... Scramble circuit, 22... Up 53-=l simbar circuit, 23... 1F modulator 1 circuit, 24... Up'' converter circuit, 25... ...Data transmitter/receiver, 26...Combiner, 27...Peripheral device, 28...Terminal device, 30...En''-da, 3
1... Main box, 42... Turnout, 43...
・Coupler, 44...Switching amplifier circuit, 45...
・Limiter circuit, 46... Video detection circuit, 47...
Mixing circuit, 48... Phase comparison circuit, 49... vCO
150...Goo 1~Circuit (switching circuit), 51
...Band pass filter, 52...Horizontal synchronization separation circuit, 53...Vertical synchronization separation circuit, 54...Phase comparison circuit, 55...■C0156...4 frequency division circuit, 57
...160 frequency dividing circuit, 58... line counter circuit, 59... random number generation circuit, 60... timing generation circuit, Gi, G2... counter output, 63... random number output, 64... . . . Storage processing circuit, 65 . . . Code conversion circuit, 66 . . . Processing output, 67 . . . Gino 1 to register circuit, 68 . 69...Storage circuit, 70.71...Timing output, 72...AND gate circuit, 73...AND gate circuit, 80...''inverter, 81...de''-da,
82..."control logic, 85...turnout,
86... Switching amplifier circuit, 87... Trap circuit, 88... Video detection circuit, 89... Y-54- evening demodulation circuit, 90... Horizontal synchronization separation circuit, 91...
Vertical synchronization separation circuit, 92...data output, 93...
Memory processing circuit, 94...Processing output, 95...'-code conversion circuit, 9G...Conversion output 1.97...Shift register circuit, 98...Counter circuit, 99...Line counter Circuit, 100... Oscillation circuit, 101...
Timing R raw circuit, 102, 103... Counter output, 104... Timing output horn, 105... AND gate circuit. Patent Applicant BuyAnia Co., Ltd. Agent Patent Attorney Nobu Kobashi Jundo Patent Attorney Susumu Toi

Claims (1)

[Claims] In addition to changing the modulation degree of a specific part of the television video signal from the original No. 15 modulation degree so that it cannot be viewed normally, it also causes descrambling in the horizontal synchronization signal of the television video signal. In the scramble of a television image to which a key signal is added and transmitted, a means is provided for converting the code of the key signal under certain conditions by setting the code of the key signal in advance. A method for transmitting a key signal for scrambling television images, which is characterized in that a key signal converted into a code is added to a horizontal synchronizing signal and transmitted.