JPS62287701A - Oscilation stop detection circuit - Google Patents

Abstract

PURPOSE:To detect the oscillation stop with simple circuit constitution employing mainly passive elements by detecting the oscillation stop by the logic coincidence of output signals of each differentiation circuit. CONSTITUTION:One of two inputs of an AND circuit 6 is at a high level and the other is at a low level at all times when the oscillation of an oscillation circuit to be supervised inputted to an input terminal IN is normal and then the logics of them differe from each other. When the oscillation of the oscillation circuit to be supervised is stopped, the level of the AND circuit 6 rises gradually by the charging of a capacitor C2 and reaches a high level in excess of the threshold value after a detection time T decided by a time constant comprising a capacitor C2 and a resistor R3 elapses. Thus, the oscillation stop is detected by a change in an output signal (e) of the AND circuit 6.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) The present invention uses a differentiating circuit to monitor the time of a binarized oscillation signal, thereby improving the performance of the monitored oscillation circuit. The present invention relates to an oscillation stop detection circuit that detects oscillation stop.

(Prior Art) As is well known, oscillation circuits are used in a wide range of fields such as switching power supplies and resolvers. Conventional.

For example, a circuit shown in FIG. 3 is known as an oscillation circuit of this type capable of detecting oscillation stoppage. That is, in the figure, 11 is an F/V converter (frequency/voltage converter), 12.13 is a comparator into which the signal from the F/V converter 11 is input, 14.
15 is a reference voltage source, 16 is an OR circuit, and different reference voltages from the reference voltage sources 14 and 15 are connected to the comparator 12.
．． 13, respectively.

The operation of this circuit is such that the output signal of the monitored oscillation circuit is F/V.
It is input to the converter 11 and converted into a voltage value proportional to the oscillation frequency, and when the voltage value becomes zero or deviates from predetermined allowable upper and lower limits, an OR circuit 16 is generated.
This is used to obtain oscillation abnormality signals such as oscillation stoppage.

(Problems to be Solved by the Invention) However, in such a circuit, the F/V converter 11 and the comparators 12, 13 . This requires a large number of active elements such as the reference voltage sources 14 and 15, has a complex circuit configuration, and has a large number of parts, resulting in high costs and a problem in that the reliability of the entire circuit is low.

The present invention was proposed to solve the above problems, and its purpose is to enable detection of oscillation stop with a simple circuit configuration mainly consisting of passive elements, thereby reducing costs and improving reliability. An object of the present invention is to provide an improved oscillation stop detection circuit (means for solving the problem). an inverting circuit, a first differentiating circuit for differentiating the oscillation signal, a second differentiating circuit for differentiating the output signal of the inverting circuit, and a logic match between the output signals of the first and second differentiating circuits. The present invention is characterized in that the differential circuit and the AND circuit can be constructed mainly from passive elements such as capacitors, resistors, and diodes.

(Operation) When the oscillation is normal, the binarized monitored oscillation signal has different signal level logic due to passing through the first and second differentiating circuits.

Also, even on a sunny day when oscillation has stopped, the output signal of one differential circuit is at a high level and the other is at a low level.
When the detection time determined by the time constant of the differentiating circuit has elapsed, the output signal of the differentiating circuit on the low level side changes to high level, so a detection signal for stopping oscillation can be obtained from the AND circuit.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a FET to which the oscillation output from a monitored oscillation circuit (not shown) is input to the gate via the input terminal IN, and its drain and source are connected via the power supply line L□ and resistor R1. and is connected to the ground line L2. Further, one end of the resistor R is connected to the input side of a Schmitt circuit 2 for waveform shaping, and the inverting circuit 3 is connected to the output side thereof.

Furthermore, a first differentiating circuit 4 consisting of a capacitor C and R2 is connected to the output side of the Schmitt circuit 2 between it and the power supply line L, and a capacitor C2 and a capacitor R2 are connected to the output side of the inverting circuit 3. A second differentiating circuit 5 consisting of R1
is connected.

Furthermore, a two-man power AND circuit 6 is connected to the output side of each differentiating circuit 4, 5. That is, this AND circuit 6 includes a diode D1 whose cathode is connected to one end of the capacitor C1, and a diode D2 which is connected in parallel with this diode D1 and whose cathode is connected to one end of the capacitor C2.
and resistors R,,R, connected in series between the power supply line L1 and the earth line L2, and the resistors R,,R,
The connection point is connected to the anodes of the diodes D□ and D2, and is also connected to the output terminal OUT via a Schmitt circuit 7 for waveform shaping.

Next, this operation will be explained with reference to the timing chart of FIG. Note that each waveform in FIG. 2 is a w4 measurement waveform at each point in FIG. 1 with the same alphabet. First, FET1.

When the monitored oscillation circuit continues normal oscillation operation, the oscillation waveform a is applied to the gate, causing it to turn on and off.
Repeat FF. Therefore, the output signal of the FETI is waveform-shaped by the Schmitt circuit 2, resulting in a square wave (binarized) signal as shown in b in FIG.

On the one hand, this signal S is input as is to the first differentiating circuit 4 and becomes the signal d, and on the other hand, after its logic is inverted by the inverting circuit 3, it is input to the second differentiating circuit 5 and becomes the signal C. Therefore, if the oscillation operation of the monitored oscillation circuit is normal, one of the two inputs of the AND circuit 6 will always be at a high level.
Since the other one is at a low level and the logic is different, the output signal e of the AND circuit 6 is at a positive logic and at a low level.

Now, suppose that the oscillation of the monitored oscillation circuit stops at time t in FIG. Although the level is low, the level gradually rises as capacitor C2 is charged, and capacitor c2
After the detection time T determined by the time constant of the resistor R1 has elapsed, the threshold value (ViH: resistor R
, , R,) and reaches a high level. So resistance R4? A voltage appears at the voltage dividing point of R5, that is, at the input side of the Schmitt circuit 7, and the output signal e of the AND circuit 6 becomes high level. Therefore, the stop of oscillation can be detected based on the change in the output signal e.

According to this embodiment, the detection time T from the stop of one oscillation to its detection can be freely changed by changing the values of the capacitors C and C2 and the resistors R2 and R1 that constitute each differentiating circuit 4 and 5. Because you can set it.

Theoretically, it is possible to cope with an unlimited number of frequencies of the supervisory oscillation signal.

(Effects of the Invention) As detailed above, the present invention detects the stop of oscillation by matching the logic of the output signals of each differentiating circuit, and uses a capacitor and a resistor as the differentiating circuit, and a diode and a resistor as the AND circuit. Since it can be realized with a circuit configuration mainly composed of passive elements such as resistors, it is possible to provide a highly reliable oscillation stop detection circuit at a small cost.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
Timing chart showing waveforms at each point in the figure, 3rd
The figure is a block diagram of a conventional oscillation abnormality detection circuit. 1... FET 2, 7... Schmitt circuit 3... Inverting circuit 4, 5... Differentiating circuit 6.
・・AND circuit C1, C, ・・Capacitor D1
．． D...Diode R~R9...Resistor I
N...Input terminal OUT...Output terminal L1
...Power line L2...Earth line Patent applicant Fuji Electric Co., Ltd. (1 other person)

Claims (1)

[Claims] an inversion circuit into which a binarized oscillation signal to be monitored is input; a first differentiation circuit into which the oscillation signal is differentiated; and a second differentiation circuit into which the output signal of the inversion circuit is differentiated;
An oscillation stop detection circuit comprising: an AND circuit that detects the stop of oscillation based on a logic match between the output signals of the first and second differentiating circuits.