JPS62286263A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62286263A
JPS62286263A JP13081486A JP13081486A JPS62286263A JP S62286263 A JPS62286263 A JP S62286263A JP 13081486 A JP13081486 A JP 13081486A JP 13081486 A JP13081486 A JP 13081486A JP S62286263 A JPS62286263 A JP S62286263A
Authority
JP
Japan
Prior art keywords
semiconductor
elements
bonding
package
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13081486A
Other languages
Japanese (ja)
Inventor
Mineo Hayashi
林　峰雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP13081486A priority Critical patent/JPS62286263A/en
Publication of JPS62286263A publication Critical patent/JPS62286263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a compact semiconductor device, by using one set of upper and lower circuit arrangements, fixing elements on both front and rear sides of a conducting plate, performing interconnection, and containing a plurality of the semiconductor elements in one package. CONSTITUTION:On both surfaces of an island part 11 of a lead frame, a semiconductor element 13 and a semiconductor element 13', whose circuit arrangement is the upside-down arrangement of the element 13, are mounted. Inner leads 12 and 12' and the semiconductor elements 13 and 13' are connected with thin metal wires 14 and 14'. The bonding pads of the semiconductor elements are positioned at the same positions for the upper and lower sides. Therefore, bonding can be readily performed to the same leads. The occupying area of the semiconductor-element mounting part can be reduced to one half by performing bonding except for the element selecting terminals.

Description

【発明の詳細な説明】 １　発明の詳細な説明 〔産業上の利用分野〕 本発明は複数の半導体素子を一つのパッケージ内に収納
した半導体装置に関する。Detailed Description of the Invention 1. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device in which a plurality of semiconductor elements are housed in one package.

〔従来の技術〕[Conventional technology]

従来、複数個の半導体素子を同一バフケージ上に収納し
ようとする際、その占有面積が増加する。Conventionally, when a plurality of semiconductor devices are housed on the same buff cage, the area occupied by the same buff cage increases.

特に、その増加分はある限られた小型パッケージに大型
の素子を実装しようとする場合に重要な問題となる。In particular, the increase becomes an important problem when trying to mount a large element in a limited small package.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の実装方法では例えば、記憶装置の様に同
−ｆｊ＆能を有する二個の素子を配置し、各々の素子の
選択は、各々に選択信号を加えて、各素子を選択しよう
とする場合など素子の占有面積やパッケージの容積等が
限定すればそれらの収態は非常に困難となる。In the conventional mounting method described above, for example, two elements having the same -fj& function are arranged like a memory device, and each element is selected by applying a selection signal to each element. If the area occupied by the device, the volume of the package, etc. are limited, it becomes very difficult to accommodate them.

そこで第２図に示すように導電板の両側に素子をそれぞ
れ固着することが考えられるが同一素子を用いるため裏
面に固着きれた素子は表面の素子と異なった端子に配線
を行なわなければならず不具合を生ずることになる。Therefore, it is possible to fix elements on both sides of the conductive plate as shown in Figure 2, but since the same elements are used, the elements that are stuck on the back side must be wired to different terminals from the elements on the front side. This will cause problems.

本発明は上記欠点を除き、半導体素子載置部の面積を増
加させることなくかつ端子の数も増力口させることなく
複数個の半導体素子を一つのパッケージ内に収納した半
導体装置を提供するものである。The present invention eliminates the above drawbacks and provides a semiconductor device in which a plurality of semiconductor elements are housed in one package without increasing the area of the semiconductor element mounting portion and without increasing the number of terminals. be.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体基板上に形成された回路配置を有する半
導体素子において上記半導体素子と上記回路配置を裏返
しにした回路配置を有する半導体素子を２４′を板もし
くは導電膜を有する絶縁板の両側に上記の二種の半導体
素子を固着し、結線し、一つのパッケージ内に収納した
ことを特徴としている。In a semiconductor element having a circuit arrangement formed on a semiconductor substrate of the present invention, the semiconductor element having a circuit arrangement in which the above semiconductor element and the above circuit arrangement are reversed is placed 24' on both sides of a plate or an insulating plate having a conductive film. It is characterized by two types of semiconductor elements being fixed together, wired together, and housed in one package.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の平面図（（ａ）図）及び（
ａ）図のＡ−Ａ’　断面図（（ｂ）図）である。FIG. 1 is a plan view ((a)) of an embodiment of the present invention and (
It is an AA' sectional view (figure (b)) of figure a).

リードフレームのアイランド部１１の両面に半導体素子
１３、回路配置を裏返しした半導体素子１３′をマクン
トし、金属紙＋１１１！１４．１４’でそれぞれ内部リ
ード１２．１２’と半導体素子１３．１３’とを接続す
る。図に示すように半導体素子のポンディングパッドが
表裏・同一の位置にくるために・容易に同一のり一ドに
ボンディングが可能となり素子選択の端子を除いてボン
ディングを行なうことにより半導体素子載置部の占有面
積を半減することができる。The semiconductor element 13 and the semiconductor element 13' with the circuit arrangement reversed are mounted on both sides of the island portion 11 of the lead frame, and the internal leads 12, 12' and the semiconductor element 13, 13' are formed with metal paper +111!14.14', respectively. Connect. As shown in the figure, since the bonding pads of the semiconductor element are at the same position on the front and back, it is possible to easily bond to the same bonding pad, and by performing bonding excluding the element selection terminal, the semiconductor element mounting area The area occupied can be halved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、回路配置を表裏−組を用
い導電板の両面に固着させ、配線することにより半導体
素子ｄ［部の面積を増加させることなく、複数個の半導
体素子を一つのパッケージ内に収納できるので小型の半
導体装置が得られる。As explained above, the present invention fixes the circuit layout to both sides of the conductive plate using front and back sets and wires it, thereby combining multiple semiconductor elements into one without increasing the area of the semiconductor element d[. Since it can be housed in a package, a compact semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（１ｋ）は本発明の半導体装置の一笑施・列の平
面図、（ｂ）はそのＡ−Ａ　　斯面図和葎ｉ卓、（Ｃ）
は二つの素子平面図、第２図は従来例図である。 １１・−・・−・アイランド部、１２・・・・・・内部
リード、１３．１３’・・・・・・半導体素子、１４．
１４’・・・・・・金属細線。 代理人　弁理士　　内　原　　　晋−パ：＼（ｃｌ、）
ｆｉｂ） 粂　１７FIG. 1 (1k) is a plan view of a semiconductor device according to the present invention in one row, (b) is an A-A side view thereof, (C)
2 is a plan view of two elements, and FIG. 2 is a diagram of a conventional example. 11...Island portion, 12...Internal lead, 13.13'...Semiconductor element, 14.
14'・・・Thin metal wire. Agent: Susumu Uchihara, Patent Attorney: ＼(cl,)
fib) Kume 17

Claims (1)

【特許請求の範囲】[Claims] 第１の回路配置を有する半導体基板と上記第１の回路配
置を裏返しにした第２の回路配置を有する第２の半導体
基板とを導電板もしくは導電膜を有する絶縁板の両面に
固着して結線し、一つのパッケージ内に収納したことを
特徴とする半導体装置。A semiconductor substrate having a first circuit arrangement and a second semiconductor substrate having a second circuit arrangement obtained by turning the first circuit arrangement upside down are bonded to both sides of a conductive plate or an insulating plate having a conductive film for wiring. A semiconductor device characterized in that: and is housed in one package.
JP13081486A 1986-06-04 1986-06-04 Semiconductor device Pending JPS62286263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13081486A JPS62286263A (en) 1986-06-04 1986-06-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13081486A JPS62286263A (en) 1986-06-04 1986-06-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62286263A true JPS62286263A (en) 1987-12-12

Family

ID=15043333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13081486A Pending JPS62286263A (en) 1986-06-04 1986-06-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62286263A (en)

Similar Documents

Publication Publication Date Title
US6271582B1 (en) Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US6344976B1 (en) Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die
US5473514A (en) Semiconductor device having an interconnecting circuit board
KR100328906B1 (en) Method and device for joining leads inside lead-on chip of leadframe
JPH0550134B2 (en)
JPH06151685A (en) Mcp semiconductor device
KR20010023575A (en) Electrical interface to integrated device having high density i/o count
JP2568748B2 (en) Semiconductor device
JPH04307943A (en) Semiconductor device
JPS63296292A (en) Semiconductor device
US6052289A (en) Interdigitated leads-over-chip lead frame for supporting an integrated circuit die
JPH10189653A (en) Semiconductor element and circuit module having this semiconductor element
JPH0274046A (en) Semiconductor integrated circuit device
JPS622628A (en) Semiconductor device
JPS62286263A (en) Semiconductor device
JP3942495B2 (en) Semiconductor device
JPH1012800A (en) Connecting device for semiconductor element
JPH03109760A (en) Semiconductor device
JPH04246851A (en) Semiconductor integrated circuit of master slice layout device
JPH06350025A (en) Semiconductor device
JP2587722Y2 (en) Semiconductor device
JPH04267361A (en) Leadless chip carrier
JP2949951B2 (en) Semiconductor device
KR100206975B1 (en) Semiconductor package
JP2581278B2 (en) Semiconductor device