JPS62285431A - Semiconductor device and manufacture of the same - Google Patents
Semiconductor device and manufacture of the sameInfo
- Publication number
- JPS62285431A JPS62285431A JP12861586A JP12861586A JPS62285431A JP S62285431 A JPS62285431 A JP S62285431A JP 12861586 A JP12861586 A JP 12861586A JP 12861586 A JP12861586 A JP 12861586A JP S62285431 A JPS62285431 A JP S62285431A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- polycrystalline silicon
- film
- films
- side walls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
産業上の利用分野
本発明は高密度化が可能で、プリント基板上に高密度に
実装することができる半導体装置およびその製造方法を
提供するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention Industrial Application Field The present invention provides a semiconductor device that can be increased in density and can be mounted on a printed circuit board with high density, and a method for manufacturing the same. It is something.
従来の技術
従来半導体装置には第４図に示すように、外部配線との
接続のため半導体装置の周辺にボンデイングパソド２１
を形成しである。かかるボンディングパッドは一般に半
導体装置の内部回路２２と同一半導体基板２ｏ上に形成
され、接続を容易にするため大きく、例えば−辺ａは１
００ミクロン程度の大きさを有し、かつ外部配線接続時
の内部回路の破壊を防止するため、内部回路との間隔す
を数十ミクロンとる必要があった。2. Description of the Related Art As shown in FIG. 4, a conventional semiconductor device is provided with a bonding pad 21 around the semiconductor device for connection with external wiring.
It is formed. Such bonding pads are generally formed on the same semiconductor substrate 2o as the internal circuit 22 of the semiconductor device, and are large to facilitate connection, e.g.
It has a size of approximately 0.00 microns, and in order to prevent damage to the internal circuit when connecting external wiring, it is necessary to provide a distance of several tens of microns between the internal circuit and the internal circuit.
また外部配線２３と前記半導体基板２Ｑは間隔をあけて
おき、金あるいはアルミニウム等の導体線２４で外部配
線２３とポンプイングツくラドを接続する必要があった
。Further, it is necessary to leave a space between the external wiring 23 and the semiconductor substrate 2Q, and to connect the external wiring 23 and the pumping pad with a conductor wire 24 made of gold, aluminum, or the like.
発明が解決しようとする問題点
従来法によるボンディングパッドを形成した半導体装置
では、内部回路とボンディング・くソドとの間隔および
ボンディングパッド自身の大きさのため、半導体装置の
高密度化の妨げとなっていた。Problems to be Solved by the Invention In semiconductor devices in which bonding pads are formed using conventional methods, the distance between the internal circuit and the bonding pad and the size of the bonding pads themselves impede higher density of the semiconductor device. was.
問題点を解決するだめの手段
上記問題点を解決するため半導体装置のスクライブライ
ンに接して選択的に開孔部を形成し、前記開孔部に二酸
化硅素膜および多結晶硅素膜を形成した後、スクライブ
ラインを食刻し、前記多結晶硅素膜の側壁を露出し、前
記多結晶硅素膜側壁上に金属膜を形成することにより前
記半導体装置のボンディングパッドを形成する。Means for solving the problem In order to solve the above problem, after selectively forming an opening in contact with the scribe line of the semiconductor device and forming a silicon dioxide film and a polycrystalline silicon film in the opening, , etching scribe lines to expose sidewalls of the polycrystalline silicon film, and forming a metal film on the sidewalls of the polycrystalline silicon film to form bonding pads for the semiconductor device.
作 用
本発明は、半導体装置の外部配線との接続用ボンディン
グパッドを内部回路と異なる半導体基板面に形成するこ
とにより高集積化をはかるとともに製造容易なボンディ
ングパッドを形成するものである。Function The present invention aims at high integration and forms bonding pads that are easy to manufacture by forming bonding pads for connection with external wiring of a semiconductor device on a surface of a semiconductor substrate different from that of an internal circuit.
実施例 本発明の一実施例を第１図にもとづいて説明する。Example An embodiment of the present invention will be described based on FIG.
半導体基板１上のスクライプレーン２に接して、選択的
に開孔部３を形成する（第１図（へ）。次に開孔部側壁
および底面に二酸化硅素膜など絶縁膜４を形成する。次
に開孔部３に多結晶硅素膜６を形成し、開孔部３を埋め
るＧ０次にアルミニウムなどの金属配線６により半導体
装置内の回路と、前記埋め込み多結晶硅素膜表面との接
続配線６を形成する（Ｑ。An opening 3 is selectively formed in contact with the scribe plane 2 on the semiconductor substrate 1 (FIG. 1). Next, an insulating film 4 such as a silicon dioxide film is formed on the side wall and bottom of the opening. Next, a polycrystalline silicon film 6 is formed in the opening 3, and the opening 3 is filled with G0.Then, a metal wiring 6 such as aluminum is used to connect the circuit inside the semiconductor device to the surface of the buried polycrystalline silicon film. Form wiring 6 (Q.
次に保護膜７を形成後、前記スクライブライン部８の半
導体基板８を前記埋め込み多結晶硅素膜より深く食刻し
、前記開孔部側壁に形成した前記絶縁膜を食刻除去し、
前記多結晶硅素膜側壁を露出し、ボンディングパッド９
とする。前記多結晶硅素膜からなるボンディングパッド
９と外部金属配線との接続をより確実にするため、前記
多結晶硅素膜側壁を露出後、全面に高融点金属膜を形成
し、熱処理を行ない前記多結晶硅素膜と反応させシリサ
イド層１４を形成するｑ０次にシリサイド層１４以外の
前記高融点金属膜を除去してボンディングパッドを形成
してもよい。Next, after forming the protective film 7, the semiconductor substrate 8 in the scribe line part 8 is etched deeper than the buried polycrystalline silicon film, and the insulating film formed on the side wall of the opening part is etched away;
The sidewalls of the polycrystalline silicon film are exposed, and bonding pads 9 are formed.
shall be. In order to make the connection between the bonding pad 9 made of the polycrystalline silicon film and the external metal wiring more reliable, after exposing the sidewalls of the polycrystalline silicon film, a high melting point metal film is formed on the entire surface, and a heat treatment is performed to bond the polycrystalline silicon film. After reacting with the silicon film to form the silicide layer 14, the high melting point metal film other than the silicide layer 14 may be removed to form a bonding pad.
本発明の第二の実施例を第２図にもとすいて説明する。A second embodiment of the present invention will be described with reference to FIG.
半導体基板１上に形成した半導体装置周辺にスクライブ
ライン１３と接して開孔部１０を形成する。次に前記第
１の開孔部に二酸化硅素膜などの絶縁物１１を埋め込み
形成する。次に前記埋め込み絶縁物に選択的に第２の開
孔部を形成する。前記第２の開孔部に多結晶硅素膜ある
いは金属膜などの導体膜１２を埋め込み形成する。次に
前記導体膜１２と半導体装置内部回路との接続配線６を
第１の実施例と同様に形成する。次にスクライブライン
を食刻し、続いて前記導体膜の側壁の前記絶縁物を食刻
除去して食刻部１３を形成し、前記導体膜側壁を露出し
、ボンディングパッドとする。An opening 10 is formed around a semiconductor device formed on a semiconductor substrate 1 in contact with a scribe line 13. Next, an insulator 11 such as a silicon dioxide film is embedded in the first opening. Next, a second opening is selectively formed in the buried insulator. A conductive film 12 such as a polycrystalline silicon film or a metal film is embedded in the second opening. Next, the connection wiring 6 between the conductive film 12 and the internal circuit of the semiconductor device is formed in the same manner as in the first embodiment. Next, a scribe line is etched, and then the insulator on the side wall of the conductor film is etched away to form an etched portion 13, and the side wall of the conductor film is exposed and used as a bonding pad.
なお上記実施例において、開孔部へ埋め込む導体膜１２
を内部回路の配線および内部回路とボンディングパッド
の接続配線と同時に形成してもよい。Note that in the above embodiment, the conductor film 12 embedded in the opening
may be formed simultaneously with the internal circuit wiring and the connection wiring between the internal circuit and the bonding pad.
また前記ボンディングパッドは内部回路と同時に形成し
ても、内部回路形成後形成してもよい。Further, the bonding pad may be formed simultaneously with the internal circuit or after the internal circuit is formed.
第３図にもとづき本発明の第２の実施例による半導体装
置の基板１と外部配線基板３１との接続を説明する。前
記半導体基板１の側壁に形成したボンディングパッド９
と対向する位置に外部配線３２の接続部３３を形成した
外部配線基板３１を準備し、第３図の矢印３４に示す方
向に合体させ、前記半導体装置のボンディングパッド９
と外部配線３３を接続する。The connection between the substrate 1 and the external wiring board 31 of the semiconductor device according to the second embodiment of the present invention will be explained based on FIG. A bonding pad 9 formed on the side wall of the semiconductor substrate 1
An external wiring board 31 having a connecting portion 33 of an external wiring 32 formed at a position facing the external wiring board 31 is prepared, and is assembled in the direction shown by the arrow 34 in FIG.
and external wiring 33 are connected.
発明の効果
本発明の方法による半導体装置は、内部回路形成面と異
なる半導体基板面、側面にボンディングパッドを形成す
るため高密度の半導体装置が形成できる。Effects of the Invention In the semiconductor device according to the method of the present invention, a high-density semiconductor device can be formed because bonding pads are formed on a side surface of the semiconductor substrate that is different from the surface on which internal circuits are formed.
本発明の製造方法によれば内部回路形成面に開孔部を形
成し、前記開孔部に導体膜を埋め込み、ドとする。この
ように、容易に前記回路と異なる面に前記パッドを形成
することができる。また前記導体膜周辺に絶縁物を形成
しておくため、スクライブラインの食刻および半導体装
置間の分割も容易に行なうことができる。According to the manufacturing method of the present invention, an opening is formed on the internal circuit forming surface, and a conductive film is embedded in the opening to form a dome. In this way, the pad can be easily formed on a different surface from the circuit. Further, since an insulator is formed around the conductor film, etching of scribe lines and division between semiconductor devices can be easily performed.
また外部配線との接続においても接続端子を側壁に形成
した外部配線基板と直接接続させることにより従来例の
ような導体線を使用することなく接続できるため高密度
に実装することができるという特徴がある。In addition, when connecting to external wiring, by directly connecting the connecting terminal to the external wiring board formed on the side wall, it is possible to connect without using conductor wires as in the conventional example, so high-density packaging is possible. be.
第１図は本発明の一実施例のボンディングパッドの製造
を説明するだめの工程断面斜視図、第２図は本発明の第
二の実施例の同パッドの製造工程断面斜視図、第３図は
本発明による半導体装置と外部配線接続を説明するため
の概略図、第４図は従来の半導体装置の外部配線接続を
説明するだめの概略図である。
１・・・・・・半導体基板、２・・・・・・スクライプ
レーン、３・・・・・・開孔部、４・・・・・・絶縁膜
、６・・・・・・多結晶硅素膜、６・・・・・・金属配
線、９・・・・・・ボンディングパッド。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名４
／−一一手再体基板
第１図
３−開孔部
（’Ａ）
（Ｂ）
第２図FIG. 1 is a cross-sectional perspective view of a process for explaining the manufacturing process of a bonding pad according to an embodiment of the present invention, FIG. 2 is a cross-sectional perspective view of a manufacturing process of the same pad according to a second embodiment of the present invention, and FIG. 4 is a schematic diagram for explaining a semiconductor device according to the present invention and external wiring connections, and FIG. 4 is a schematic diagram for explaining external wiring connections of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Screen plane, 3...Opening part, 4...Insulating film, 6...Multiple Crystal silicon film, 6...metal wiring, 9...bonding pad. Name of agent: Patent attorney Toshio Nakao and 1 other person4
/-11 hand reassembled board Fig. 1 3- Opening part ('A) (B) Fig. 2
Claims (3)
導体集積回路を形成した半導体基板表面と異なる面に形
成したことを特徴とする半導体装置。(1) A semiconductor device characterized in that a bonding pad of a semiconductor integrated circuit is formed on a surface different from the surface of a semiconductor substrate on which the semiconductor integrated circuit is formed.
開孔部を形成する工程と、前記開孔部に絶縁膜および多
結晶硅素膜を形成する工程と、前記開孔部に接するスク
ライブラインを食刻する工程と、前記絶縁膜を食刻し、
前記多結晶硅素膜の側壁を露出する工程とを含むことを
特徴とする半導体装置の製造方法。(2) A step of selectively forming an opening in a semiconductor substrate in contact with a scribe line, a step of forming an insulating film and a polycrystalline silicon film in the opening, and a step of forming an opening in contact with the scribe line in the opening. etching the insulating film;
A method of manufacturing a semiconductor device, comprising: exposing a sidewall of the polycrystalline silicon film.
を形成する工程と、前記多結晶硅素膜と前記高融点金属
膜を反応させシリサイド膜を形成後、前記多結晶硅素膜
上以外の高融点金属膜を除去する工程を含むことを特徴
とする特許請求の範囲第２項に記載の半導体装置の製造
方法。(3) After exposing the side walls of the polycrystalline silicon film, forming a high melting point metal film on the entire surface; and after forming a silicide film by reacting the polycrystalline silicon film and the high melting point metal film, and then forming a silicide film on the polycrystalline silicon film. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of removing a high melting point metal film other than the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12861586A JPS62285431A (en) | 1986-06-03 | 1986-06-03 | Semiconductor device and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12861586A JPS62285431A (en) | 1986-06-03 | 1986-06-03 | Semiconductor device and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62285431A true JPS62285431A (en) | 1987-12-11 |
Family
ID=14989166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12861586A Pending JPS62285431A (en) | 1986-06-03 | 1986-06-03 | Semiconductor device and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62285431A (en) |
-
1986
- 1986-06-03 JP JP12861586A patent/JPS62285431A/en active Pending
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