JPS6228515B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device.
The present invention relates to a static semiconductor memory device having a static memory cell made up of transistors.

(2) Background of the Technology Generally, in the above-mentioned static type semiconductor memory device, one row of memory cells is connected between one word line and one hold line, and the memory state of each memory cell, that is, the flip-flop state is determined. To hold, a hold current flows from the word line through the memory cell to the hold line. Such word line selection is performed by pushing up the word line potential using a word driver. In this case, since the word driver is an emitter follower, it is possible to change the word line from a non-selected state to a selected state. The transition time, ie, the rise time of the word line, is short. On the other hand, the change time of the word line from the selected state to the non-selected state, that is, the fall time of the word line, depends on the amount of charge accumulated in the parasitic capacitance of the word line and the magnitude of the hold current.
In particular, in a PNPN memory cell in which NPN transistors are cross-coupled with a PNP transistor as a load, the hold current can be reduced, which is useful for increasing capacity. However, recent semiconductor memory devices have become larger in capacity and have lower power consumption, and the magnitude of the hold current has also become smaller, so the fall time of a word line tends to become longer. Therefore, in order to obtain high switching speed, it is important to shorten the fall time of the word line, that is, the recovery time.

(3) Prior art and problems In order to speed up the fall time of the selected word line, a discharge current is intensively drawn from the selected word line, and therefore the above-mentioned discharge current is drawn in addition to the normal hold current. It is already known that this discharge current is maintained for a certain period of time, thereby rapidly drawing out the charge from the selected word line (see: Japanese Patent Application No. 1973-
No. 110720). On the other hand, in a half-selected memory cell connected to a selected word line and an unselected bit line, the potential of the emitter of the detection transistor, that is, the unselected bit line, is raised to prevent erroneous writing to the half-selected memory cell. is prevented. As a result, the emitter of the detection transistor of the half-selected memory cell acts as a collector, and a phenomenon occurs in which part of the discharge current described above is shunted from the unselected bit line through the half-selected memory cell. Note that this current is called a sink current. Moreover, since there are many half-selected memories connected to the word line, in the end, even though the above-mentioned discharge current was adopted,
Due to the presence of sink current, high switching speed cannot be expected.

The magnitude of the sink current described above depends on the inverse β (current amplification factor) of the transistor. That is, if the inverse β is large, the sink current increases and the word line current decreases, resulting in a decrease in switching speed and the result that the circuit is wasted. Conversely, if the inverse β is small, the sink current decreases and the word line current increases, which tends to improve the switching speed, but the word line load becomes excessive and the selected word line level decreases accordingly. In other words, inverse β is inconvenient whether it is large or small. Note that the inverse β here refers to β when the emitter of the transistor acts as a collector, and is approximately proportional to β.

Focusing on the dependence of the magnitude of the sink current on the magnitude of the inverse .beta., it has already been proposed to change the above-mentioned discharge current value in accordance with the inverse .beta. (see Japanese Patent Application No. 155100/1982).

However, as mentioned above, if the word line potential amplitude is reduced by changing the discharge current value according to the inverse β, high-speed reading becomes possible, but the write current required for high-speed writing is shunted to non-selected memory cells. There is a problem.

(4) Purpose of the Invention The purpose of the present invention is to change the potential of an unselected word line in accordance with the sink current by a half-selected memory cell in a selected row, that is, to make the unselected word line potential follow the selected word line potential. Based on the concept, the purpose is to ensure a minimum word line potential amplitude to prevent the write current from being shunted to unselected memory cells, thereby solving the problems in the conventional type described above.

(5) Structure of the Invention In order to achieve the above-mentioned object, the present invention includes a plurality of memory cells arranged in a matrix, a word line connected to each row of the memory cells, and selecting the word line. and a constant discharge current source that draws a discharge current from the selected word line, a dummy cell having a structure similar to that of the memory cell to which a predetermined bias voltage is applied, and the dummy cell and means for changing the drive capability of each of the word drivers according to the magnitude of the sink current to the word driver, thereby causing the change characteristics of the unselected word line potential to follow the change characteristics of the selected word line potential. A semiconductor memory device is provided.

(6) Embodiments of the Invention The present invention will be explained below with reference to the drawings in comparison with a conventional type.

FIG. 1 is a block circuit diagram of a conventional static type semiconductor memory device. In FIG. 1, memory cells MC ₀₀ , MC ₀₁ , ......, MC _o-1 , _o-1 are arranged in a matrix, and the memory cell arrays in the 1st row, . Each word line W ₀ ,...
..., W _o-1 and each hold line H ₀ , ......, H _o-1 are connected. Also, the first column, the second column,...
..., in the memory cell array of the n-th column, each bit line pair B ₀ , ₀ ; B ₁ , ₁ ; ......; B _o-1 , _o
-1 is connected. In each memory cell, in order to hold the memory state (flip-flop state) of the memory cell, a hold current source I _H0 , ......, I H , _o is connected to each hold line H ₀ , ......, _{H o-1} . _-1 is connected.

Each word line W ₀ , ......, W _o-1 is selected by the word driver D ₀ , ......, D _o-1 selected by the word decoder WD ₀ , ......, WD _o . This is done by increasing the potential of W ₀ , ......, W _o-1 , but the word drivers D ₀ , ...
..., D _o-1 is an emitter follower, so the word line potential rises quickly. On the other hand, in order to speed up the fall time of the word line potential, that is, the time when the word line changes from a selected state to a non-selected state, the elements T ₁₀ ,
......, T ₁ , _o-1 ; R ₁₀ , ......, R ₁ , _o-1 ; C ₀ ,
………, C _o-1 ; T ₂₀ , ………, T ₂ , _o-1 ; R ₂₀ ,…
..., R ₂ , _o-1 are connected to the word line terminations. In detail, T ₁₀ , ......, T ₁ , _o-1 are emitter follower transistors that are switched by the potentials of the word lines W ₀ , ......, W _o-1 ;
Resistor R ₁₀ ,......, R ₁ , _o-1 and capacitor C ₁₀ ,...
..., C ₁ , _o-1 is the transistor T ₁₀ , ......,
A time constant circuit is formed to delay the output of T ₁ and _o-1 . Transistor T ₂₀ , ......, T ₂ , _o-1
is switched by each time constant circuit,
Connected to common hold current source △I _H.
That is, the transistors T ₂₀ , ......, T ₂ , _o-1
constitutes a current switch for the hold current source ΔI _H , and therefore any one of the transistors T ₂₀ , . . . , T ₂ , _o-1 is turned on.
In other words, _in addition to the normal _hold currents _{I H0} , . becomes faster.

In such a configuration, for example, when the word line W ₀ changes from the selected state to the non-selected state, the potential of the word line W ₀ is changed to the transistor T ₁₀ , the resistor R ₁₀ that constitutes the delay circuit, and the capacitor C ₀
Since the discharge current ΔI _H is applied to the hold current I _H0 for a predetermined period _of time, the potential of the word line W ₀ falls more quickly.

In FIG. 1, the bias current source I _BS has resistors R ₁₀ , . . . , R ₁ , _o-1 and R ₂₀ , . . . , R ₂ ,
Together with _o-1 , this determines the base potential of the transistors T ₂₀ , . . . , T ₂ , _o-1 .

On the other hand, the bit line clamp circuits BCL ₀ , BCL ₁ ,...
..., when the internal transistor pair turns on, BCL _o-1 pushes the potential of the unselected bit line to a high potential, thereby causing the unselected memory cell, especially, Erroneous writing to half-selected memory cells is prevented. Note that Y ₀ ,
Y ₁ , . . . , Y _o-1 are column selection signals, and D is write data.

Next, the sink current in the half-selected memory cell will be explained with reference to FIG. In FIG. 2, memory cell C ₀₀ is the same as the other memory cells, but with PNP transistors T ₁ , T ₂ , and PNP transistors as loads.
and detection NPN transistors T ₃ and T ₄ forming a flip-flop. These transistors T ₃ and T ₄ are incorporated as multi-emitter transistors, such as transistors
Among the multi-emitters of _T3 , the emitter connected to the bit line _B0 is designated as E _S , and the emitter connected to the hold line _H0 is designated as _EH . Note that transistors surrounded by circles are in an on state. In such a memory cell _C00 , when the potential of the emitter E _S becomes higher than the potential of the emitter E _H , the emitter E _S acts as a collector, and therefore, as shown by the dotted line, the potential i changes from the bit line _B0 . It flows into the hold line _H0 via the emitter _EH . This phenomenon in which the potential of the emitter E _S becomes higher than the potential of the emitter E _H occurs when the unselected bit line potential is applied to the bit line clamp circuits BCL ₀ , BCL ₁ , ..., BCL _o-1 shown in Figure 1. Occurs when it is pushed up. i.e. word line
When W ₀ and bit line B ₀ , ₀ are selected,
The above phenomenon occurs in the memory cells connected to the selected word line W ₀ , that is, the half-selected memory cells C ₀₁ , . . . , C ₀ , _o-1 . Such a current i
is called a sink current, and all but one memory cell selected for the selected word line are half-selected memory cells, and the hold current I _H0 +△I _H added to the discharge current △I _H in Fig. 1 is a non-selected memory cell. Since the current is shunted to the selected bit line as a sink current, high switching speed cannot be expected.

By the way, focusing on the fact that the magnitude of the sink current mentioned above depends on the inverse β of the transistor, it has been proposed to change the discharge current ΔI _H according to the inverse β (reference: Japanese Patent Application No. 56-155100) ). for example,
The discharge current ΔI H is increased when the inverse β is large and therefore the sink current is large, while the discharge current ΔI _H is decreased when the inverse β is small and the sink current is _small .

However, as mentioned above, the discharge current △I _H
If the word line potential amplitude, that is, the difference between the selected word line potential and the unselected word line potential, becomes smaller by changing the Divert.

In the present invention, when the selected word line potential changes due to a change in discharge current ΔI _H , the non-selected word line potential is also changed. For example, when the selected word line potential decreases, the unselected word line potential also decreases, thereby ensuring the minimum value of the word line potential amplitude and preventing the write current from being shunted to unselected memory cells. .

FIG. 3 is a circuit diagram showing a semiconductor memory device as an embodiment of the present invention. However, only necessary parts are extracted and illustrated. In FIG. 3, a word decoder, for example WD ₀ , receives address signals A ₀ ,
A ₁ , ......, A _l-1 (2 ^l = n) are supplied to the gates of the transistors T ₃₀ , T ₃₁ , ......, T ₃ , _l-1 ,
It is composed of a transistor TR to which _a reference voltage V _R is applied to its gate, resistors R ₃₁ and R ₃₂ , and a transistor _TC . Here, the transistor T _C and the resistor R ₃₂ act as a constant current source I _C , and therefore each transistor T ₃₀ , T ₃₁ , ......, T ₃ , _l-1 , T _R acts as a constant current source I A current switch is configured for _C.

For example, the selected state of word line W ₀ corresponds to when the potentials of address signals A ₀ , A ₁ , . . . , A _l-1 are all lower than _VR . In _this case, _{the transistors} T _{30 ,} T _{31 ,} .
As a result, the base potential V _X0 of the word driver D ₀ becomes high, and the word line W ₀ is selected. On the other hand, the non-selected state of the word line W ₀ corresponds to when at least one of the address signals A ₀ , A ₁ , . . . , A _l-1 is equal to or higher than _VR . In this case, one of _the transistors T _{30 ,} T _{31 ,} . Therefore, word driver
The base potential V _X0 of D ₀ becomes low due to the voltage drop caused by the resistor R ₃₁ , and the word line W ₀ is not selected.

In Fig. 3, each word decoder (WD ₁ ,
If the constant current source I _C of the selected word line _W0 is constant, even if the potential of the selected word line _W0 decreases due to an increase in the discharge current ΔI _H shown in FIG. The potentials of the unselected word lines W ₁ , . . . , W _o-1 do not decrease. Therefore, the difference between the selected word line potential and the unselected word line potential, that is, the word line potential amplitude becomes small.

In the present invention, when the selected word line potential decreases due to an increase in the discharge current ΔI _H , the current value of the constant current source I _C of each word decoder is increased to lower the unselected word line potential as well. A minimum word line potential amplitude is ensured. Such control of the constant current source I _C is performed by circuits C ₁ , C ₂ , and C _3. The circuit C ₁ is a bias circuit and generates a predetermined bias voltage V _B. Note that the bias voltage V _B
is expressed as V _B =R ₃₄ +R ₃₅ /R ₃₅ V _BE1 . However, R ₃₄ and R ₃₅ are resistances R ₃₄ and R ₃₅
The resistance value of V _BE1 is the base-emitter voltage of the transistor _T41 . Transistors T ₄₃ , T ₄₄ ,
In the dummy cell circuit constituted by the resistor R ₃₆ , the transistors T ₄₃ and T ₄₄ are always on. Therefore, the tummy cell circuit C ₂ corresponds to the left half of the circuit in FIG. 2, or the bias voltage V _B
approximately corresponds to the selected word line potential.

Circuit C ₃ consists of resistors R ₃₇ , R ₃₈ , R ₃₉ and transistors
T ₄₅ and a diode D ₁ , and changes the voltage V _Rx according to the sink current i of the dummy cell circuit C ₂ . For example, when the sink current i decreases and more discharge current flows through the selected word line, causing the word line amplitude to decrease, the potential at node N ₁ increases, and therefore, transistor T ₄₅ is controlled more in the on direction. be done. As a result, the potential V _Rx increases,
The constant current value I _C of all word decoders WD ₀ , . . . increases. As a result, the base potential of unselected drivers decreases. Note that such a change in the current value of the constant current source I _C has almost no effect on the base potential of the selected driver. This is because in this case the current I _C flows through the transistor T _R .

FIG. 4 is a circuit diagram showing a modification of the dummy cell circuit _C2 in FIG. 3. In other words, the resistance in Figure 3
Instead of R ₃₆ , a resistor R ₄₀ , a diode D ₂ and a transistor T ₄₆ are used.

(7) Effects of the Invention As explained above, according to the present invention, when the selected word line potential changes by changing the discharge current of the selected word line according to the sink current (inverse β),
Since the unselected word line potentials are also changed in the same direction, the word line potential amplitude can be kept at a minimum, and therefore the write current can be prevented from being shunted to unselected memory cells.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a conventional static type semiconductor memory device, FIG. 2 is a circuit diagram of a memory cell shown in FIG. 1, and FIG. 3 is a circuit diagram showing a semiconductor memory device as an embodiment of the present invention. FIG. 4 is a circuit diagram showing a modification of the dummy cell circuit shown in FIG. 3. C ₀₀ , ......, C _o-1 , _o-1 : memory cell, W ₀ ,
………, W _o-1 : Word line, B ₀ , ₀ , ………,
B _o-1 , _o-1 : Bit line, D ₀ , ......, D _o-1 : Word driver, WD ₀ , ......, WD _o-1 : Word decoder, △I _H : Constant discharge current source , I _C : Constant current source of word decoder, C ₁ : Bias circuit, C ₂ , C ₂ ':
Dummy cell circuit, C ₃ : A circuit that controls the constant current source I _C according to the sink current of the dummy cell circuit.

Claims (1)

[Claims] 1 A plurality of memory cells arranged in a matrix, a word line connected to each row of the memory cells, a word driver for selecting the word line, and a regulator for drawing a discharge current from the selected word line. a dummy cell having a structure similar to the memory cell to which a predetermined bias voltage is applied; and a drive capacity of each word driver according to the magnitude of a sink current to the dummy cell. What is claimed is: 1. A semiconductor memory device comprising: means for changing the potential of an unselected word line, thereby causing a change characteristic of an unselected word line potential to follow a change characteristic of a selected word line potential.