JPS6228475B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a moving pattern display device in a raster scan type image display device.

Conventionally, when displaying a desired pattern on a CRT (cathode ray tube) display device, etc., a method was generally used in which data for the display pattern was created using a microprocessor and then supplied to the image receiving unit as serial color signals R, G, and B. ing. This microprocessor has display data in its own memory, and performs operations such as sequentially reading data from the memory along each X and Y coordinate of the CRT screen under timing control. On the other hand, each pattern of display characters, figures, etc. is constructed as a collection of rectangular or square dots. One dot corresponds to one bit of data in memory, and is the smallest collection of pixels on the display screen. For example, if a ball is displayed as a dot on a CRT screen, this ball will be displayed on the X axis,
Each Y-axis is scanned with four scanning lines and displayed as a square pattern. A ball made up of such a square pattern is stored in memory as 1-bit ball information. Therefore, when moving this ball pattern, it could only be moved in units of one dot. That is, as shown in Fig. 1, a square ball pattern 1 is displayed by scanning four scanning lines each in the horizontal and vertical directions with the origin at X, Y coordinates 0, 0 on the CRT screen. For example, even if you want to move the ball along the trajectory of AA, the ball pattern can only move in units of one dot, so the trajectory of BB will be 1 → 2.3 → 4.5 → 6.7 → 8 for each screen, and the ball will not fly as you see. The images were displayed in unnatural motion, or were blurred.

To compensate for this, as shown in Figure 2, the resolution of the screen is increased by increasing the number of pixels displayed per screen and reducing the size of the pattern per dot, and the trajectory shown in Figure 1 is improved. Trajectory almost equal to AA
It is also suggested that CC be required. However, increasing the number of display pixels by reducing the area per dot has the disadvantage that the data capacity stored in the memory must be increased in units of one dot. Specifically, it is necessary to increase the X and Y coordinate bit data of the display data that indicates the origin of each pattern. For example, as shown in Figure 2, in order to quadruple the resolution in both the X and Y directions, means that the bits indicating each coordinate of X and Y must be incremented by 2 bits each and stored in the memory. In this way, the conventional method that requires an increase in memory capacity of 4 bits per pattern can handle not only moving patterns that require high resolution, but also patterns that do not require high resolution (such as stationary patterns). must all be increased by 4 bits. Therefore, the memory capacity has to be increased redundantly, which is a heavy economic burden. Also, to quadruple the resolution in the X direction, quadruple the transfer rate per 1 bit of the pattern,
In addition, in order to quadruple the resolution in the Y direction, the selection of the pattern to be displayed in the next scan line must be processed within the currently displayed scan line. The Y-direction display used to be displayed using four scanning lines, but now each dot must be displayed using one scanning line.

Therefore, during the display period of one scanning line, it is necessary to process and select the pattern to be displayed in the next scanning line. In order to achieve this, the processing speed of the microprocessor had to be quadrupled at once, so the performance required of the processor itself had to be dramatically greater.

As described above, according to the conventional movement pattern display method, in order to smoothly display the trajectory of a moving object, the memory capacity of all display patterns must be increased and the processing speed must be increased, resulting in high costs. However, it had many drawbacks in manufacturing and use, such as increased power consumption.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pattern display device that displays a moving pattern with high resolution without increasing the memory capacity for storing display data.

The present invention provides a first register in which a static pattern is stored, and the first register is provided independently,
a second register in which a moving pattern is stored; an input selection circuit that separately inputs the stationary pattern and the moving pattern to the first register and the second register; a first output control circuit that serially outputs a stationary pattern stored in the second register to a display unit at a first timing; and a first output control circuit that outputs a moving pattern stored in the second register to the display unit at a timing different from the first timing. and a second output control circuit for outputting, for the movement pattern stored in the second register, a timing signal created based on display coordinate data at which the movement pattern is displayed is used. This feature is characterized in that the pattern is moved on the display surface by outputting it to the display section.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram of a pattern display device showing an embodiment of the moving pattern display device of the present invention.

The program memory 11 is a memory (RAM) that stores display program data such as the X coordinate code, Y coordinate code, pattern name code, display column position code, and pattern color code of the pattern to be displayed. Pattern code data is output in parallel to registers 15-18 in response to control signals. Registers 15 to 18 temporarily store and hold the pattern X coordinate code, Y coordinate code, pattern name code, display column position code, and pattern color code output from the memory 11, respectively. The pattern X coordinate code held in the register 15 is input to a subtracter 19, and a horizontal counter 1 obtains a raster scan signal in the X coordinate direction of the CRT screen, which is also input to the subtracter 19.
A subtraction operation is performed with the count output from 2. If the count code from the horizontal counter 12 is larger than the X coordinate code from the register 15, the subtraction circuit 19 outputs a borrow signal to the X coordinate correction circuit 21,
A borrow generation signal is also sent to the control circuit 10. The pattern generation circuit 20 receives pattern name codes (upper addresses) input from registers 16 and 17, respectively.
and a column position code (lower address), and among pre-stored display patterns, data of a pattern specified by the pattern name code is read out in parallel. The pattern data read out from the pattern generation circuit 20 is
It is commonly led to the red, green, and blue serial-to-parallel conversion shift registers 27, 28, and 29. These parallel-serial conversion shift registers 27~
The pattern data led to 29 is passed through three AND gates 24, 25,
Reading into shift registers 27-29 is controlled according to the state of the output signal from 26. AND
A register 18 is connected to each input terminal of gates 24 to 26.
The three pattern color code data of red, green, and blue written in are inputted correspondingly. Furthermore these
The output of the pattern decoder 22 is inverted by an inverter 23 and commonly input to the other input terminals of each of the AND gates 24 to 26. A pattern name code input from the program memory 11 to the register 16 is input to the pattern decoder 22, and the special pattern is decoded. In the case of this embodiment, this special pattern is a pattern of an object that moves over time on the display screen with high resolution. Therefore, when the pattern read from the program memory 11 is a moving pattern, the pattern decoder outputs an H level, and in other cases (a stationary pattern, a background pattern, etc.), an L level is output.
The level will be output. Therefore, when the static pattern is read out, the output of the decoder 22 becomes L level, AND gates 24 to 26 are opened, and only the H level pattern color code information read out from the register 18 is passed through, and the parallel With the serial conversion shift registers 27 to 29 in operation, parallel pattern bits output from the pattern generation circuit 20 are simultaneously written into predetermined registers. The written parallel pattern bit data is serially output one bit at a time from output terminals O _R , O _G , and O _B as red, green, and blue color signals through OR gates 47 to 49, respectively. On the other hand, the output of the pattern decoder 22 is used as a control signal for the special pattern parallel-to-serial conversion shift register 30, and when this output is at H level, the pattern data read from the pattern generation circuit 20 is sent to the shift registers 27 to 29. It is entered as it is entered. Parallel for special patterns
The pattern data is serially read out one bit at a time by timing control from the serial conversion shift register 30, and the pattern data is read out in series, one bit at a time, through the AND gate 35 and the OR gate 5.
2. Through the AND gate 46, the output terminals O _R , O _G ,
OR gates 47 to 49 provided in the front stage of O _B
will be entered in all fields. Furthermore, among the display patterns set in the program memory 11, the lower two of the special pattern's X coordinate code and Y coordinate code
Special pattern memory 31, 3 for setting bits
2, and each of these memories 31 and 32 is connected to a decoder 33 and 34, respectively. Special pattern of X
The output terminal of _X1 of the coordinate code decoder 33 is connected to the other input terminal of an AND gate 35 to which the output of the special pattern parallel-to-serial conversion shift register 30 is input. On the other hand, other output terminals _X2 to _X4 and _Y1 to _Y4 of the decoders 33 and 34 are input to corresponding AND gates 36 to 42. Among these, AND gates 36 to 38 are the OR gate 4 of the next stage.
The outputs of other AND gates 39-42 (corresponding to decoder 34) are connected to AND gate 45 via OR gate 44. The other input terminal of the AND gate 45 is a special pattern serial-parallel conversion shift register 3.
An output of 0 is input, and the output terminal of this AND gate 45 is connected to the trigger input terminal of the trigger flip-flop 51. The output of the D flip-flop 50 is input through an OR gate 52 to an AND gate 46, whose other input is supplied with the output of the trigger flip-flop 51.

Here, reference numbers 10-12, 15-29, 4
The circuit blocks indicated by 7 to 49 output pattern data for displaying stationary patterns and low-resolution moving patterns to terminals O as serial color signals of red, green, and blue.
Blocks 10 to ₁₂ , 15 to ₂₃ , and 30 to ₅₂ are used as blocks for creating pattern data for displaying movement patterns.

The program memory 11 stores an X coordinate code, a Y coordinate code, a pattern name code, a column position code, and a color code for each display pattern in descending order of the X coordinate. This storage method is
It may be written via a path from a control system such as a CPU, or it may be a normal ROM in which a program pattern is designed as a mask in advance. A circuit 10 that controls the output of data for each pattern read from the program memory 11 to the register groups 15 to 18
Depending on the raster scan that scans the screen,
The data pointers (addresses) of the pattern matching the Y coordinate scanning line are stored in the data pointer stack register in order of decreasing X coordinate. The data pointer stack register stores pattern addresses for four X-coordinate scanning lines for one Y-coordinate scanning line. The storage method may be a so-called first-in, first-out method in which patterns are written in the order of the smallest X coordinate and read out in that order. Two such data pointer stack registers are provided in the control circuit 10.
While a pattern address is read from one stack register and the program memory is being addressed, another stack register is set with the address of the pattern to be scanned in the next four lines.

In this way, the pattern with the smallest X coordinate is read out from the program memory 11 based on the address data output from the stack register of the control circuit 10, and its X coordinate code, pattern name code, column position code, and color are read out from the program memory 11. The codes are set in registers 15-18, respectively.

If the pattern read out now is a moving pattern that does not require high resolution or a stationary pattern, the pattern decoder 22 outputs an L level, which is inverted by the inverter 23 and then
Open gates 24-26. At this time, register 18
The red, green, and blue bit signals read from
Only the gates at the high level output the H level to the parallel-to-serial conversion shift registers 27 to 29 at the next stage.

On the other hand, when the count output of the horizontal synchronization counter 12 that indicates the horizontal scanning line position becomes larger than the value of the X coordinate code of the display pattern read from the register 15, a borrow signal is generated as described above, that is, it is temporarily stored in the register 16. A signal indicating that the data is pattern data to be displayed on the next scanning line is output from the subtraction circuit 19 to the X coordinate correction circuit 21. Therefore, the pattern data from the pattern generation circuit (ROM) 20 addressed by the registers 16 and 17 is held in the correction circuit 21 until a borrow signal is output, and when the borrow signal is generated, the AND gates 24 to The signals are written in parallel to the shift registers 27 to 29 from which the H level is output from 26. In addition, pattern generation ROM2
Data corresponding to the pattern to be displayed is stored in 0 in advance as binary bit information of "1" and "0", and the display pattern is determined by an address signal with the pattern name code as the upper address and the column position code as the lower address. Read out as bit information. Here, the column position code serving as the lower address is used to specify the Y coordinate direction of the matrix forming one pattern, and one pattern usually forms a matrix of 8 x 8 X and Y scanning lines. If so, the column position code (3 bits) changes sequentially from 0 to 7 and is output to the pattern generation ROM 20. As a result, the 8-bit parallel data is read out eight times, and the display data for one pattern is stored in the shift registers 27 to 2.
9 in sequence.

The display pattern data set in the predetermined parallel-to-serial conversion shift registers 27 to 29 in this way is output as serial color signals under timing control from the output terminals O _R , O _G , G _B to the color signal processing circuit (Fig. (not shown) and displayed as a static pattern on the screen by raster scanning. On the other hand, when a borrow signal is output from the subtraction circuit, the control circuit 10 reads out the data pointer (address) set in the other stack register and selects the next pattern to be displayed from the memory 11 in the registers 15 to 18. Performs processing to send data to in parallel.

Next, a case where the pattern data read from the program memory 11 is a pattern that moves with high resolution will be described. In this embodiment, a white ball pattern is exemplified as this movement pattern.

In the ball pattern, as shown in FIG. 4, "1" bit information is written in the shaded area in an 8.times.8 memory area. When this ball pattern data is read from the pattern generator 20, the address signal specifying the ball pattern is decoded by the decoder 22, and the special pattern parallel-to-serial conversion shift register 30 enters a write state. At this time, the ball pattern data whose timing has been corrected by the X coordinate correction circuit 21 is written into the shift register 30 in 8 bits in parallel. On the other hand, as described above, the other shift registers 27 to 29 are disabled and are not used. Data 00000001 is stored in the special pattern shift register 30, and is serially read out to the AND gate 35 in synchronization with the clock signal _φ2 . In this embodiment, an example of moving the ball pattern with high resolution along the trajectory DD shown in FIG. 5 will be described with reference to timing charts shown in FIGS. 6 and 7.

First, on the first screen of the CRT, a ball pattern 1 (see FIG. 5) is displayed in a square section consisting of four scanning lines each in the X and Y directions, starting from the X, Y coordinates 0,0. In this case, the pattern decoder 22 shown in FIG. 3 outputs a 1-level output, and the ball pattern data shown in FIG. 4 is read from the pattern generation ROM 20 to the special pattern shift register 30. First, the output 8 bits 00000001 corresponding to column position 0 in the Y direction in FIG. 4 are written in parallel, and the other shift registers 27 to 29
The shift register _{30 moves bit by bit in the order of 0 → 0 → 0 → 0 → 0 → 0 → 0 → 1 in synchronization with the same clock φ2 as the synchronization timing that is output from the output terminals O R , O G} , O B to the output terminals O R , O G , O B . is read out to the AND gate 35.

On the other hand, the vertical blanking period (blanking period)
0,0 data is written in the special pattern memories 31 and 32, and the trigger flip-flops 51 and D
The flip-flop 50 is set to a reset state by the vertical retrace signal VBLK. This allows each decoder 33, 3 of the X coordinate and Y coordinate code memories 31, 32 to store the lower bits of the special pattern to
The output terminals X ₁ and Y ₁ of 4 are both at 1 level. The 1 level signal output from the _X1 output terminal of the decoder 33 is supplied to the AND gate 35 during one screen display period. Further, a 1 level signal is also output from the _Y1 output terminal of the decoder 34 to the AND gate 39 for one screen display period. Therefore, the OR gate 44 outputs the first scanning line 4H-1 which displays one bit of display data in units of four scanning lines. This operation will be explained with reference to the timing diagrams of FIGS. 6 and 7. FIG. 6 shows the output pulses of each gate when displaying three screens on three axes of Y coordinates 0, 1, and 2. The set pulses 4H-1, ...4H-4 shown in a to d in the figure are timing pulses that are output at different timings for each coordinate of Y=0, 1, 2, and are synchronized with the clock _φ2 along with the generation of these timing pulses. 1 level ball pattern data is read out from the shift register 30 four times (e in the figure). As a result, the output terminal of the AND gate 45 outputs a 1-level output pulse shown in the figure f when the timing pulse 4H-1 is generated. Therefore, the next stage trigger, flip-flop 51, outputs 1 level from the timing pulse 4H-1 generation until the next timing pulse 4H-1 occurs, as shown in FIG. This trigger, the output g from the flip-flop, is ball pattern data (1 level) periodically output from the shift register 30.
This signal is also input to an AND gate 46, and a 1-level signal is outputted from this output terminal in synchronization with clock _φ2 as shown in FIG. These four output pulses have pulse widths as shown in FIG. 7 and are led to the color signal conversion circuit. FIG. 7 is a timing diagram showing the serial signals of the ball pattern output from the output terminals O _R , O _G , _{O B to} the color signal conversion matrix circuit in synchronization with the four-phase clock pulses φ _{2 , 2} , φ 1 , 1 . It is. In FIG. 7, the ball pattern data output from the AND gate 46 in _FIG . as output terminals O _R , O _G , O _B
is output from. As a result, a square ball pattern is displayed on the CRT screen as shown in FIG. 51. At this time, as in this embodiment, O _R , O _G ,
When the output from the AND gate 46 is added to all output terminals of O _B , a white pattern is displayed.

When displaying a pattern for timing pulse 4H-2 cycles in synchronization with position 2 in Fig. 5, that is, ₁ cycle of clock pulse φ, on the next second screen display,
Output pulses as shown by j to l in FIG. 6 are obtained. That is, by setting (1, 1) and (0, 1) in the special memories 31 and 32, respectively, the X ₄ and Y ₂ outputs of the decoders 31 and 34 become 1 level. This causes the D flip-flop 50 to be set at clock ₁ , and output Q to clock ₁ .
One level per period is applied to AND gate 46. On the other hand, the clock _φ2 is output from the shift register 30.
Ball pattern data e read out in synchronization with
is output from the AND gate 45 under the control of the timing pulse 4H-2 inputted through the OR gate 44, and sets the trigger flip-flop 51. Therefore, the output signal shown in FIG. 6l appears at the output of the AND gate 46. The ball pattern signal l created on this second screen is shown in FIG.
~Timing pulse 4H as shown by L-
2. Output for one period in synchronization with clock pulse ₁ .

Furthermore, on the third screen, set the ball's X, Y coordinate code to (1, 0), set it to memory 31, set it to 0, 1, and set it to memory 32.
When 1 and 0 _{are written} to the
6 is opened, and the output of the D flip-flop 50 becomes _{a 2-} synchronous output. Furthermore, the output of the AND gate 45 becomes m in FIG.
The output of is n in FIG. Therefore, the output of the AND gate 46 becomes O in FIG. 6, and the clock pulse
With ₂ synchronous outputs, it will look like M to P in Figure 7,
A white ball is displayed at position 3 shown in FIG.

Similarly, on the fourth screen (not shown), balls
Set the coordinate code to (1, 0) and set the memory 31 to 1,
1, and by setting the memory 32 to 1,1, it is possible to change from 4H-4 of Y=0 to 4H-4 of Y=1 using the same operation as above.
From ₁ of X=1 to 4H-3 of X=2
A white ball is displayed between ₁ and 5, and the X and Y coordinate codes of the ball are set to (2, 1) on the 5 screen, and by setting the memory 31 to 0, 1 and the memory 32 to 0, 1, Y= 1 4H-2 to Y=2 4H-1
A white ball is displayed between ₂ at X=2 and ₂ at X=3. Similarly, on the sixth screen, the X and Y coordinate codes are set to (2, 1), the memory 31 is set to 1, 0, and the memory 32 is set to 1, 1. Also, on the 7th screen, set the X, Y coordinate code to (2, 2), set the memory 31 to 1, 1, and set the memory 32 to 0, 1, and on the 8th screen, set the X, Y coordinate code to (3, 3), and set the memory 31 to 0, 1. is set to 0,0, and the memory 32 is set to 0,0. By rewriting the X, Y coordinate codes and the contents of the special pattern memories 31, 32 during the blanking period, the ball can be further moved to 6, 7 in FIG.
Move to 8, 1 → 2 → 3 → 4 → 5 → in Figure 4
A white ball is displayed, drawing a DD trajectory of 6 → 7 → 8.

In this way, according to this embodiment, high-resolution timing pulses and clock pulses are created within the microprocessor serving as the display data creation section, and
By controlling the output of the serial color signals in synchronization with these pulses, moving patterns can be displayed with high resolution without increasing memory capacity. Furthermore, by changing the data written to the special pattern memory, the direction of movement can be freely set, making it possible to display more natural and fine movements. Further, since there is no need to increase the processing speed (access time) for the program memory 11, power consumption does not increase, and a microprocessor for the processing can be easily manufactured.

Note that the special pattern memory 3 used in this example
1 and 32 may be flip-flop circuits or other writable storage means. Furthermore, the special pattern memory and decoders 33 and 34 can be manufactured as a single RAM.In particular, if the storage capacity is increased to 3 bits, it is possible to move with eight times the resolution by using eight clock pulses and eight timing pulses. It can also be displayed. In other words, the timing of outputting the serial color signals is
By controlling with clock pulses and timing pulses, more minute movement display becomes possible.

[Brief explanation of the drawing]

1 and 2 are display state diagrams of conventional movement patterns, FIG. 3 is a block diagram of an image processing device showing an embodiment of the present invention, and FIG. 4 is a ball pattern applied in this embodiment. 5 and 5 are movement state diagrams of the ball pattern according to this embodiment, and FIGS. 6 and 7 are operation timing diagrams of the image processing apparatus, respectively. AA~DD...Ball trajectory, 10...Control unit, 1
1...Program data RAM, 12...Horizontal counter, 15-18...Register, 19...Subtractor, 20...Pattern generation ROM, 21...X coordinate correction circuit, 22...Pattern decoder, 23...
...Inverter, 24-26, 35-42, 45,
46...AND gate, 27-30...Parallel-to-serial conversion shift register, 31, 32...Special pattern memory, 33, 34...Decoder, 43,
44,47~49,52...OR gate, 50...
...D flip-flop, 51...Trigger flip-flop.

Claims (1)

[Claims] 1. A first register in which a stationary pattern is stored, a second register provided independently from the first register, and a second register in which a moving pattern is stored, and a an input selection circuit that separately inputs a static pattern and a moving pattern; a first output control circuit that serially outputs the static pattern stored in the first register to a display section at a first timing; a second output control circuit that outputs the movement pattern stored in the second register to the display section at a timing different from the first timing, the movement pattern stored in the second register; A pattern display characterized in that a pattern is moved on a display surface by outputting it to a display section using a timing signal created based on display coordinate data on which the movement pattern is displayed. Device.