JPS62284441A - Address control device - Google Patents

Abstract

PURPOSE:To reduce the error of calculation and to round addresses in each arbitrary unit by providing the titled device with an address processing part for executing half-adjust based on the value of specific bits of an address calculated by an address generating part. CONSTITUTION:A parameter register group 1 stores parameters necessary for addresses. The parameters stored in the register group 1 are used for the calculation of an address by the address generating part 2 and the calculated result is outputted to an address half-adjust part 3 as an address. The half-adjust part 3 executes round-up or round-down processing in accordance with the value of the specific bits to execute half-adjust processing in each optional bit unit. Since the bits to be used for half-adjust processing can be specified, an integer address close to a calculated address can be generated and a straight line or a square based upon a fine variable can be more accurately drawn.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) This invention is a method for storing information such as graphics or image information, for example in image processing ￥ AW1 etc. The present invention relates to an address control device that controls addresses given to an image memory.

(Prior art) In recent years, personal computers, workstations,
With the development of image editing devices such as electronic file devices, requests for graphic processing and image information are being met. The demand is getting stronger. In addition, demands for drawing speed, generation of straight lines, etc. are becoming stronger. At this time, the problem is how to generate addresses quickly and accurately by affine transformation during graphic drawing or rotation at an arbitrary angle.

Conventionally, there are two methods for generating this address: one method is to generate it by software, and the other is to generate it by hardware. In the method of generating addresses using software, more accurate addresses can be calculated and generated by the CPU by increasing the number of decimal bits in the address or by using a linear generation algorithm called DDA. . However, in this software method, the CPU of the system is 1
If there is only one CPU, the CPU is monopolized, making it impossible to perform other processing, and the processing speed is slow.

Additionally, the hardware method increases the fractional part of the address to generate an accurate address.
Hardware scale increases. In addition, when generating a straight line as shown in Figure 12(a), there was a drawback that the straight line was not as shown in Figure 12(b), but as shown in Figure 12(C). .

Therefore, not only by straight lines but also by affine transformation etc.
Even when generating an address for a rectangular WA area that has been rotated by an arbitrary angle, the address generation circuit alone cannot approximate the calculated address to the closest address, resulting in errors. Ta. Furthermore, if we consider a memory system such as a bitmap memory not only to have a structure of 1 pixel and 1 pit, but also to have a structure of 2 pits per pixel and 4 pits per pixel, it is not possible to generate addresses corresponding to each. Ta.

(1F11 problems to be solved by the invention) This invention:
As mentioned above, this eliminates the disadvantage of slow speed when generating addresses by software, or the disadvantage that errors tend to occur in address calculations during processing such as affine transformation when generating addresses by hardware. It is an object of the present invention to provide an address 111111 device that has little calculation error when generating addresses by affine transformation, etc., and can round up 7 addresses in arbitrary units.

[Configuration of the invention 1 (Means for solving the problem) Address IQ of this invention 10! ! As shown in the functional block diagram of FIG. 1, It is a parameter register group 1 that stores parameters necessary for address generation in a device that generates an address that specifies the access position of data in the information storage II, and this parameter register. An address generator 2 calculates an address using the parameters stored in group 1 and outputs the result of the calculation as an address, and performs a carry or a It is composed of an address processing section 3 that rounds off addresses by performing truncation processing.

(Function) This invention provides an address processing unit that performs rounding by carrying and truncating according to the value of a specific bit of the address calculated by the address generation unit, so that rounding can be performed at any bit position. It is something.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 shows an image information editing device as an image processing device according to the present invention. In other words, reference numeral 11 is a main control unit, which includes a CPU 12 that performs various controls, a main memory 13, a hedge memory 14 that has a storage capacity corresponding to image information for several pages of an A4 size manuscript, and a compression (redundancy) of image information. It has a compression/decompression circuit 15 that performs decompression (reducing redundancy) and decompression (returning reduced redundancy), a pattern generator 16 storing pattern information such as characters or symbols, a display memory 17a, and a display control device 17b. It is comprised of a display interface 17, an address generator 18 as an address PM device, and an enlargement/reduction circuit 30 for enlarging and reducing image information.

The address generator 18 controls access to the page memory 14 and the display memory 17a in the display interface 17, that is, it outputs narrowing addresses or write addresses to the page memory 14, and outputs narrowing addresses or write addresses to the read addresses of the page memory 14. The corresponding write address is output to the display interface 17. Further, the address generator 18 outputs (throughs) read and write addresses from the CPU 12 to the page memory 14 or display memory 17a when the page memory 14 or display memory 17a is used as a memory for the CPU 12. .

20 is, for example, a two-dimensional scanning device M (for example, a scanner) that scans the document (text I) two-dimensionally over 21 with a laser beam to obtain an electrical signal corresponding to the image information on the document 21. be.

Reference numeral 22 denotes an optical disk device which sequentially stores image information and the like read by the two-dimensional scanning device 20 and supplied via the main device 11111 on the optical disk 19.

On the other hand, 23 is a keyboard for inputting a unique search code corresponding to image information and various operation commands. 24 is an output Ill, for example, image information read by a two-dimensional scanning device F-20 from a cathode ray tube display device t (hereinafter referred to as a CRT display device) serving as a display section and supplied via the main control ID device 11; It displays image information read out from the optical disk device M22 and supplied via the system control device 11, and together with the display interface 17 in the main control device 11 constitutes a significant image information display device. .

25 is a recorder (for example, a printer), which is read by the two-dimensional scanning device 20 and the main! i control 1! 111 or image information read from the optical disk device 22 and supplied via the main controller 11, as a hard copy 26. Reference numeral 27 denotes a magnetic disk device, which retrieves search data consisting of a search code input using the keyboard 23, the size of image information for one item corresponding to this search code, and a storage address one level above the optical disk in which the image information is stored. magnetic disk 2
The image information is stored for every 1 in 8 images.

Also, 29 is Bointing HM, for example CR
T display equipment! By arbitrarily moving the cursor on the 24 vertically and horizontally and giving instructions at the desired position, you can change the display content where the cursor is located (for example, various modes, editing images, cut and cut ranges, The above-mentioned icons, etc.) can be selected using a mouse, 'or the same tablet as the display contents of the CRT display 1iff24 (for example, various modes, edited images, cropping ranges, and each of the above-mentioned icons, etc.).

The above search data includes a search code (image name) consisting of a plurality of search keys, an image storage start track address on one optical disc of image information corresponding to this search code,
It consists of the image storage start sector address and the number of image storage sectors (image length).

The address generator 18 is constructed as shown in FIG. That is, the parameter register group 31 is
It consists of a register group <20al) that individually stores various parameters for performing address calculation, and the data (Do ~ Dt s >) to be set in the register is the above C
PU12 to I10 buffer? 32, and signals for selecting registers (RAO to RA4
) is supplied from the CPU 12 via the input buffer 33 and decoder 34.

The above parameters include operation mode (OPMD; 8
bit), operation command (OPCD: 8 bits), main scanning repetition number (MN: 13 bits), which indicates the number of address calculations within one scan in the main scanning direction, and indicates the number of address calculations within one scan in the sub-scanning direction. Sub-scanning repetition number (SN
: 13 pits), X-direction scanning width (XW: 11 pits) indicating the scanning width in the X direction of the address calculation m area, and start address (XST) indicating the start address of address calculation.
A.

YSTA: 14 pits), the number of main scanning steps (MDX) indicating the address increment for each time in the main scanning direction.

MDY: 14 pits), the number of sub-scanning steps (SDX) indicating each address increment in the sub-scanning direction.

SDY; 14 pits), clipping address (CXI) indicating the address of the clipping II area.

CYI, CXE, CYElCMOD: 13L't), direction code data (NA: 16 bits) consisting of a direction code and step number, and mode data specifying the rounding mode. The above operation command o
pco is an enable signal (A
GENB>, a recalculation signal (RPT) instructing repetition of address calculation, and a signal instructing clearing of each parameter and internal circuit.

The concept of each of the above parameters is as shown in FIG. However, the X direction scanning width XW:XW.

Start address STA: xsta, ysta1 Number of main scanning steps MD: mdx, mdy% #J number of scanning steps SD: sdx, sdy, Number of main scanning repetitions MN; mn,
Sub-scanning repetition number SN; sn, clipping address CI
, CE: cxi, cyilcxe, cye, main scanning is performed at Pa=Px, and sub-scanning is performed at Pa-+P2. The coordinates of Pa above are expressed as (XSta, VSta), and the coordinates of Pl are (xsta+ (mdx)x (
mn), ySta+ (mdy)X (mn)), and the coordinates of P2 are (xsta+ (sdx)x (s
n), VSta+ (sdy)X (sn)).

The operation output from the parameter register group 31 is supplied to the timing controller 35. This timing controller 35 controls the entire timing signal (MCLK) according to the supplied operation command 0PCD.

5CLK, ACLK,...).

Further, the main scanning repetition number MN output from the parameter register group 31 is supplied to the main counter 36.

As a result, the main counter 3-6 counts the number of times main scanning is repeated. The sub-scanning repetition number SN output from the parameter register group 31 is supplied to a sub-counter 37. As a result, the sub-counter 37 counts the number of times main scanning is repeated.

The outputs of the main counter 36 and sub-counter 37 are supplied to a line status circuit 38. This line status circuit 38, depending on the supplied count value,
Main scanning end signal (MSEND), sub-scanning line end signal (SSEND), address generation end signal (AGEND)
＞ is output. These signals are outputted to the display memory 17a via the output buffer 61. The main counter 36, sub-counter 37, and line status circuit 38 constitute a line control section 71.

Also, the X output from the parameter register group 31 is
The start address X5TA1 of the direction parameters, the number of main scanning steps MDX, the number of sub-scanning steps SDX, and the clock from the timing controller 35 are supplied to the X address generation section 39. This X address generation 8I
The X39 calculates an address in the X direction (X address) and a two-dimensional address by performing arithmetic operations according to the supplied parameters and data.

The output of the decimal part of the X address generating section 39, that is, the address signals <AXF12 to AxF9), is outputted to the display memory 17a via the 7-upput buffer 40.
' Roughly speaking, if the start address X5TA1 of the Y-direction parameters output from the parameter register group 31, the number MDY of main scanning steps, the number SDY of II scanning steps, and the clock from the timing controller 35 are
It is supplied to the address generation section 41. The Y address generating section 41 calculates an address in the Y direction (Y address) by performing calculations according to supplied parameters and a clock, thereby calculating a two-dimensional address.

The output of the decimal part of the Y address generating section 41, that is, the address signals (AYF12 to AYF9), is outputted to the display memory 17a via the output buffer 42.

The outputs of the integer part and the decimal part of the x, Y address generation section 39.41 are respectively supplied to a rounding circuit (address processing section) 43.44. These rounding circuits 43
．． 44 is for rounding off the number of digits set by the above parameters. The output of the rounding circuit 43, that is, the address signal (AXO to AX3) is supplied to the display memory 17a via the output buffer 45, and the output of the rounding circuit 44, that is, the address signal (AYa-AY3) is supplied to the output buffer 746. The signal is supplied to the display memory 17a through the display memory 17a. The above X, Y address generation section 39.41 and rounding circuit 43.44
The address calculation circuit 73 is configured by:

Each of the above address signals (AXF12 to AXF9, AYFI
2~AYF9, AXo~AX3, AYO~
AY3) is used for scaling, etc.

The outputs of the rounding circuits 43 and 44 and the X-direction scanning width XW output from the parameter register group 31 are supplied to the address converter 47.

This address conversion unit 47 converts the two-dimensional address calculated by the supplied address calculation circuit 39.41 from two-dimensional to one-dimensional by performing the calculation rA-XWxY+XJ using the value of the X-direction scanning width XW. It consists of a multiplier circuit group and an adder circuit group. The output of the address conversion section 47 is supplied to a selection circuit 48.

Further, the selection circuit 48 is supplied with address signals (CAO to CA 25 ) from the CPU 12 via an input buffer 49 . The selection circuit 48 selects whether to output the calculation result from the address conversion section 47 as it is or to output an address signal supplied from the CPU 12. Is the address signal <AO~A25) from the selection circuit 48 outputted back? 50 to the display memory 17a.

Also, the clipping addresses CXI, CYI, CxElCYEl output from the parameter register group 31 are
CMOD is supplied to clipping controls 0-551. This clipping controller 51 is supplied with the X address and Y address from the rounding circuits 43 and 44. The clipping controller 51 is
Clipping addresses CXI, CYI supplied.

Compare the clipping area parameters set by CXE and CYE with the X and Y addresses, and select the inside/outside, right edge,
It determines the left edge, and depending on the determination result, a window signal (WND), a left edge window signal (LWND), and a right edge window signal indicating the inside and outside, right edge, and left edge of the specified rI4 area (clipping area) are generated. (RWND) is output to the display memory 17a via the clipping status 52 and output buffer 753.

The clipping controller 51, clipping status 52, and output buffer? 53 constitutes a clipping ill tlD section 72.

Further, a register write signal (WR) and a register successive signal (RD) supplied from the CPU 12 are supplied to the parameter register group 31 via an interface 62.

Further, each of the output buffers 4o... is supplied with an address output enable signal (OE) from the display memory 17a.
) is now supplied.

Parameters necessary for address 611111 are sequentially supplied to parameter register group 31 via I10 buffer 32 as input/output data signals. As a result, in the parameter register group 31, each parameter is set in the register specified by the register address signal (RAO to RA4) supplied from the decoder 34 in synchronization with the register write signal (WR). There is. At this time, the previously set parameters are used again for the parameters that were not set.

Next, the rounding circuits 43 and 44 will be explained using FIG. 5. The circuit configurations of the rounding circuits 43 and 44 are common. Further, the addresses supplied from the X address generation 8B39 and the Y atref generation section 41 to the rounding circuits 43.44 are, for example, as shown in FIG.
F). Its arrangement aalsA D D
is composed of 14 bits (ADD13 to ADDO), and M
SB is a sign bit. Also, the decimal part ADDF
is composed of 13 bits (ADDF15 to ADDF3). For example, the above address is rol 10100
It is 10110101100000101000J. Among these, the rounding circuit 43 (, 44) inputs the 14 bits of the integer part (ADD13 to ADDO) of the above address.
) and 1 bit of the decimal part (ADDF15), a total of 16 bits, are input, rounded off, and 14 bits of the integer part (AD13 to ADO) are output.

That is, the rounding circuit 43 (, 44) includes a mode designation register 101 in which 3-bit mode data indicating the rounding mode supplied from the parameter register detail 31 is stored, and a mode supplied from the mode designation register 101. A 9-bit signal corresponding to the data is output, that is, a signal necessary for rounding is output according to the rounding mode, and each output of the decoder 102 consisting of a gate and the decoder 102 is supplied, and the address Of these, ADDO-ADD3, ADDF
AND gate 103a to which 15 is supplied.

...103i, the above AND gate 103a, ...1
4-bit full adder 104 that adds the outputs from 03h
, the above AND gate 103i and addresses ADD4-A
4-bit full adder 105 that adds the outputs from DD7
, a 4-bit full adder 106 that adds the outputs from ADD8 to ADD11 at the above address, and a 2-bit full adder 107 that adds the outputs from ADD8 to ADD11 at the above address. The full adders 104, 105, 106, and 107 constitute a 14-bit filter, and carry is performed by rounding.

The mode data of the mode specification register 101 (ROM
OD),! :t, Tit, "000" is rounded L mode, roolJ is the first bit of the decimal part ADDF1
5 is the rounding bit, roloJ is the mode where the first bit ADDO of the integer part is the rounding bit, rollJ is the mode where the second bit ADD 1 of the integer part is the rounding bit, NOOJ is the mode where the second bit ADDO of the integer part is the rounding bit. Mode where the third pit ADD2 is the rounding bit, rio
iJ consists of six modes, including a mode in which the fourth pit ADD3 of the integer part is the rounding bit, and is shown in Table 1 below.
It is shown in the figure below. As a result, 1 address unit, 2 address unit, 8 address unit, 1 address unit, 1 address unit, 2 address unit, 1 address unit, etc.
It is possible to generate addresses in units of 6 addresses.

The decoder 102 includes the mode designation register 101
The 9-bit signal corresponding to the mode data from the output terminal RCO1RC1, RO2, RO3, RO, R1, R2,
It is designed to output from R3 and R4. for example,
As shown in Table 1 below, rl 11100000J is output for mode data rooOJ, and mode data r
rl 11110000J is output for o01J, and rol 11010 is output for mode data r010J.
00J is output, and r for mode data r011J.
ool 100100J is output and mode data N
rooolooloJ is output for OOJ, and "0oOOoOOo1" is output for mode data "1o1"
is now output.

The output from the output terminal RCO of the decoder 102 is supplied to one end of the AND gate 103b, the output from the output terminal RC1 is supplied to one end of the AND gate 103d, and the output from the output terminal RC2 is supplied to one end of the AND gate 103f. The output from the output terminal RC3 is output from the AND gate 103h.
The output from the output terminal RO is supplied to one end of the AND gate 103a, the output from the output terminal R1 is supplied to one end of the AND gate 103C, and the output from the output terminal R2 is supplied to one end of the AND gate 103e. The output from the output terminal R3 is supplied to one end of the AND gate 103g, and the output from the output terminal R4 is supplied to the AND gate 1031.
is supplied to one end of the

The ADDF 15 at the above address is supplied to the other end of the AND gate 103a, and the AND gate 103b,
The other end of the AND gate 103c is supplied with the address ADDO, and the other ends of the AND gates 103d and 103e are supplied with the address ADDl.
f.

The other end of 103Q is supplied with the address ADD2, and the other ends of the AND gates 103h and 103i are supplied with the address ADD3.

Furthermore, the outputs of the AND gates 103a to 103h are as follows:
Input terminals AO1BO1A1 and B1 of adder 104, respectively
, A2, B2, A3, and B3. This results in
Adder 104 adds the contents of input terminals AO and So and the contents of lower bits (carry), outputs the addition result from output terminal YO, and adds the contents of input terminals A1 and B1 and the contents of lower bits (carry). , the addition result is output from the output terminal Y1, the contents of the input terminals A2 and B2 and the contents of the lower bit (carry) are added, the addition result is output from the output terminal Y2, and the addition result is output from the input terminal A3, B3. and the content (carry) of the lower bits are considered, and the addition result is output from the output terminal Y3, and these outputs are output as addresses AOO to AO3.

In addition, the output of the AND gate 103i, address AD
D4 to ADD7 are input terminals AO of the adder 105, respectively.
1BO1B1.82, supplied to B3, this adder 10
Input terminals A1, A2, and A3 of 5 are grounded. As a result, the adder 105 performs addition using each input terminal and the carry supplied from the adder 104, and outputs the addition result from the output IYO-Y3, and these outputs are used as addresses AD4 to AD7. Output.

Further, the addresses ADD8 to ADD11 are supplied to input terminals BO181, 82, and B3 of the adder 106, respectively, and input terminals AO1A1, A2, and A3 of the adder 106.
is grounded. As a result, the adder 106 performs addition using each input terminal and the carry supplied from the adder 105, and outputs the addition result from the output mYo-Y3, and these outputs are sent to addresses AD8 to AD.
It is output as 11.

Further, the addresses ADD12 and ADDl3 are each supplied to the input end BO1B1 of the adder 107, and the input end AO1A1 of this adder 107 is grounded. As a result, the adder 107 performs addition using each input terminal and the carry supplied from the adder 106, and outputs the addition result from the output terminal YO1Y1, and these outputs are output as addresses AD12 and AD13. be done.

In such a configuration, rounding processing will be explained. For example, now, the address from the X at 12 generating unit 39 (or the Y at 9 f generating unit 41) is as shown in FIG.
Assume that 1010oo>r-.

By the way, when the rounding mode data is rooOJ, that is, the mode without rounding, the IT 1 IT signal is output from the output terminals RCO to RC3 of the decoder 1o2, and '0'' is output from the output terminals RO to RC4.

A signal is output. As a result, the AND gate 103b
, 103d, 1o3f', 103Q (7) gate opens. Therefore, the same addresses as addresses ADDO to ADD13 are output as they are as addresses ADO to AD13. As a result, the rounding circuit 43 outputs an address obtained by truncating the decimal part ADDF15 of the address from the X address generating section 39.

In addition, if the rounding mode data is a mode in which rooIJ, that is, the first pit ADDF15 of the decimal part is the rounding bit, the output terminals RCO to RC of the decoder 102
A "1" signal is output from the output terminal RO, a 1" signal is output from the output terminal RO, and a °'0" signal is output from the output terminals R1 to RC4.
The gates of 3b1103d, 103f, and 103Q open.

Therefore, the adder 104 adds the first bit ADDO of the integer part of the address from the X address generating section 39 and the first bit ADDF15 of the decimal part, and the address ADO becomes 0'1''.

At this time, since the first bit ADDO of the integer part is not carried, the same addresses as the addresses AD01 to ADD13 are output as they are as the addresses ADI to AD13. As a result, an address (0
1101001101011) is output from the rounding circuit 43.

In addition, in the case of a mode in which the first bit ADDO of the integer part is a rounding bit, the address (011
01001101010) is output from the rounding circuit 43, and in the mode where the second bit ADDI of the integer part is the rounding bit, the address (011
01001101100) is output from the rounding circuit 43, and in the mode where the third bit ADD2 of the integer part is the rounding bit, the address (011o1001101000) obtained by rounding off the integer part ADD2 of the address from the X address generator 39 is output from the rounding circuit 43.
In the mode in which the fourth bit ADD3 of the integer part is the rounding bit, the address (01101001110000) obtained by rounding off the integer part ADD3 of the address from the X address generator 39 is the rounding circuit 43.
is output from. The relationship between the mode data and the address ADO-AD13 output from the rounding circuit 43 is as shown in Table 2 below.

When the addresses in each of the above modes are expressed as one-dimensional addresses, they become as shown in FIG. Here, the x mark is an address including a decimal part generated by the address generation part 1 (39, 41), and the O mark is an address after rounding in each mode. This shows that an address that is very close to the correct address is generated.

Next, Table 3 shows the case where two-dimensional addresses are generated.
This will be explained based on FIG. Table 3 shows the addresses generated by the X at 92 generating section 39 and the Y at 92 generating section 41 when a straight line as shown in FIG. 8(a) is generated. Each of these addresses is rounded off by a circuit 43.
．． Table 4 shows the results of rounding in each mode using 44. That is, A in Table 4 shows the output of the rounding circuits 43 and 44 in the mode in which rounding is not performed, and the address corresponding to this output is shown in FIG.
b).

Further, 8 in Table 4 shows the output of the rounding circuits 43 and 44 in the mode of rounding off the first bit of the decimal part, and the address corresponding to this output is as shown in FIG. 8 (C). become. As a result, factors 8 (b) and (C) above
It can be seen that by rounding off the first bit of the decimal part in FIG. 8(C), an address closer to the straight line shown in FIG. 8(a) is generated.

Next, a case will be described in which the memory configuration is 2 bits per pixel in the Y direction. At this time, regarding the Y address,
If the first pit YADDO of the integer part is not rounded off but rounded down, the result will be as shown in FIG. 8(d).

Furthermore, when the first pit YADDO of the integer part is rounded off, the address becomes as shown in C of Table 3, as shown in FIG. 8(e). As a result, as shown in FIG. 8(d) and (e) above,
It can be seen that the rounding shown in FIG. 8(e) generates addresses closer to the straight line shown in FIG. 8(a).

Next, the flow of signals in each part will be explained with reference to the flowchart shown in FIG. First, the parameter register group 31 or each buffer is initialized. Next, specify the operation mode. The operation mode is specified by specifying an address generation mode, an output address selection mode, a clipping mode, and a rounding mode. Next, the parameters of the addresses to be calculated by the address generator 18 are set.

These parameters are as described above, and it is sufficient to set only the necessary parameters. After setting various parameters in this manner, a command to start address calculation is set. With this set parameter,
The rounding circuit 43 rounds off the start address of the X address generator 39 as described above, and
Generate an address. Furthermore, the rounding circuit 44 performs rounding processing on the start address of the Y address generating section 41 as described above to generate a Y address. After this generation, if two-dimensional address output is specified,
Address signals (AXo to AX!) are sent via the output buffers 745.46, and if one-dimensional address output is specified, the address converter 47 converts the X address and Y address from the rounding circuit 43.44. After converting into a one-dimensional address, the address signal (AO to A25) is sent via the selection circuit 48 and the output buffer 50.
is output to the display memory 17a.

Also, the X address from the above rounding circuit 43.44,
The Y address is supplied to the clipping controller 51. As a result, the clipping controller 51 receives the clipping address CX I, CY I%CXE1CYEt supplied from the parameter register group 31.
'Compare the address representing the set clipping area with the x and Y addresses from the rounding circuits 43 and 44 to determine whether the specified area is inside or outside, right end, or left end. As a result of this determination, the window signal <WND) indicating the inside/outside, right edge, and left edge of the specified area, and the left edge window signal <L
WND) and the right edge window signal (RWND) are output to the display memory 17a via the clipping status 52 and output buffer 53.

Next, each operation timing will be explained.

In other words, the register write signal W from the CPL 112
When R is supplied to the parameter register group 31, I10 buffer 32, and timing controller 35 via the CPU interface 62, when the register write signal WR rises, the signal is sent from the CPLJ 12 via the input buffer 33 and decoder 34. The I10 buffer 3 is sent from the CPU 12 to the register selected by the supplied register address signals RAo to RA4.
The input/output data signal Do''Dls as a parameter or command supplied via the input terminal 2 is stored.As a result, various parameters and commands shown in FIG. 4, for example, are set in the parameter register group 31.

Further, the register read signal RD from the CPU 12 is c
When supplied to the parameter register group 31, I10 buffer 32, and timing controller 35 via the pu+ interface 62, the register read signal R
At the rising edge of D, the status of the register selected by the register address signals RAa to RA4 supplied from the CPU 12 via the input buffer 33 and decoder 34 is changed to C via the I10 buffer 32.
It is output to PLJ12.

Then, in a state where various parameters are stored in the parameter register group 31 as described above, CPIJ
The instruction command from I is supplied to the parameter register group 31. Then, the enable signal AGEND in this instruction command is supplied to the timing controller 35. As a result, the timing controller 35 generates various clocks and sequentially outputs the address clock ACLK to the X address generation section 39 and the X address generation section 41. As a result, the X address generator 39 outputs the supplied start address [xstaJ as an X address. Further, the Y-Abi 92 generation unit 41 outputs the supplied start address rYstaJ as a Y address.

Therefore, the X address from the X address generation section 39 is rounded off by the rounding circuit 43 and then supplied to the address conversion section 47. In addition, the Y at 92 generating section 4
The Y address from 1 is rounded off by the rounding circuit 44 and then supplied to the address converter 47.

Then, the address conversion unit 47 converts the supplied X1Y address into a one-dimensional address signal (BAO to BA25) and supplies it via the selection circuit 48. As a result, the address signal A output from the output buffer 50
O-A25 is supplied to display memory 17a.

Further, in response to the rise of the address clock ACLK, the X AT 12 generating section 39 calculates an address in the X direction (X address) by performing a program according to the supplied parameters, and calculates a two-dimensional address. . For example, an address rxsta+mdxJ in the main scanning direction of Po+1 steps is calculated as the scanning address. Further, the Y-axis 92 generation unit 41 calculates an address in the Y direction (Y address) by performing calculations according to the supplied parameters, and calculates a two-dimensional address.

For example, an address [ysta+mdyJ] in the sub-scanning direction of Pa+1 steps is calculated as the scanning address.

Therefore, the X address from the X address generation section 39 is rounded off by the rounding circuit 43 as described above, and then supplied to the address conversion section 47. Further, the Y address from the Y atto 92 generating section 41 is rounded off by the rounding circuit 44.
After being rounded off as described above, the address converter 4
7.

Then, the address conversion unit 47 converts the supplied X1Y address into a one-dimensional address signal (BAO to 8A25) and supplies it via the selection circuit 48. As a result, the address signal A output from the output buffer 50
O-A25 is supplied to display memory 17a.

Further, the main counter 36 is counted up in response to the rise of the address clock ACLK.

After that, in response to the rise of the address clock ACLK,
The same calculation as above is performed, and the main scanning step is advanced one step at a time, and address signals are sequentially output. In other words, the X address is rxsta+2mdx, xsta+
3mdx, -J are sequentially output, and rysta+2mdy, ysta+3mdy, -J are sequentially output as Y addresses.

When the address advances to Pl, the main scanning end signal MSEND from the line status circuit 38 is outputted to the CPLJ 12 via the output buffer 61. Then, the timing controller 35 outputs the clock corresponding to the next line to the X address generation section 39 and the X address generation section 41. As a result, in response to the rise of the address clock ACLK, the X AT 12 generation unit 39 calculates the address in the X direction (X address) by performing calculations according to the supplied parameters, and calculates the two-dimensional address. do. For example, as a scanning address, Pa − is moved from P6 by one step in the sub-scanning direction.
The main scanning direction address [X5ta+5dXJ is calculated. In addition, the Y-axis 92 generation unit 41 calculates the address in the Y direction (
Y address) and calculate the two-dimensional address.

For example, an address "ysta+5dyJ" in the sub-scanning direction of Pa+1 steps is calculated as the scanning address. At this time, the sub-counter 37 is counted up in response to the rise of the address clock ACLK.

Then, the X address from the X address generation section 39 is rounded off by a rounding circuit 43 and supplied to an address conversion section 47 . Further, the Y address from the Y atto 92 generating section 41 is rounded off by a rounding circuit 44 and then supplied to an address converting section 47 . Then, the address conversion unit 47 converts the supplied X1Y address into a one-dimensional address signal (BAO to BA25), and sends the selection circuit 4
8. Thereby, the address signals AO to A25 output from the output buffer 50 are supplied to the display memory 17a.

Further, the main counter 36 is counted up in response to the rise of the address clock ACLK.

After that, in response to the rise of the address clock ACLK,
The same calculation as above is performed, and address signals obtained by advancing one main scanning step at a time are sequentially output.

After the address advances to Pl-, in response to the rise of the next address clock ACLK, the X address generation section 39 and the Y address generation section 41 move the scanning address from Pa by two steps in the sub-scanning direction. rxsta+2sdxJ and rysta+2sdyJ are output.

Thereafter, the same operation as above is repeated.

In this way, as shown in FIG. 10, quadrilateral (rectangular) SSW addresses are sequentially output.

In this case, when drawing a diagonal line, the first address specification is
As shown in FIG. 1, the closest address can always be taken, and the image display corresponding to the address control becomes natural.

As mentioned above, by adding the address rounding part, for example, when rounding is performed using the first decimal place bit, if the first decimal place bit is 0', all bits below this bit will be 'O'. , the integer part remains as it is, and if the first decimal place bit is 1', the address is one step higher by adding 1' to the integer part and setting all the decimal parts to 0'. As a result, the shortest distance approximation of the address can be performed, and a straight line address as shown in FIG. Addresses with few errors can be generated. Roughly speaking, by using the function to specify the bits to be rounded off, in addition to the configuration in which bitmap memory etc. is considered to have 1 bit per pixel, it is possible to consider the same memory system as having 2 bits per pixel or 4 bits per pixel. Even in this case, it is possible to round off in units of 2 bits or 4 bits, and it is possible to generate addresses according to the memory configuration.

〔Effect of the invention〕

As detailed above, according to the present invention, by performing rounding processing, it is possible to generate an integer address close to the calculated address by simply adding simple hardware, and it is possible to generate an integer address close to the calculated address. By making it possible to specify the bits for rounding off more accurately, even if the memory configuration changes, more accurate addresses can be easily generated in the same way as above. We can provide an address control device that can

[Brief explanation of the drawing]

1 to 11 show an embodiment of the present invention, in which FIG. 1 is a functional block diagram, FIG. 2 is a block diagram showing a schematic configuration of a uniform information editing device, and FIG. 3 is an address generation block diagram. FIG. 4 is a diagram for explaining the concept of parameters, FIG. 5 is a diagram showing the schematic configuration of the rounding section, and FIG. 6 is an example of the configuration of the address output from the address generation section. Figure 7 is a diagram to explain the address output from the rounding section, Figure 8 is a diagram showing an example of generating a two-dimensional address, and Figure 9 is a diagram showing the flow of signals in each part. FIG. 10 is a flowchart for explaining an example of rectangular processing, FIG. 11 is a diagram for explaining an example of addresses l1llID for diagonal lines, and FIG. 12 is a diagram for explaining an example of rectangular processing. FIG. 3 is a diagram for explaining an example. 14...Page memory, 17a...Display memory, 1
8...Address generation section (address control device, 31.
...Parameter register group, 32, ...110 buffer, 33.49...Input buffer, 34...
Decoder, 35... Timing controller, 36...
・・Main counter, 37・・Sub counter, 38・
...Line status circuit, 39...X address generation section, 40.42.45.46.50.53.61...
Output buffer 7.41... Y at 92 generation part,
43.44...Rounding circuit (address processing section), 4
7... Address conversion section, 48... Selection circuit, 51.
... Clipping controller, 52 ... Clipping status, 62 ... CPU interface, 7
DESCRIPTION OF SYMBOLS 1... Line control part, 72... Clipping control part, 73... Address calculation circuit, 101... Mode specification register, 102-... Decoder, 103a-103
i...andgate, 104.105.106.10
7... Adder, OPMD... Operation mode, SN...
・Number of sub-scanning repetitions, MD...Number of main-scanning steps, DX
...Number of a1 scanning steps, MN...Number of main scanning repetitions, xW...X direction scanning width, X5TA, YSTA...
Start address, MDX, MDY...Number of main scanning steps, SDX, SDY...Number of sub-scanning steps, CXI
, CYI, CXE, CYE, CMOD-')') Ping address, NA... Direction code data, 0PCD.
...Operation command, AGEN8...Address calculation enable signal, RPT...Recalculation signal, MD...Number of main scanning steps, C1, CE... Clipping address. Appearance Agent Patent Attorney Takehiko Suzue Parameters Figure 1 tn 4 Figure 9 Figure 10 Figure 11 Exit x, , , , , , , . Y... Two knee seven out (a) (b) (C) Figure 12

Claims (5)

[Claims] (1) In an address control device that generates an address that specifies the data access position in an information storage device, there is a parameter register group that stores parameters necessary for address generation, and address calculation using the parameters stored in this parameter register group. and an address generator that outputs the result of this calculation as an address, and an address process that rounds the address by carrying or truncating the address supplied from the address generator, depending on the value of a specific bit. An address control device comprising: a part; (2) Claim 1 characterized in that a mode designation register is provided for designating the bits for rounding off.
Address control device as described in section. (3) The parameters stored in the parameter register group include the scanning width in the main scanning direction, the start address of address calculation, the address increment value in the main scanning direction, the address increment value in the sub-scanning direction, the number of repetitions in the main scanning direction, The address control device according to claim 1, characterized in that the number of repetitions in the sub-scanning direction, an address specifying an arbitrary area, and an address calculation mode are provided. (4) The address control device according to claim 1, wherein carry or truncation processing is performed depending on whether the value of the specific bit is 1 or 0. (5) The address control device according to claim 4, wherein a carry process is performed when the value of the specific bit is 1, and a truncation process is performed when the value of the specific bit is 0.