JPS62281675A - Shading correction deciding circuit - Google Patents

Abstract

PURPOSE:To decide with high accuracy whether a shadihg correction is carried out properly or not by dividing the output of an image sensor into the prescribed number of sections and detecting the maximum and minimum values of the output of the image sensor within those divided sections. CONSTITUTION:A white reference plate is read by an image sensor 21 and the read signals equivalent to a single line are divided into the prescribed number of sections by a dividing circuit 52. Both the maximum and minimum values of the read signal in each section are detected by a maximum/minimum detecting circuit 51 with all sections equivalent to a single line. A deciding part 54 checks whether the maximum and minimum values of each section detected by the circuit 51 are coincident or not with the reference data set previously to the part 54. Then it is decided that the shading correction is not properly carried out if just a single discordant section is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a schema correction determination circuit applied to a scanner device equipped with an image sensor or the like.

BACKGROUND OF THE INVENTION FIG. 8 is a block diagram showing a shading correction circuit including an example of a conventional shading correction determination circuit.

In this shading correction circuit, an analog signal read by an image sensor 1 is amplified to a predetermined level by an amplifier 2. This analog signal is then converted into a digital signal by the A/D converter 3. Thereafter, this digital signal is input to the shading correction section 16.

The shading correction unit 16 includes a RAM 4 that stores a signal for one line when a color reference plate such as a reference white plate is read with the image 7/s1, and a RAM 41 that stores data proportional to the reciprocal of the stored signal content. ROM 5 (!:) This data is written in advance and is taken out according to the output of the RAM 4. Multiplier 6 that multiplies and combines the obtained data
It is designed to correct a decrease in the amount of peripheral light due to the (COS) law of the optical system or bit variations in the output of the image sensor 1.

A comparison circuit 16 is connected to the output side of the RAM 4.

The comparison circuit 16 can change the initial value and
is stored, and data A output from the latch 7 (hereinafter referred to as latch data) and data B output from the RAM 7 (hereinafter referred to as RAM data) are input, and both data A is input. , B>
A (here, the level of latch data A and the level of RAM data B are assumed to be A and B, respectively, for convenience), then the comparator 8 outputs a signal indicating this, and the comparator 8 receives the output signal of the comparator 8. It has a gate 9 for storing RAM data B in the latch 7.

A comparator 1o is connected to the output side of the latch T. The comparator 10 is preset with reference preset data D, and the latch data A finally output from the latch 7 is compared with this preset data D. When the latch data A is larger than the preset data D, outputs a signal indicating this to the CPU (not shown), indicating that the shape ink correction is not being performed properly.
This prevents shading correction from being performed in this state.

Note that the above example is an example in which the maximum value of the output of the image sensor 1 is referred to to determine whether shading correction is possible, but the minimum value or both are referred to to determine whether shading correction is possible. It is also possible to determine.

When making a judgment by referring to the minimum value, write the maximum value data (for example, rF'FJ in hexadecimal for an 8-bit circuit) in latch 7 in advance, and check that A>B when compared by comparator 8. When gate 9 is opened, RAM data B
is stored in the latch 7. Further, in this case, when the comparison in the comparator 10 determines that A<D, the comparator 10 outputs a signal to the CPU to the effect that shading correction cannot be performed normally in this state.

Further, when making a determination by referring to both the maximum value and the minimum value, the above-mentioned methods are used in combination.

Problems to be Solved by the Invention By the way, when the image 7/S 1 reads only the reference white plate 100, the outputs of this S/S will not be at the same level, but for example, as shown in FIG. 9, the maximum value Vdmax and the minimum value It is represented by a curve according to the (008)' rule with a value Vdm1n, and shape ink correction is performed based on this curve. However, in such a case, a foreign object 101 may be placed on the reference white plate 100 as shown in FIG. 13, and the reference white plate 100 may be read in this state. In this case, the processor output becomes a concave curve as shown in FIGS. 10 and 11 (the level vB at the bottom of the concave is the first
high in Figure 0 and low in Figure 11). For this reason, when making a determination with reference to the maximum value Vdmax, the depressions are overlooked, and the sensor outputs shown in Figures 9, 10, and 11 are treated as being equal, and appropriate shading correction is not performed. . If the method refers to both the maximum value Vdmax and the minimum value Vdm1n, the processor output shown in FIG. When a processor output as shown in FIG. 10 is obtained, it is treated as equivalent to the 7/S output shown in FIG. 9, and proper shading correction is not performed.

For example, if the amplifier 2 shown in FIG. 8 is damaged, the first
As shown in Figure 2, the output may become constant. In this case, it is impossible to determine whether shading correction is correctly performed using the method described above.

The present invention has been made in view of the above problems.

Detection is performed according to the image output waveform.

It is an object of the present invention to provide a shading correction determination circuit that can accurately determine whether shading correction is properly performed through this detection.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention includes a dividing circuit that divides a read signal of an image sensor 1 rai/min into a predetermined number of sections;
A maximum/minimum detection circuit that detects the maximum and minimum values of the read signal in each section divided by this division circuit, and
The apparatus includes a determination section that compares the maximum value and minimum value detected by the minimum detection circuit with preset reference data, and determines whether or not shading correction can be performed based on the comparison result.

The working white reference plate is read by an imager, and the reading signal for one rhino is divided into a predetermined number of sections by a dividing circuit. The maximum and minimum values of the read signal in each section are detected by a maximum/minimum detection circuit for all sections for one line. The maximum value of each section detected by the maximum/minimum detection circuit,
The determination unit compares each section of one line to determine whether the minimum value conforms to reference data preset in the determination unit. If there is even one section that does not match, it is determined that shading correction is not performed appropriately.

Embodiment FIG. 1 is a block diagram showing a shading correction circuit including a shading correction determination circuit according to an embodiment of the present invention.

In this shading correction circuit, the image sensor 21
The analog signal obtained by reading is amplified to a predetermined level by an amplifier 22 and converted to a digital signal by an A/D converter 23. This digital signal is input to the shading correction section 50.

When a color reference plate such as a reference white plate is read by the image processor 21, the shading correction unit 60 includes a RAM 24 that stores one line of this reference read signal, and a correction proportional to the reciprocal of the reference read signal stored in the RAM 24. It has a ROM 25 in which data is written in advance, and a multiplier 26 that multiplies the read signal of the image sensor 21 outputted via the A/D converter 23 by the correction data of the ROM 26. The reduction in the amount of peripheral light according to the 008 rule or the bit variation in the output of the imager/sustainer 21 is corrected and outputted.

A maximum/minimum detection circuit 51 is connected to the output side of the RAM 24 via a buffer 27. The maximum/minimum detection circuit 61 includes six detection circuits 511.512. ...616. Detection circuit 511.512. ...5
16 correspond to each section (described later) of the reference read signal of the image sensor 21, 1, 2, . . . . are provided corresponding to each of 6. Further, the shading correction unit 50. A division circuit S2 is connected to the maximum/minimum detection circuit 61. Then, the dividing circuit 52 outputs six reference reading signals (sensor outputs) from the image sensor 21 as shown in FIG. Section 1.2.・
. . . is divided into 6 sections, and is input to detection circuits 511, 612, . . . 516 corresponding to each section,
Here, the maximum value and minimum value of each section are detected, and the maximum value and minimum value are output to the CPU 54 via the bus rhino 53 for each detection circuit 611, 512, °°°...°516. .

The partitioning circuit 52 is based on the oscillator 28 and the excavator 28.
A counter 29 sends an address signal to the AM24 and a signal equivalent to this address signal to the decoder 3o, and a counter 29 that sends an address signal to the AM24 and a signal equivalent to this address signal to the decoder 3o, and a counter 29 that sequentially enables section 1 enable, section 2 enable, . . . section 6 based on the input signal. outputs enable and detects circuits 511, 512. . . 516 and is equipped with a decoder 307 that switches and operates the decoder 307.

Detection circuit 511 (detection circuit 612...516
has the same function as the detection circuit 611, and will be explained using the detection circuit 611 as a representative. ) is inputted from the latch 31 whose initial value can be changed and in which “0” is initially stored, the data (hereinafter referred to as latch data) A output from this latch 31, and the buffer 27, and is input to this detection circuit 611. Corresponding section 1 reference read signal (hereinafter referred to as RAM data) B
and compares latch data A and RAM data B to determine whether A>B or A<B (the level of latch data A is set to A,
A comparator 32 outputs a signal indicating the level of RAM data B (B is the level of RAM data B), and a signal indicating A>B or A<B is input, and the output signal is set to the maximum value, for example, according to maximum value detection or minimum value detection. A switching unit 36 selects either a signal indicating A<B at the time of detection, or a signal indicating A>B at the time of minimum value detection, and outputs this to the gate 34 via the OR circuit 33. Data corresponding to the output signal of the OR circuit 33 is sequentially stored in the latch 31 by the gate 34.

Furthermore, the detection circuit 511 includes a buffer 36 on the output side of the latch 31, and when the latch for section 1 is completed, this stored data is transferred to 0PU via the pass line 53.
64.

Note that six detection circuits 511, 512. A buffer 37 is connected to the CPU 64 via a bus line 153 to the maximum/minimum detection circuit 51 having an angle of 616 degrees, and a latch 31, a comparator 32, and a gate 3 are connected to the CPU 64 via a bus line 153.
4. The buffer 36 and the switching section 36 are switched and set to perform maximum value detection and minimum value detection, respectively. That is, when detecting the maximum value, the latch 31 is set to "00" (also 2).The switching unit 35 is set to output a signal indicating A<B. No signal is output from the A/D controller/harter 23, and A<
By outputting the signal indicating B, RAM data B, which is larger than latch data A, is sequentially stored in the latch 31, and finally the maximum value of section 1 is stored, and this maximum value is detected by the detection circuit 511. It turns out. On the other hand, when performing minimum value detection, the latch 31 is set to "FF" (hexadecimal display when the data bus is 8 bits. In this embodiment, 8 bits is taken as an example, but data buses other than 8 bits are , the highest value corresponding to the number of bits is displayed.), and the switching unit 35 is set to select the signal indicating A)B. Then, the minimum value is detected by the detection circuit 511.

The CPU 54 presets each section 1 as shown in FIG.
,2. ...The reference minimum value BVmin and reference maximum value BVmax are set as reference data every 6, and this CP
The data input to U54 is the standard maximum value 3Vma.
It is determined whether or not x falls within the range indicated by the reference minimum value B Vmin. That is, the maximum value is detected by the detection circuits 511, 512. ...616, the maximum value obtained from this is compared to see if it exceeds the reference maximum value BVmax, and the detection circuit 6 detects the minimum value.
11.612. ...516, it is compared whether the minimum value obtained from this is less than the reference minimum value BVmin. These comparisons are made using six detection circuits 5
11.512. . . 516, and the comparison result is determined as the reference maximum value BVmax,
If the value is not within the range indicated by the reference minimum value BVmin, it is determined that the shading correction is not performed properly. Note that in this embodiment, the division circuit 52.
The maximum/minimum detection circuit 51.0 PUes4 constitutes a shaped correction determination circuit.

In the shading correction circuit configured as above,
As shown in Figure 3, the reference white plate is connected to the image sensor 2.
1 is read, and this read signal is stored in the RAM 24. Next, section 1 enable is output from the division circuit 52, the detection circuit 511 corresponding to section 1 is enabled, and the latch 31 is set to "
oo'' (when 8 bits) is written. Next, RAM
The stored contents of 24 are read out. Then, latch 31
The maximum value of the output of the RAM 24 is held, and this maximum value is read out to the CPU 54 via the pass line 63. Next, "F'F" is written in the latch 31, and the contents of the RAM 24 are read from this state. Then, the minimum value of the RAM 24 is held in the latch 31. This minimum value is read out to the CPU 54 via the pass line 53. and,
The maximum value and minimum value of the read signal in section 1 are compared with the reference maximum value BVmax and reference minimum value BVmin of section 1, and the reference maximum value BVmax and reference minimum value BVmin are determined.
When it is determined that the value is not within the range indicated by , it is determined that shading correction is not performed properly.

Similarly, the detection circuit 512,
613 . . . 616 operate in sequence, and the maximum and minimum values of the reference read signal in each section are detected and compared and determined by the CPU 54 with the reference data.

Through such an operation, if there is a depression at a position corresponding to section 3 as shown in FIG. 4, for example, the detection circuit 5i13 detects that there is a minimum value smaller than the reference minimum value BVmin of this section 3. Ru. In this case, it is determined that shading correction is not performed properly.

Further, in the case where there is a flat output as shown in FIG. 6, it is determined that appropriate shading correction is not performed in the same way as described above.

Further, as shown in FIG. 5, if there is a depression in the part corresponding to section 32 and section 4, the detection circuits 513 and 514
, 4 are detected, which are smaller than the respective reference minimum values BVmin. As a result, it is determined that the correction by this shading correction section 50 is not performed properly.

Note that in this embodiment, the detection circuits 511, 612. ...5
Although the case where six detection circuits 16 are provided has been described, it is not necessarily necessary to provide a plurality of detection circuits. This example will be explained with reference to FIG.

This shading correction determination circuit takes in the output of the decoder 3o via the buffer 38 to the CPU 54. In this circuit, first, "00" is written into the latch 31 through the buffer 37.

Next, the output of the RAM 24 is read and the output of the decoder 30 is C! The maximum value of each section is first detected while being monitored by PUs4. Next, it passes through the buffer 37 to the latch 31.
FF" is written, and the minimum value of each section is detected and written to the CPU 54.Based on these maximum and minimum values, the CPU 54 determines whether shading correction is properly performed. By adopting such a configuration, the amount of hardware can be reduced.

Effects of the Invention As is clear from the above explanation, the present invention divides the output of the image processor into a predetermined number of sections, and detects the maximum and minimum values of the image sensor output within the sections. Since detection is performed according to the sensor output waveform, it can be determined with high precision whether shading correction is being performed appropriately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a shading correction circuit equipped with a shape ink correction determination circuit according to an embodiment of the present invention;
FIG. 2 is a conceptual diagram showing an example of the operation of the division circuit shown in the same figure, FIG. 3 is a timing chart showing an example of the operation of the circuit shown in FIG. A waveform diagram showing one example, FIG. 5 is a waveform diagram showing another example of the read signal of the same image processor, FIG. 6 is a waveform diagram showing still another example of the read signal of the same image processor, and FIG. FIG. 8 is a block diagram showing a shading correction circuit including an example of a conventional shading correction determination circuit, and FIG. 9 is a block diagram showing a shading correction circuit including an example of a conventional shading correction determination circuit. A waveform diagram showing the sensor output when reading the reference white plate, Fig. 10 is an image of the same figure. The figure is a waveform diagram showing the sensor output when the image processor in the same figure reads a reference white plate with a foreign object placed on another part, and Figure 12 is a waveform diagram obtained when the amplifier in Figure 7 is damaged. FIG. 13 is a conceptual diagram showing a state where a foreign object is placed on the white reference plate.

Claims (1)

[Claims] dividing means for dividing the read signal for one line of the image sensor into a predetermined number of sections; maximum/minimum detection means for detecting the maximum and minimum values of the read signal for each section divided by the dividing means; - A determination unit that compares the maximum value and minimum value detected by the minimum detection means with preset reference data and determines whether or not shading correction can be performed based on the comparison result. A shading correction determination circuit.