JPS62278818A - Programmable logical array - Google Patents

Abstract

PURPOSE:To attain the whole testing and to shorten a test time by dividing to the part circuit of the suitable number of the input determined from a test speed and a test time when the number of the input is many, and testing a logical array for respective part circuits. CONSTITUTION:A part array 12 to realize a logic for a test is added to prevent the redundancy defect from occurring by the dividing. In the part, by adding a mutually exclusive OP concerning the input of the test between respective product term lines to link to the same output line, the occurrence of the redundancy defect can be prevented. For example, when the part array 12 is included in a part circuit as C3=C4=1, at product term lines 101 and 104 of the left edge and the fourth from the left, (x1+C1) (the inverse of x2+c2) (the inverse of y1+ct) (the inverse of y2+ct) and (the inverse of x2+c2) (y1+ct) (the inverse of y2+ct) are obtained and the inclusive relation is eliminated. In addition to the part circuit in which the c3=c4-1 is obtained, the part circuit, in which c1=c2=1 is obtained, is tested, thereby, obtaining the whole test.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to programmable logic arrays (hereinafter referred to as PLA).

[Conventional technology]

Conventional PLA testing requires the use of a large computer for a long time to generate test patterns, the use of a high-end tester to apply a large number of test patterns at high speed, and to determine the pass/fail in a short time. As a result, testing costs were extremely high. For this reason, various testability techniques have been proposed for the purpose of reducing test costs.

One of them is a simple method that adds all 2'' input vectors once to a combinational circuit with n inputs, compresses the output with a linear feedback shift register, and compares the final value with the expected value to determine pass/fail. There is a test method.

[Problem that the invention seeks to solve]

The conventional test method for PLA described above has a problem in that the test time becomes extremely long as the number of inputs n becomes large.

The purpose of the present invention is to select an appropriate number of inputs (for example, 10M) determined from the test speed and test time when the number of inputs is large.
If the frequency is several seconds at Hz, the PL is divided into 20 to 25) subcircuits and the above test is performed for each subcircuit to enable the overall test and shorten the test time.
The goal is to provide A.

[Means for solving problems]

The programmable logic array of the present invention includes a group of external input signal decoders with means for controlling the decoding function;
a programmable AND array having a group of product term lines that generates an arbitrary AND of the output signals of the decoder group; and a programmable AND array that has a group of output lines that generates an arbitrary OR of the output signals of the AND array. A programmable OR array, a portion of the decoder group and a corresponding portion of the AND array are used to establish an exclusive relationship between each defined product term line of the product term line group. It is configured to include a test AND array to which test logic is added, and an output register that functions as a linear feedback shift register during testing.

[Effect]

The AND array is divided and tested using the control function provided in each decoder. Each partial circuit consists of a part of the AND array for realizing the original logic function, an AND array added for testing, and an OR array, and the number of inputs is kept below an appropriate value. do. For this partial circuit,
All input vectors are added once and the output response series is compressed with an output register that functions as a linear feedback shift register under test mode. For each partial circuit, the final value of this test is compared with the expected value to determine whether the entire circuit is good or bad.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, 1 is a programmable AND array;
11 is a partial array for realizing normal logic; 12 is a partial array for realizing test logic; 2 is a programmable OR array; 31 to 36 are decoders; 4 is an output register; 101 to 106 are Product term line, 201-20
3 is the output line, 311-312 are the decode lines, X4 to Xl
is the normal input signal, y1 to y2 are the test input signals, c
l"'-c4 and C0 are decoder control signals, f1 to f
3 is an output signal, and S is a mode switching signal.

FIG. 2 is a circuit diagram of the decoder 31 of FIG.
1 is an inverter, and 502 to 503 are OR gates. In FIG. 2, OR gates 502 and 503 respectively execute the operation Xi +C1, -ma]''+C1, and the results are output to decode lines 311 and 312. However, + means logical sum, and - means Hail the negation of logic. The same applies to decoders 32-36.

FIG. 3 is a circuit diagram of the output register 4 in FIG.
0 to 42 are NOR gates, 43 to 46 are exclusive OR gates, and 47 to 49 are D type flip-flops. In FIG. 3, when the mode switching signal S is 1 (
In normal mode), the signals on output lines 201-203 are stored in D-type flip-flops 47-49, respectively. When S is 0 (in test mode), the feedback loop is activated and the output lines 201 to 201 are activated in this circuit, which functions as a linear feedback shift register.
The signal sequence appearing at 203 is compressed.

It is known that when the number of registers is m, the missed error rate when compressing using linear feedback shift registers is about 21 (0.4% when m = 8) (Heuret Paracard・Journal (Hewl
ett-Packard Jour [Ial.

pp, 2-8. May 1977)), therefore, if m is made large to a certain extent, this oversight will not actually be a problem.

When the number of output lines is small, the oversight rate can be improved by adding a dummy output register to make m apparently larger.

Referring again to FIG. 1, in the logical product array 1, each product term line 1
In 01 to 106, the AND of the signals of the decode lines where devices (corresponding to marks) are present is generated, and in the OR array 2, the presence of devices (corresponding to × marks) is generated in each output line 201 to 203. A logical sum of the product term line signals is generated. Therefore, normal mode (C□~C4=Q
, Ct=1), then fl=xlX4 +xI X2X3 +x27Tf2
= 1] ηX4 - stone ball - t'3 = xl xSX4 +X2X4 +xI X3
becomes.

Now, if C3=C4=Ct=1, the input xl, C1
, x2. A partial circuit relating only to C2 is obtained. In this partial circuit, an inclusive relationship is established that is the logic realized by the left end and the fourth product term line 101 and 104 from the left, and the product term line 101 at the left end is redundant. Therefore, a failure in a device existing at the intersection of this product term line and each decode line cannot be detected.

The partial array 12 for implementing test logic is added to prevent such redundant failures from occurring due to division. In this part, by adding mutually exclusive logic regarding the test input between each product term line connected to the same output line, the occurrence of redundant faults as described above can be prevented.For example, if C3=c4=1 When the partial array 12 is included in a partial circuit, the leftmost and fourth product term lines 101 and 104 from the left (xt
+C,>(X2 +c2)(y+ +ct)(y
z +ct), (X2 +C2)
(y+ +ct)(yz+ct), and the inclusion relationship disappears. If the partial circuit with C3=02=1 is tested in addition to the partial circuit with C3=04=1, the entire test is completed. Although the case of the 1-bit decoding method has been described above, the case of the 2-bit decoding method can be similarly considered.

〔Effect of the invention〕

As mentioned above, according to Ippon Haimei, by adding simple test hardware, a large-scale PLA can be divided and tested in a short time, and test patterns can be generated using a large-scale computer. Since there is no need to compare output responses successively, test costs can be significantly reduced.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a circuit diagram of the decoder 31 shown in the figure, and FIG. 3 is a circuit diagram of the output register 4 shown in FIG. 1... logical product array, 11.12... partial array,
2... Logical sum array, 31 to 36... Decoder, 4
...Output register, 101-106...Product term line, 2
01-203...Output line, 311-312...Decode line, 40-42...NOR gate, 43-4
6...Exclusive OR gate, 47-4...D type flip-flop (F/F), 501...Inverter, 502-503...OR gate, x1-x4
...Normal input signal, yr-y2...Test input signal, C1-C4, Ct...Decoder control signal, f1
3...output signal, S...mode switching signal. Rate / Figure 2, Figure 3

Claims (1)

[Claims] a programmable AND array having a group of external input signal decoders having means for controlling a decoding function; a group of product term lines for generating an arbitrary AND of output signals of the decoders; and the AND array; A programmable disjunction array having a group of output lines that generates an arbitrary disjunction of a group of output signals, and a portion of the decoder group and a corresponding portion of the AND array are used to It is characterized by including a test logical AND array that adds test logic having an exclusive relationship between each defined product term line of the line group, and an output register that functions as a linear feedback shift register during testing. Programmable logical array.