JPS62278675A - Transfer device for picture data - Google Patents

Abstract

PURPOSE:To transfer even picture data on an optional memory area of a 1st picture memory means to a 2nd picture memory means in the form of an optional reduced picture, by adding a circuit that detects the position of the picture data and then sets the transfer style to be executed next in response to the detected position of the picture data and therefore dividing and reducing optionally a picture. CONSTITUTION:A skidding circuit 22 counts down a counter 33 every time the picture data is skidded by a picture element and sets both RC and selection signals at H when the count value of the counter 33 is equal to zero. At the same time, the clock signal supplied to the counter 33 is masked. While an address selection circuit 23 switches the addresses delivered to a microprogram memory 24 to the values received from a latch 11 and a sequencer 12 in response to a fact that the selection signal received from the circuit 22 is set at H. Therefore the thinning, skidding and thinning are carried out to the transfer of the 2nd picture data, for example, against the picture data that is transferred so that the picture data 60 is expensed into a picture 61. Then the picture data are transferred continuously to obtain a reduced picture 62.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to an image data transfer device.

[Conventional technology]

For example, compressed image data that is sequentially output from an image storage device is decompressed, and the decompressed image data that is sequentially output is controlled by various microprograms and arbitrarily stored in the frame memory of the display. The applicant has proposed an image data transfer device having a structure as shown in FIG. 8 as an image data transfer device that thins out and transfers images so that they become reduced images. This image data transfer device includes an image storage device 1 that stores compressed image data and transfers it sector by sector, and an image storage device 1 that decompresses the compressed image data output from this image storage device 1. an image data compression/expansion circuit 2 that performs image data compression/expansion; a thinning circuit 3 that is controlled by a microprogram and thins out the expanded image data sequentially output from the image data compression/expansion circuit 2 into an arbitrary reduced image; and a thinning circuit 3 that is controlled by a microprogram. direct memory access that controls the image data compression/decompression circuit 2 and performs DMA transfer of image data by generating discontinuous addresses according to predetermined rules so that an arbitrary reduced image is created on the frame memory 5 of the display 4. It consists of a controller (DMAC) 6.

FIG. 9 shows a circuit configuration of a part of the thinning circuit 3 and DMAC 6 in the image data transfer apparatus shown in FIG. 8. This circuit includes a latch 11 that stores an upper address of a microprogram to be executed that is input from an input device such as a keyboard (not shown) through a processor (not shown), and a latch 11 that stores a lower address of a microprogram to be executed in response to the execution of the microprogram. a sequencer 12 that controls the flow of microprograms; a microprogram memory 13 that stores microprograms for various transfers and outputs microprograms according to addresses given from the latch 11 and the sequencer 12; Pipeline register 14 that outputs in synchronization with the lock that executes the output microprogram
, set the number of lines (number of pixels in the vertical direction) of the image to be transferred, set the line counter 15 that counts down every time one line is transferred, and the number of columns (number of pixels in the horizontal direction) of the image to be transferred. , and a column counter 16 that counts down every time one pixel is transferred.

[Issues that the invention attempts to violate]

However, it has been found that the image data transfer device described above has the following points to be improved.

That is, when an image is arbitrarily divided and compressed, and these image data are allocated and stored in an arbitrary storage area of the image storage device 1, each piece of image data is read out and decompressed, and the decompressed data is stored. If you thin out the image data that has been transferred and transfer it so that it becomes the desired reduced image, it will not be possible to connect the transferred image as a reduced image because it is not known where in the image the transferred image ≠ - data is, and the reduced image will not be transferred normally. It may not be possible.

This invention was made with a focus on these problems.
To provide an image data transfer device appropriately configured to transfer image data arbitrarily divided and compressed and stored in arbitrary storage areas so as to obtain a normal arbitrary reduced image. The purpose is to

[Means and operations for solving the problem] In order to achieve the above object, the present invention provides a method for storing image data that is provided between the first image storage means and the second image storage means and transferred therebetween. an image data compression/expansion unit that compresses or expands the image data; a transfer control unit that transfers the image data expanded by the image data compression/expansion unit to the second image storage unit as it is or as a reduced image; and the image data Transfer format selection means for detecting at which position of the image the image data expanded and transferred by the compression/expansion means is and sets the transfer format to be executed next;
Image data is directly transferred between the first image storage means and the second image storage means.

〔Example〕

FIG. 1 shows the configuration of a circuit corresponding to the circuit shown in FIG. 9, which is a main part of an embodiment of the present invention, and the overall configuration is the same as that of FIG. 8.

In this embodiment, a latch 11 stores an upper address of a microprogram to be executed that is manually inputted from a human-powered device such as a keyboard (not shown) via a processor (not shown), and an expanded address sent from a data compression/expansion circuit 2 is used. A latch 21 stores the upper address of a program for performing a blank feed without transferring it to the frame memory 5 even if it receives image data, and a latch 21 stores the upper address of the program to perform a blank feed without transferring it to the frame memory 5. a sequencer 12 that controls the flow of the data; a jump feed circuit 22 that determines whether or not to perform jump feed in the processor; , the address select circuit 23 for selecting from among the addresses inputted from the latch 21 and the sequencer 12, and microprograms for various transfers and idle feeds. A microprogram memory 24 that outputs a microprogram, a pipeline register 14 that outputs a microprogram manually input from the microprogram memory 24 in synchronization with a lock, and the number of lines of an image to be transferred are set; A line counter 15 that counts down every time one line is transferred, a buffer 25 that outputs the value of this line counter 15 to the processor, and a column that sets the number of columns of the image to be transferred and counts down every time one pixel is transferred. A counter 16 and a buffer 2 for outputting the value of this column counter 16 to the processor.
6.

FIG. 2 shows a circuit configuration of an example of the idle feed circuit 22 shown in FIG. 1. The idle feed circuit 22 includes a latch 31 that stores data sent from the processor in response to a mode signal from the processor, and a latch 31 that stores data sent from the processor in response to a mode signal from the processor, and a latch 31 that stores data sent from the latch 31 and data from the processor in response to a load signal from the processor. a selector 32 for selecting;
A counter 33 that sets data from the selector 32, counts down every time one pixel is transferred, and outputs an RC signal when it reaches zero, and an inverter 34 and a gate 35 for controlling the load signal to the counter 33. ,
The address select circuit 23 responds to the mode signal from the processor, the load signal, and the RC signal from the counter 33.
Flip-flop 3 for controlling the select signal to
6. 37 and gate 38, and gates 39 and 40 and an inverter 41 for controlling the clock signal input to the counter 33 in accordance with the output of the flip-flop 36 and the select signal.

FIG. 3 shows an example of image data transfer in this embodiment. This is 640 columns x 48 lines.
The image of 0 is arbitrarily divided into four parts, each of which is compressed, and the image data stored in the four storage areas of the image storage device 1 is sequentially read out and decompressed into 640x.
The expanded image 50 of 480 pixels is further transferred to the frame memory 5 so as to become a reduced image.

The operation of this embodiment will be explained below based on the image transfer shown in FIG.

First, the upper address of the start address of the microprogram according to the transfer format manually entered from a keyboard (not shown) or the like through the processor is inputted into the latch 11, the upper address of the start address of the microprogram for empty feeding is inputted into the latch 21, and the transfer destination is inputted manually through the processor. The start address of the frame memory 5 of
Set it to MAC6.

Next, the processor sets the idle transfer circuit 22 to the initial state, sends commands such as the read start address and the number of transfer sectors to the image storage device 1 to transfer the image data 51, and sends the image data 51 to the DMAC 6. Instructs to start DMA transfer. In response to this, the DMAC 6 puts the processor in a hold state and starts DMA transfer.

FIG. 4 shows each signal in the initial state of the idle feed circuit 22, and each signal in the figure corresponds to each signal line in FIG. 2.

Since the select signal sent from the idle feed circuit 22 is at a high level (H), the address select circuit 23 selects the latch 1.
1 and the sequence 12 are selected and outputted to the microprogram memory 24, and as a result, at the beginning of the microprogram output from the microprogram memory 24, the line counter 15 has the number of lines 480, and the column counter 16 has the number of columns 640. is set, and the image data 51 is transferred according to the subsequent microprogram.

The image data 51 to be transferred is input to the image data compression/expansion circuit 2, subjected to expansion processing so as to become an image 52, and sequentially outputted to the thinning circuit 3. The thinning circuit 3 thins out the sequentially inputted image data and stores it in the frame memory 5 under the control of discontinuous addresses according to a predetermined rule from the DMAC 6 so as to form a reduced image 53. For example, if the image reduction ratio is a, image data is transferred at intervals of a for the first line of a lines (line indicated by a broken line in image 50), and the remaining (a-1) lines are empty. By performing the feeding, it is possible to obtain an image of 1/a in both the horizontal and vertical directions. Line counter 15 is 640x48
A countdown is performed each time one line of image data (640) of the 0 image is transferred. In addition, the column counter 16
counts down each time one pixel of image data (640) for one line is transferred, and when the transfer for one line is completed, the number of image data for one line (640) is set again. Therefore, from the values of the line counter 15 and column counter 16, it is possible to know which part of the image is currently being transferred.

When the first image transfer is completed, the OMAC 6 releases the processor from the hold state. The processor checks the values of the line counter 15 and column counter 16 and sets the next transfer format.

Figure 5 shows the flow of processing in the processor.
In the figure, A and B indicate registers within the processor, and a indicates the reduction rate. The processor first controls the buffer 25 to load the value of the line counter 15 into the register A, and determines to which line the transfer has been completed. At this point, if the transfer of the line to be skipped has been completed (A=0)', then the buffer 26 is controlled and the value of the column counter 16 is loaded into the register B. Determine whether the transfer is complete. here,
If the next line has not been transferred yet (B=0)
, select program 71. This means that, for example, the first image data transfer was performed by expanding the image data 51 in FIG. means,
In this case, by selecting the program 71, the processor does not perform any processing on the idle feed circuit 22,
The next image data transfer can be subsequently performed using the same procedure as the first image data transfer.

On the other hand, if the first transfer ends in the middle of the line to be skipped (A<a and A≠0), program 72 is selected. This means that, for example, the first image data transfer expands the image data 54 in FIG.
This is a case where the image data to be transferred is thinned out and transferred to become a reduced image 56. In this case, the processor calculates the number of images that need to be skipped and outputs it to the skipping circuit 22, as well as outputting a load signal. As a result, in the idle feed circuit 22, data from the processor is selected by the selector 32 according to the load signal and set in the counter 33, and the select signal is set to low level (L) to mask the clock signal of the counter 33. remove. FIG. 6 shows the operation timing of the idle feed circuit 22 in this case. In addition, the address select circuit 23
Since the select signal sent from the idle feed circuit 22 is L, the address from the latch 21 and the sequencer 12 is selected and output to the microprogram memory 24. Next, the processor sends a command to the image storage device 1 and instructs the MAC 6 to start DMA transfer of image data. In response, the DMAC 6 puts the processor in a hold state and starts DMA transfer. In this DMA transfer, a microprogram for image data empty feeding is initially executed to perform image data feeding.

In the jump feed circuit 22, the counter 33 counts down every time the image data is skipped by one pixel, and when it reaches zero, the RC
While setting the signal and select signal to H, the counter 33
Mask the clock signal that is input manually. Further, the address select circuit 23 switches the address output to the microprogram memory 24 to the value from the latch 11 and the sequencer 12 in response to the select signal from the idle feed circuit 22 becoming H. As a result, for example, in the second image data transfer, image data 57 in FIG. The image data is then transferred continuously.

On the other hand, if the first transfer ends in the middle of the line where the image data should be thinned out and transferred (A<a, A
"0, and B≠0), for example, the first image data transfer expands image data 57 in FIG. 3 to become image 58, and the transferred image data becomes reduced image 59. When executed, the program 73 is selected. In this case, the processor first calculates the number of pixels that must be transferred and outputs it to the blank feed circuit 22, as well as outputs a load signal. 22 selects data from the processor by the selector 32 in response to the load signal and sets it in the counter 33, and also sets the select signal to L to unmask the clock signal of the counter 33.Next, the processor performs a blank feed. The required number of pixels is determined and outputted to the idle feed circuit 22, and the mode signal is set to H. This mode signal causes the idle feed circuit 2 to
2 stores data from the processor in the latch 31 and sets the select signal to H. FIG. 7 shows the operation timing of the idle feed circuit 22 in this case. The address select circuit 23 receives the select signal from the idle feed circuit 22 at an H level.
Therefore, the addresses from the latch 11 and sequencer 12 are selected and output to the microprogram memory 24.

The processor sends a command to the image storage device 1 and instructs the 0MAc6 to start DMA transfer of image data. In response, the DMAC 6 puts the processor in a hold state and starts DMA transfer.

In this DMA transfer, a microprogram for image data transfer is initially executed to transfer image data. In the idle feed circuit 22, the counter 33 is counted down every time one pixel of image data is transferred, and when it reaches zero, the RC signal is set to H, the select signal is set to L, and
Data output from the latch 31 via the selector 32 is set in the counter 33. Further, the address select circuit 23 switches the address output to the microprogram memory 24 to the value from the latch 21 and the sequencer 12 in response to the select signal from the idle feed circuit 22 becoming L. As a result, the image data is continuously fed. In the jump feed circuit 22, the counter 33 counts down each time the image data is skipped by one pixel, and when it reaches zero, the RC signal and the select signal are set to H,
The clock signal manually input to the counter 33 is masked.

Further, the address select circuit 23 switches the address output to the microprogram memory 24 to the value from the latch 11 and the sequencer 12 in response to the select signal from the idle feed circuit 22 becoming H. This results in
For example, in the second image data transfer, image data 60 in FIG. The image data is then transferred as follows.

〔Effect of the invention〕

As described above, according to the present invention, the image data sequentially outputted from the first image storage means is subjected to expansion processing, and the expanded image data sequentially outputted is then transferred to the second image storage means.
By adding a circuit that detects the position of the image data and sets the next transfer format to be executed in accordance with this to the image data transfer device that thins out and transfers the image data to an image storage means of an arbitrary reduced size. , even if the image is arbitrarily divided and compressed and each image data is stored in an arbitrary storage area of the first image storage means, an arbitrary normal reduced image is stored in the second image storage means. It can be transferred as follows.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the main parts of an embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of an example of the idle feed circuit shown in Fig. 1, and Fig. 3 shows an example of image data transfer. Figure 4 is a diagram showing each signal in the initial state of the jump feed circuit. Figure 5 is a flowchart showing the operation of image data transfer. Figures 6 and 7 are timings of the jump feed circuit in different transfer formats. The chart, FIGS. 8 and 9 are diagrams showing the configuration of an image data transfer device previously developed by the applicant. 1... Image storage device 2... Data compression/expansion circuit 3... Thinning circuit 4... Display 5...
・Frame memory 6...DMAC11...Latch for transfer program start address 12...Sequencer
14...Pipeline register, 15...Line counter 16...Column counter 21...Latch for blank feed program start address 22...Nut feed circuit 23...Address select circuit 24... Micro program memory 25, 26... Buffer Figure 2 Figure 3 Figure 4 H□ Load ■ L Figure 5 Figure 6 ■ Figure 7 ■

Claims (1)

[Claims] 1. Image data compression/expansion means provided between the first image storage means and the second image storage means and compresses or expands the image data transferred between them, and this image data compression means. a transfer control means for transferring the image data expanded by the expansion means to the second image storage means as it is or as a reduced image; transfer format selection means for detecting the position of the data and setting the transfer format to be executed next; An image data transfer device characterized by being configured to perform transfer. 2. The transfer format selection means includes an image position detection means for detecting the position of the image data to be transferred on the image, and a transfer method for setting the transfer format to be executed next based on the output of the image position detection means. Image data according to claim 1, comprising a format setting means and an image data empty feeding means for feeding the image data based on the transfer format set by the transfer format setting means. Transfer device. 3. The transfer control means includes a thinning means for thinning out the image data sequentially output from the image data compression/expansion means according to a predetermined rule, and a thinning means for thinning out the image data sequentially output from the image data compression/expansion means, and a discontinuous address to the second image storage means according to a predetermined rule. 3. The image data transfer apparatus according to claim 1, further comprising address generating means for generating an address. 4. The image data transfer apparatus according to claim 3, wherein the image data empty feeding means, thinning means, and address generation means are configured to be controlled by a microprogram.