JPS6227842A - Memory control system - Google Patents

Abstract

PURPOSE:To decrease the stopping period of the system working which is caused by the repairs of a defective area of a memory, by replacing the defective area of the memory without breaking the power supplies of other devices. CONSTITUTION:If a storage part 26 of a memory 22 has a defective part, a central processing unit 10 delivers a command to a power supply device 50 to cut off the power supply voltage to the part 26. At the same time, the unit 10 delivers an indication to an interface part 24 to cut off logically the part 26. The part 24 can turn off simultaneously both a driver 23a and a receiver 23b by the cut-off signal given from the unit 10 through a common bus since the driver 23a and the receiver 23b have a 3-state structure respectively. Then it is possible for the part 24 to produce a state where no memory 22 exists. In such a way, the part 26 can be replaced without cutting off the power supplies of other parts since the part 26 is separated from the part 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory management system, and particularly to a memory management system in an IF information processing device.

[Conventional technology]

Conventionally, in this type of memory management method, when the existence of a defective part is found as a result of memory test 1 diagnosis, the entire device including the memory is turned off, the defective part is replaced, and then the memory is turned off again. The defective areas were recovered by turning on an IL source.

[Problem that the invention seeks to solve]

In the conventional memory management method described above, it is necessary to turn off the power to remove the defective part, so even if the defective part is in a location unrelated to program execution, it is necessary to restart the program execution from the beginning. There is a drawback that it must be done.

[Means for solving problems]

According to the present invention, a memory device that can be divided and implemented for each central processing fixed capacity connected to a common bus, one or more input/output control devices, and a power supply device that supplies a power supply voltage to each of the devices, respectively. The central processing unit has a function of testing and diagnosing the memory device, and the memory device has an interface unit that connects each of the divided memory devices to the common bus. , and a storage section.

The power supply device cuts off only the power supply voltage supplied to the storage section in response to a command from the central processing unit, and the interface section for the front storage section cuts off the power supply/voltage of the storage section. A memory management method waits for a function that does not affect the common bus, and cuts off the power supply voltage to a storage section of the memory that is determined to be defective as a result of the test and diagnosis by the central processing unit, A memory management method based on exchange can be obtained.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In Figure 1, there are 2 and one embodiment is a central processing bag! 110, a memory device 20, a plurality of input/output control devices 30, 40, and a power supply device 50 that supplies power supply voltage to each device, and includes a central processing unit 10, a memory device 20E, and an input/output control device 130. ,4
0 is connected to the common bus 60.

The memory device 20 is divided into three parts each having a certain capacity, and includes a memory 21 having an interface section 232 and a storage section 25.
and a memory 22 having an interface section 24z and a storage section 26. This memory 21.2
2 has its respective interface sections 23 and 24 connected to the common bus 60 and receives data from the source device 50.
The voltage is applied to the interface section 23.242 and the storage section 25.242.
26 independently.

The central processing unit 10 has a function of independently testing and diagnosing each of the memories 21.22 divided into a certain capacity of the memory device.
A command to cut off only the power supply voltage supplied to each of the storage units 25 and 26 of 2, and a disconnection signal indicating that the power supply of the storage unit is cut off to the interface units 23 and 24ζ are supplied. It has the function of

The power supply unit JT50 has 8 central processing! Based on the command from AT, the power to the storage sections 23 and 24 of the desired memory is cut off.

As shown in Figure 2, the memory interface section 23.24 consists of drivers 23a, (24a) and l/receivers 3b, (24b), and the disconnection signal from the central processing unit is connected to the common bus. 60, and has the function of not affecting the common bus even if the power to the storage unit is cut off.

lol lol Next, the operation of this embodiment will be explained.

In one embodiment of the present invention, the memory 21 and the memory 22 are memory (2) 000 (□++) to 7F.
FF (1s) at address F' (16), 800 (1g) ~
Configure a street address. Now, if there is a defect in the storage section 26 on the memory 22 side, when the central processing unit fio tests and diagnoses the memory, 6 of the 'Plc source voltage supplied to this storage section 26 is detected on the power supply 50 side. Cut off. in this case,
When viewed from the central processing unit 10 and the input/output control unit 30.40, the memory 22 is 000 (1g) to 71! "F(,,)
Even the street address appears to exist.

This is because the central processing bag [10 indicates to the power supply device 50 the wipe number and voltage being supplied to the storage section 26. In the interface section, as shown in Fig. 2, the driver 23a and the 1/sceiver 23b are three-state, and can be turned off at the same time by a disconnection signal sent from the central processing unit through the common bus. It is possible to create a state in which the memory 22 does not exist. When this state occurs, since the storage section 26 is separated from the interface section 24 due to implementation, the storage section 26 can be replaced without turning off the FI source of other parts. Therefore, in this example, 2 OOO (1 g) to 7 FF
As long as a program using only the (ss) address is running, defective memory can be replaced during operation.

〔Effect of the invention〕

As explained above, the present invention enables defective memory to be replaced without interrupting program execution by providing a means for replacing a defective portion of memory without turning off the power to other devices. .

This has the effect of reducing the period during which system operation is stopped due to repair of a defective portion of memory.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a memory management system in Embodiment 2 of the present invention, and FIG. 2 is a detailed diagram showing an interface portion in Embodiment 3 of the present invention. 10...Central processing unit, 20...Memory device, 21.22...Memory, 23.24.
...Interface section, 25.26...
Storage unit, 30.40... Input/output control device, 50
...Power supply device, 60...Common bus.

Claims (1)

[Claims] A central processing unit connected to a common bus; a memory device that can be divided and implemented for each predetermined capacity; one or more input/output control devices; and a power supply device that supplies a power supply voltage to each of the devices, The central processing unit has a function of testing and diagnosing the memory device, and the memory device is configured such that each of the divided memories includes an interface unit connected to the common bus and a storage unit. The power supply device cuts off only the power supply voltage supplied to the storage section according to a command from the central processing unit, and the interface section for the storage section cuts off the power supply voltage supplied to the storage section. The memory management system has a function that does not affect the common bus, and is a memory management system that applies power supply voltage to the memory storage section of the memory that is determined to be defective as a result of the test and diagnosis by the central processing unit. A memory management method that is characterized by being disconnectable and replaceable.