JPS62277751A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62277751A JPS62277751A JP12174486A JP12174486A JPS62277751A JP S62277751 A JPS62277751 A JP S62277751A JP 12174486 A JP12174486 A JP 12174486A JP 12174486 A JP12174486 A JP 12174486A JP S62277751 A JPS62277751 A JP S62277751A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- mask
- semiconductor wafer
- bumps
- printing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 16
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000007639 printing Methods 0.000 abstract description 15
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000005294 ferromagnetic effect Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- FGRBYDKOBBBPOI-UHFFFAOYSA-N 10,10-dioxo-2-[4-(N-phenylanilino)phenyl]thioxanthen-9-one Chemical compound O=C1c2ccccc2S(=O)(=O)c2ccc(cc12)-c1ccc(cc1)N(c1ccccc1)c1ccccc1 FGRBYDKOBBBPOI-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、更に詳述すれば
半導体装置を構成する基板上に半田層を形成する方法に
関するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for forming a solder layer on a substrate constituting a semiconductor device. It is about the method.
従来、この種の方法において、例えばフリップチップの
Ｃｕバンプ上に半田層を形成する場合、第２図に示すよ
うな印刷法を採用している。即ち、第２図（ａｌに示す
ように半導体ウェハ１上に形成されたＣｕバンプ２に対
応してスルーホール１０が形成されたメタルマスク４を
、半導体ウェハ１との間に所定の間隔をもって配置し、
スキージ５によりメタルマスク４に圧力を加えた状態で
スキージ５を移動させて半田ペースト３をＣｕバンプ２
上に印刷し、その後半田ペースト３をリフローさせて同
図（ｂｌに示すように半田層３ａを形成している。尚、
図中６は印刷台であり、８はメタルマスク４の枠である
。Conventionally, in this type of method, for example, when forming a solder layer on a Cu bump of a flip chip, a printing method as shown in FIG. 2 has been adopted. That is, as shown in FIG. 2(a), a metal mask 4 in which through holes 10 are formed corresponding to the Cu bumps 2 formed on the semiconductor wafer 1 is placed at a predetermined distance from the semiconductor wafer 1. death,
While applying pressure to the metal mask 4 with the squeegee 5, move the squeegee 5 to apply the solder paste 3 to the Cu bumps 2.
The solder layer 3a is formed by printing on top and then reflowing the solder paste 3 as shown in the same figure (bl).
In the figure, 6 is a printing table, and 8 is a frame of the metal mask 4.
又、他の方法としては、第３図（ａｌに示すように半導
体ウェハ１上に形成されたＣｕバンプ２に対応してスル
ーホール１０が形成されたメタルマスク４を、半導体ウ
ェハ１上にそのスルーホール１０内にＣｕハンプ２が入
るように配置し、所定の量で形成された半田ボール９を
スルーホール１０内に入れ、その後半田ボール９をリフ
ローさせて同図（ｂ）に示すように半田層９ａを形成し
ている。In addition, as another method, as shown in FIG. The Cu hump 2 is placed in the through hole 10, and a solder ball 9 formed in a predetermined amount is placed in the through hole 10, and then the solder ball 9 is reflowed as shown in FIG. A solder layer 9a is formed.
尚、図中６ａはその両面に四部が形成された印刷台であ
り、７はメタルマスク４が半導体ウェハｌ上から離れる
のを防止するための永久磁石である。In the figure, 6a is a printing table having four parts formed on both sides thereof, and 7 is a permanent magnet for preventing the metal mask 4 from coming off the semiconductor wafer l.
しかしながら、上記のスキージを用いて半田バーストを
印刷する方法においては、第４図に示すように半田ペー
スト３を印刷する際、半導体ウェハｌからメタルマスク
４が離れる時にメタルマスク４にも半田ペースト３が一
部付着しており、そのメタルマスク４に付着する半田ペ
ースト３の量すと、Ｃｕバンプ２に付着する半田ペース
ト３の量ａとが個々の部分においてばらつきがあり、従
って、Ｃｕバンプ２上に形成される半田Ｎ ３ ａの量
、高さにばらつきが生じている。さらに、半田層３ａの
高さを高くした場合、半田のりフロ一時に半田が流れ出
すことがあるので隣接する半田同士がフリンジを形成し
てしまうという問題がしばしば生じている。However, in the method of printing solder bursts using the above-mentioned squeegee, when printing the solder paste 3 as shown in FIG. The amount a of solder paste 3 adhering to the metal mask 4 and the amount a of solder paste 3 adhering to the Cu bumps 2 vary from part to part. There are variations in the amount and height of the solder N 3 a formed thereon. Furthermore, when the height of the solder layer 3a is increased, the solder may flow out during the solder flow process, which often causes the problem that adjacent solders form fringes.
又、半田ボール９を使用する方法においては、メタルマ
スク４のスルーホール１０内に半田ボール９を確実に１
個ずつ入れる事は困難であり、又、半田ボール９のコス
トが高いという問題がある。In addition, in the method using solder balls 9, one solder ball 9 is reliably placed in the through hole 10 of the metal mask 4.
There is a problem in that it is difficult to insert each solder ball 9 one by one, and the cost of the solder balls 9 is high.
そこで本発明は上記の問題点に鑑みて、基板上に形成す
る半田層の量及び高さのばらつきを低減し、その高さを
高くする事が可能であり、しかもそれらを低コストで実
現する半導体装置の製造方法を提供する事を目的として
いる。In view of the above-mentioned problems, the present invention reduces variations in the amount and height of the solder layer formed on the substrate, makes it possible to increase the height, and achieves this at low cost. The purpose is to provide a method for manufacturing semiconductor devices.
上記の目的を達成する為に本発明は、基板上の所定の位
置に、前記基板上の半田を印刷すべき部分に対応する部
分に孔を有したマスクを配設し、前記基板上の前記半田
を印刷すべき部分に半田ペーストを印刷し、その状態に
て半田のりフロー、引き続き固化を行ない、その後、前
記マスクを前記基板より取りはずす事を特徴とした半導
体装置の製造方法を採用している。In order to achieve the above object, the present invention provides a mask having a hole in a portion corresponding to a portion of the substrate where solder is to be printed, at a predetermined position on the substrate, and A method of manufacturing a semiconductor device is adopted, which is characterized in that solder paste is printed on the area where solder is to be printed, the solder paste is allowed to flow in that state, and then solidified, and then the mask is removed from the substrate. .
そして上記の手段を採用する事により、基板上に形成さ
れる半田層の半田量はマスクに形成された孔の容積で決
まり、又、その高さはマスクの厚みで決まるのでばらつ
きを低減する事ができ、さらに、半田のりフロ一時にお
いて、個々の半田はマスクの孔により隔離されているの
でブリッジを形成するといった不具合は生じない。By adopting the above method, the amount of solder in the solder layer formed on the substrate is determined by the volume of the hole formed in the mask, and the height is determined by the thickness of the mask, so variations can be reduced. Furthermore, during the solder flow process, individual solders are isolated by the holes in the mask, so problems such as formation of bridges do not occur.
以下、実施例を用いて本発明を説明する。第１図（ａｌ
乃至（Ｃ）は本発明の一実施例を説明する為の工程順の
説明図である。まず第１図ｆａｌに示すように、その両
面に凹部が形成された印刷台６ａの一方の凹部にＣｕバ
ンプ２の形成された半導体ウェハ１を嵌合し、そのＣｕ
バンプ２に対応してスルーホール１０が形成されたメタ
ルマスク４を半導体ウェハ１上に配置する。このメタル
マスク４の材質としては、半田のりフロー後に半田が付
着しないように、又、磁石により固定する場合には強磁
性体を使用するとよく、本実施例ではステンレス鋼（Ｓ
ＵＳ）を用いている。７はメタルマスク４を位置合せし
た状態で固定する為に印刷台６ａの他方の凹部に配置し
た永久磁石である。そしてこの状態の印刷台６ａを印刷
保持台１３によって保持し、スキージ５によって半田ペ
ースト３をスルーホール１０に完全に充填するように印
刷する。尚、図において点線はスキージ５が折返移動す
る様子を示したものであり、８はメタルマスク４の枠で
ある。The present invention will be explained below using examples. Figure 1 (al
1 to 3(C) are explanatory diagrams of the order of steps for explaining one embodiment of the present invention. First, as shown in FIG.
A metal mask 4 in which through holes 10 are formed corresponding to the bumps 2 is placed on the semiconductor wafer 1. As for the material of this metal mask 4, it is preferable to use a ferromagnetic material to prevent solder from adhering after the solder paste has flowed, or to fix it with a magnet. In this example, stainless steel (S
US) is used. A permanent magnet 7 is placed in the other recess of the printing table 6a in order to fix the metal mask 4 in an aligned state. The printing table 6a in this state is held by the printing holding table 13, and the solder paste 3 is printed using the squeegee 5 so that the through holes 10 are completely filled. In the figure, the dotted line shows how the squeegee 5 moves back and forth, and 8 is the frame of the metal mask 4.
次に、第１図（ｂ）に示すように、印刷台６を印刷保持
台１３より取はずし、熱板１１又はベルト炉（図は前者
）によって加熱し、半田ペースト３をリフローする。そ
して、半田を固化してＣｕハンプ２上に半田層３ｂを形
成する。この際、メタルマスク４の浮き上りを防止する
為に永久磁石は取り付けたままとする。Next, as shown in FIG. 1(b), the printing table 6 is removed from the printing holding table 13, heated by a hot plate 11 or a belt furnace (the former shown in the figure), and the solder paste 3 is reflowed. Then, the solder is solidified to form a solder layer 3b on the Cu hump 2. At this time, the permanent magnet is left attached to prevent the metal mask 4 from floating up.
次に、第１図（Ｃ１に示すように、半導体ウェハ１及び
メタルマスク４を超音波洗浄器１２により超音波洗浄し
て剥れ易くした後に両者を引き離す。Next, as shown in FIG. 1 (C1), the semiconductor wafer 1 and the metal mask 4 are ultrasonically cleaned using an ultrasonic cleaner 12 to make them easier to peel off, and then they are separated.
そこで上記のような半田層３ｂの形成方法によると、半
田層３ｂの半田量はスルーホール１０の容積に応じて決
まり、又、その高さはメタルマスク４の厚みに応じて決
まるのでそれらのばらつきを低減できる。さらに、半田
層３ｂの高さを高くしても個々の半田はスルーホール１
０によって隔離されているので半田によるブリッジを形
成するといった不具合を生じる事はない。そして上記の
事を実現するのに何ら半田ボール９を用いていないので
、その分コストは低くなる。Therefore, according to the method for forming the solder layer 3b as described above, the amount of solder in the solder layer 3b is determined according to the volume of the through hole 10, and the height thereof is determined according to the thickness of the metal mask 4, so that variations in the solder layer 3b can be avoided. can be reduced. Furthermore, even if the height of the solder layer 3b is increased, individual solder is
Since they are isolated by 0, problems such as formation of solder bridges do not occur. Since no solder balls 9 are used to achieve the above, the cost is reduced accordingly.
尚、本発明は上記の実施例に限定される事なく、その主
旨を逸脱しない限り種々変形可能であり、例えば、被印
刷物としては半導体ウェハでなくとも、厚膜基板等であ
ってもよい。又、スルーホールの形状を半田リフロー後
にメタルマスクを剥れ易くするために、その断面がへの
字型になるように形成してもよい。It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the spirit of the invention. For example, the substrate to be printed may be a thick film substrate or the like instead of a semiconductor wafer. Further, in order to make the metal mask easier to peel off after solder reflow, the through hole may be formed so that its cross section is in the shape of a square.
〔発明の効果］
以上述べた如く、本発明の半導体装置の製造方法による
と基板上に半田層を形成後にマスクを取りはずしており
、その際に何ら半田ボールを用いる事がないので、製造
コストはその分低くなり、又、半田量、高さのばらつき
を低減する事が出来るという効果がある。[Effects of the Invention] As described above, according to the method for manufacturing a semiconductor device of the present invention, the mask is removed after forming the solder layer on the substrate, and no solder balls are used at that time, so the manufacturing cost is reduced. This has the effect of reducing the amount of solder and reducing variations in the solder amount and height.
第１図（ａｌ乃至（Ｃ）は本発明の一実施例を説明する
為の工程順の説明図、第２図（ａｌ及び（ｂ）は従来の
方法の一例を説明する為の図、第３図（ａｌ及び（ｂｌ
は従来の方法の他の例を説明する為の図、第４図は第２
図における従来の方法の不具合を説明する為の図である
。
１・・・半導体ウェハ、３・・・半田ペースト、４・・
・メタルマスク、１０・・・スルーホール。Figures 1 (al to (C)) are explanatory diagrams of the process order for explaining one embodiment of the present invention, Figures 2 (al and (b) are diagrams for explaining an example of a conventional method, Figure 3 (al and (bl)
is a diagram for explaining another example of the conventional method, and Figure 4 is a diagram for explaining another example of the conventional method.
It is a figure for explaining the problem of the conventional method in a figure. 1... Semiconductor wafer, 3... Solder paste, 4...
・Metal mask, 10...Through hole.
Claims (1)
き部分に対応する部分に孔を有したマスクを配設し、前
記基板上の前記半田を印刷すべき部分に半田ペーストを
印刷し、その状態にて半田リフローし、半田の融点以下
まで冷却した後、前記マスクを前記基板より取りはずす
事を特徴とした半導体装置の製造方法。A mask having a hole in a portion corresponding to the portion of the substrate where the solder is to be printed is arranged at a predetermined position on the substrate, and a solder paste is printed on the portion of the substrate where the solder is to be printed. . A method for manufacturing a semiconductor device, characterized in that the mask is removed from the substrate after solder reflow is performed in that state and cooled to below the melting point of the solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12174486A JPS62277751A (en) | 1986-05-27 | 1986-05-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12174486A JPS62277751A (en) | 1986-05-27 | 1986-05-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62277751A true JPS62277751A (en) | 1987-12-02 |
Family
ID=14818805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12174486A Pending JPS62277751A (en) | 1986-05-27 | 1986-05-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62277751A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6706621B2 (en) | 1999-10-21 | 2004-03-16 | International Business Machines Corporation | Wafer integrated rigid support ring |
| US6709966B1 (en) * | 1999-06-29 | 2004-03-23 | Kabushiki Kaisha Toshiba | Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device |
-
1986
- 1986-05-27 JP JP12174486A patent/JPS62277751A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6709966B1 (en) * | 1999-06-29 | 2004-03-23 | Kabushiki Kaisha Toshiba | Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device |
| US6706621B2 (en) | 1999-10-21 | 2004-03-16 | International Business Machines Corporation | Wafer integrated rigid support ring |
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