JPS62276942A - Information transmission equipment - Google Patents

Abstract

PURPOSE:To eliminate the need for a redundant bit pattern by applying delay correction at a sending end so as to be recieved at the same location as an N-terminal common block signal. CONSTITUTION:In setting an A terminal 1 as a common block source, a B terminal 2 is constituted similarly to a C terminal 3, a reception signal f12 from the B terminal 2 is observed at the A terminal 1 and the transmission timing at the B terminal 2 is adjusted by the delay circuit 9 of the B terminal 2 to eliminate the phase shift of the clock component in a transmission signal f11 at the A terminal and the reception signal f12. Then the phase shift in the clock component between the reception signal from the A terminal 1 and the reception signal from the B terminal does not exist without fail similarly. Thus, no redundant bit pattern is required, the transmission efficiency is improved and the synchronizing correction circuit is simplified.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The power system protection/control device of the present invention, in particular, transmits and receives signals from a plurality of terminals via a transmission path using the same star coupler. The present invention relates to an information transmission device suitable for a device that uses

[Conventional technology]

In conventional devices, in order to accurately and stably receive and demodulate signals from each terminal, a preamplifier (PRE) is used to set the clock and level of the receiving section before valid data is received.
A redundant bit pattern called AMBLE was added to the transmitted signal. In addition, regarding this device, "hygiene communication"
Tokyo Denki University Press, co-authored by Miyauchi, Hirata, and Yamamoto, pages 94-9
7 is known.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when a signal from an N terminal is received via an N-port star coupler, the transmission path delay times are different because the distances between the respective transmitting ends and receiving ends are different. Therefore, even though each transmitting end transmits data in synchronization with a common clock signal, the receiving end needs to correct the synchronization again every time the receiving end changes. This is done after receiving a signal from one terminal in sync.

This is because in order to receive and demodulate a signal from the next terminal, accurate demodulation cannot be achieved unless the phase shift of the received signal due to the difference in transmission path delay is corrected. For this reason, it is necessary to lengthen the time for redundant bit patterns attached to valid data, which reduces transmission efficiency.

Furthermore, the synchronization circuit that creates clock timing synchronized with the received signal is complicated and requires a large amount of hardware because the synchronization correction is completed within the redundant bit pattern time, that is, within a short period of time.

It is an object of the present invention to simplify the synchronization circuit that creates clock timing synchronized with the received signal, to eliminate the need for redundant bit patterns in order to set the clock and level at the receiving end, and to reduce the performance of the synchronization circuit in the receiving section. There is a particular thing.

[Means for solving problems]

At each terminal synchronized with the N-terminal common clock signal received via the N-port star coupler, when transmitting a signal to other terminals via the N-port star coupler,
By correcting the phase of the clock component of the transmission signal by the delay circuit, it is possible for other terminals, that is, the receiving terminal, to receive the lock signal in the same phase as the lock signal common to the N terminals.

The delay circuit can be realized simply by using commonly used delay line elements.

The above object is achieved by correcting the delay at the transmitting end so that the N terminals receive the lock signal in the same phase as the common lock signal.

[Effect]

Hereinafter, the elimination of phase shift at the receiving end by delay correction at the transmitting end will be explained with reference to FIG. In order to avoid complication of the drawing, FIG. 2 clearly shows the case where N=3 terminals. If the transmission path distances between the terminals 1, 2.3 and the star coupler 4 are all the same, the phase shifts due to transmission path delays are all the same. But usually.

Since the distance between each terminal 1, 2.3 and the star coupler 4 is different, the amount of phase shift of the clock component is also different. Here A terminal 1
is a common clock source, the signal f from A terminal 1
il is connected to B terminal 2. through star coupler 4. Each clock component arrives with a phase shift commensurate with the distance of the transmission path to the C terminal 3. Also, the transmission signal f21 from B terminal 2
Similarly.

A terminal 1. It reaches C terminal 3.

Observe the received signal f12 from B terminal 2 at A terminal 1, and
By adjusting the transmission timing of the terminal 2 by the delay circuit 9 of the B terminal 2, the phase shift between the clock components of the transmission signal fil of the A terminal and the reception signal f12 is made to a value that can be ignored. Then, similarly, at C terminal 3, A terminal 1 is also required.
Therefore, there is no phase shift in the clock component between the received signal and the received signal from the B terminal. In other words, the phase shift due to the difference in distance between each terminal 1, 2.3 and star coupler 4 can be corrected by adjusting the transmission timing by m while observing at any terminal. VJ has been adjusted, and there is no need to observe at all terminals, and the adjustment is completed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In order to avoid complication in one drawing, only the C terminal 3 in FIG. 2 is clearly illustrated. The optical fiber transmission line 5, f32, connected to any terminal of the star coupler 4 receives a common clock signal, that is, the transmission signal fil from the A terminal 1 and the signal reached at the C terminal of the transmission signal f21 from the B terminal, ○ /
E6 is an optical-to-electrical converter, E107 is an electric-to-optical converter, and a synchronization circuit 8 is a clock synchronization interconnection circuit that synchronizes the clock 15 at its own end with the received signal f32. clock f33, P/SIO is a parallel-serial transmission circuit, S/P11 is a serial-parallel transmission circuit, and delay circuit 9 is a delay line for adjusting transmission timing. RY-U and NIT 12 are arithmetic processing units that perform relay calculation and control based on the signal from the S/P 11 and the input signal 13 from the outside, and output the output signal 14 and the P/S I O signal to the outside. 6 The operation of this device is that when A terminal 1 is set as a common clock source, the master clock signal fil from A terminal 1, that is, a part of the received signal f32 of C terminal 3 and its own clock source. 15 and the synchronization circuit 8 constitute a PLL circuit or the like to perform synchronization correction. The C terminal 3 starts transmitting at a predetermined timing based on the synchronized signal f33. Similarly, the B terminal 2 also exchanges information via the same transmission path by starting transmission at a preset timing.

Therefore, the phase shift adjusted at the C terminal 3 will be explained with reference to FIG. Figure 3 shows the signal fi from A terminal 1.
Only the glue-lock components of the signal f21 from the l and B terminals are clearly shown. The transmission signal fil from the A terminal 1 reaches the C terminal 3 with a delay of the transmission line delay time 'rA. or,
Furthermore, the transmission signal f21 from the B terminal has a transmission path delay time TB.
reaches the C terminal with a delay of At this time, since the distance between the C terminal 3 and the B terminal 2 is longer than the distance between the C terminal 3 and the A terminal 1, the signal arrives after an extra delay time TC. The signals f11°f21 from the A and B terminals 1 and 2 are combined to form the received signal f32 at the C terminal. Here, the synchronous circuit 8 of the C terminal first performs synchronous interconnection with respect to the signal fil from the A terminal and outputs a transmission/reception clock f33. However, B
A deviation of the delay time difference TD occurs with respect to the signal from the terminal, and it becomes necessary to re-correct the synchronization in order to eliminate the phase deviation. Therefore, the signal f from the B terminal
Since accurate demodulation cannot be expected during a period at the beginning of 2L, a redundant bit pattern must be used for the clock am. Therefore, the B terminal 2 is configured in the same manner as the C terminal 3, and the delay circuit 9 is used to adjust the delay time difference. By transmitting with a delay of TD in advance, the transmitted signal f from the B terminal
2LI7) The redundant bit pattern at the beginning for clock adjustment is no longer necessary.

The delay circuit 9 at the transmitting end corrects the phase shift due to the difference in transmission path distance.
According to this embodiment, a redundant bit pattern is not necessary, and the synchronization circuit 8 that performs synchronization correction in a short time can also be a simple circuit. Furthermore, as clearly shown in FIGS. 4 and 5, it is clear that the same effect can be obtained even if the location of the delay circuit is changed.

〔Effect of the invention〕

According to the present invention, since the signal from the N terminal can be received and demodulated without phase shift, the signal is added before valid data in the transmission signal. This eliminates the need for redundant bit patterns for adjusting the clock and level of the receiving section, improving transmission efficiency, and since there is no phase shift, the synchronization correction circuit can also be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment of the information transmission device of the present invention, FIG. 2 is an explanatory diagram showing an example of a system using the device of FIG. 1, and FIG. The time chart in the figure, FIGS. 4 and 5 are block diagrams of the configuration of other embodiments of the information transmission apparatus of the present invention, respectively. 1.2.3-1. Information transmission device, 4... star coupler, 5... optical fiber transmission line.

Claims (1)

[Claims] 1. N clock signals emitted from a shared clock source
An information transmission device characterized in that the information is supplied to the information source of the terminal via an N-port star coupler, and each terminal is configured to transmit and receive signals in synchronization with this.