JPS62275388A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To clear display data in an optional area of a display screen at a high speed just with designation of a word line, by providing a mask means to the data line and supplying a prescribed write signal to a data line indicated by the mask means in a substantial read mode. CONSTITUTION:A dynamic RAM writes initial value data designated by an initial value register CDR to plural memory cells whose masks are not indicated by a clear mask shift register SRC among those (n) pieces of memory cells connected to the intersecting points between a selected word line and the complementary data lines at one side of (n) pairs. Then the RAM clears partially the memory cells connected to the word lines for each line, i.e., each word line. The memory cells can be cleared for each line by designating the lines by the external address signal and also continuously by a built-in refresh counter. In other words, said clearing action is carried out together with a selecting action of a row system in a substantial read mode.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention relates to a semiconductor memory device, and is used, for example, in a RAM (random access memory) for image processing. It is about effective techniques.

[Conventional technology]

As a RAM for image processing to display characters and figures on the screen of a CRT (cRT), for example, the serial access RAM described in Nikkei McGraw-Hill, February 11, 1985, r Nikkei Electronics J, pages 219 to 229, is used. Memory is known.

In this RAM, data lines of a memory array are connected in parallel to a data register via a switch circuit, and data is serially output between the data register and an external terminal. As a result, the stored information of the memory cell connected to the selected word line is outputted serially, so that pixel data can be easily retrieved in synchronization with the rask scan timing of the CRT.

[Problem that the invention seeks to solve]

In image processing, two images can be displayed alternately in a fixed display area as shown in Figure 3 by clearing the previous display, or by erasing part of the displayed image and displaying messages one after another. This often happens. However, in the conventional image RAM described above, writing to the memory cell is performed in units of 1 to 8 bits, so in order to obtain partial erasure as shown in Figure @3, a considerable number of addresses are required. Operations and memory accesses must be performed. In addition, the image RAM is
Even if a serial input function is provided, it is necessary to read out the memory contents of the image RAM, perform calculations for partial erasure, and then perform serial input.

An object of the present invention is to provide a semiconductor memory device such as an image RAM having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, masking means is provided corresponding to the data lines constituting the memory array, and a predetermined write signal is supplied to the data lines designated by the masking means in the actual read mode. .

[For production]

According to the above-mentioned means, a predetermined write signal is supplied only to the memory cells connected to the data line designated by the mask means, so that the data can be displayed in any area of the display screen simply by specifying the word line. Data can be cleared quickly.

〔Example〕

Figure 2 shows the DynaX type R to which this invention was applied.
A block diagram of one embodiment of an AM is shown. Each circuit block in the figure may be formed using known semiconductor integrated circuit manufacturing technology, but is not particularly limited to it.
formed on a single semiconductor substrate.

FIG. 2 exemplarily shows a 1-bit memory array M-ARYO and its peripheral circuits. Although not particularly limited, the dynamic RAM of this embodiment has four memory arrays as a whole, and performs writing or reading in units of 4 bits by - times of memory access.

In addition, each memory array has the function of serially reading out row by row starting with the read data of the data line given as the Y address signal. Corresponds to pixel and brightness, each memory address is color C
It is used corresponding to each pixel (dot) of RT,
It can be used as a so-called image RAM.

Each memory array represented by the memory array M-ARYO is of a two-intersection system, as will be explained in detail later in FIG. It is composed of n pairs of complementary data lines arranged in the direction and m x n memory cells coupled to the intersections of the word lines and the complementary data lines. The m word lines are connected to a row address decoder RDC that decodes an X address signal among address signals supplied from the outside.
One of them is selected and specified by R.

In the dynamic RAM of this embodiment, each complementary data line of the memory array has a sense amplifier S on one side.
It is coupled to the input/output nodes of each unit circuit constituting the AO. Further, the complementary data line is coupled to each unit circuit forming the clear circuit CLSO. This clear circuit C'L
Initial value data rO is supplied to S0 from an initial value register CDR for specifying the initial value in the clear state of the memory cell. Each unit circuit of clear circuit CLSO is coupled to a corresponding bit of clear mask shift register SRC. As a result, in the dynamic RAM of this embodiment, by selecting one word line, one of the 11 memory cells coupled to the intersection of the word line and one of n pairs of complementary data lines is selected for the clear mask. By writing initial value data specified in the initial value register CDR to multiple memory cells whose masks are not specified by the shift register SRC, the memory cells connected to the memory cells are written row by row, that is, word line by word line. It has a partial clear function. Clearing of memory cells in row units can be performed by specifying a row using an external address signal, and can also be performed sequentially and continuously using a built-in refresh counter. That is, it is executed together with the row-related selection operation in the actual read operation mode.

The sense amplifier SAO is a timing control circuit described later.
n memories that are selectively activated by a timing signal φpa supplied from rC, and are coupled to the intersection of a selected word line and one data line of n pairs of data lines, although this is not particularly limited. A minute read voltage from the cell is amplified with reference to a reference voltage supplied from a dummy cell (not shown) coupled to the other data line, and is converted into a high level/low level binary signal. Furthermore, the sense amplifier SAO includes an active restore circuit for replenishing a drop in the level of information stored in the memory cell due to a destructive read operation of the dynamic memory cell.

Each data line of memory array M-ARYO is connected to a corresponding switch MO of column switch cswo on the other side.
Single read or! via SFET! coupled to a complementary common data line CDQ for performing a write operation;
Furthermore, they are coupled to seven data latches DLO for holding the read data of the corresponding complementary data lines. Each bit of data latch DLO is connected to the corresponding serial read column switch csso switch MO3FET.
Complementary common data line CD5O for serial readout via
is combined with Column switch csw.

Data i! is directly sent from the column address decoder CDCR to the gate of each switch MO5FET constituting the switch MO5FET. ! A selection signal is supplied to the column switch c for serial readout.
The gate of each switch MO3FET constituting sso is coupled to a corresponding bit of the serial read shift register SRD.

In the case of a normal 4-bit read operation, the column switch cswo selects one set of data lines in response to a data line selection signal directly supplied from the column address decoder CDCR, and connects them to the complementary common data line CDO. The complementary common data line CDO has a corresponding data output buffer DO.
The input terminal of BO is coupled, and the output terminal of data input cover sofa DIBO is coupled.

The data output buffer DOBO is a dynamic RAM
In the 4-bit read operation mode from a single address, the operation mode is activated by the high level of the timing signal φr supplied from the timing 11 control circuit TC, and the read data on the data line supplied from the complementary common data line CDO is amplified. and outputs it to the outside via the input/output terminal Do. When the dynamic RAM is in a non-operating state or in another operating mode in which the timing 18 φr is at a low level, the output of the data output cover 7 DOBO is brought into a high impedance state.

The data input cover sofa DIBO is a dynamic RAM.
In the 4-bit write operation mode for a single address, the operation state is activated by the high level of the timing signal φW supplied from the timing control circuit TC, and the write data to the memory cell supplied via the input/output terminal Do is This signal is used as a complementary write signal and is supplied to the complementary common data line CDO. When the dynamic RAM is in a non-operating state or in a read operation mode when the evening/f timing signal ψW is at a low level, the data input cover sofa DIBO
The output of is in a high f-impedance state.

On the other hand, the data launch DLO for serial reading is composed of n latches for holding read data of corresponding data lines. data lunch DL
O is operated by the timing signal φ5r11 supplied from the timing control circuit TC at the timing when the read signal of each data line is established by the unit circuit of the corresponding sense amplifier SAO in the serial read operation of the dynamic RAM. state, and the read data of the corresponding data line is held in each launch circuit.

In the serial read operation mode of the dynamic RAM, the serial read column switch csso sequentially selects complementary data lines for serial read complementary data by a continuous data line selection signal supplied from the serial read shift register SRD. *CD5O
C, the read signal of each complementary data line held in the data latch DLO is transmitted one after another to the complementary common data line CD5O for serial readout.

In the serial read shift register SRD, logic 21' is written into the bit corresponding to the data line that is output first in the serial read operation. That is, in the case of a serial read operation mode for continuous read row by row of dynamic RAM, the row to be read, that is, the word line, is specified by the X address signal, and the data line to be output first is specified by the Y address signal. It is specified. This Y address signal is decoded by the column address decoder CDCR, and logic "1" is written into the corresponding bit of the serial read shift register SRD. In the serial read operation, this logic "L" write signal is shifted one after another using the timing signal φsd supplied from the timing control circuit TC as a shift signal, and is used as a continuous data line selection signal for serial read operation. Supplied to column switch csso.

The complementary common data line CDSO for serial reading is
It is coupled to the input terminal of serial readout amplifier circuit 5RAO. This serial readout amplifier circuit 5RAO is
The dynamic RAM is activated in the serial read operation mode, and the serial read signal transmitted to the serial read complementary common data line CD5O is amplified and sent to the outside via the serial read output terminal SDO.

Column address decoder CDCR receives complementary internal address signal a supplied from column address buffer CADB.
yO-ayi is decoded to form a data line selection signal. This data line selection signal is 4 for a single address.
For bitwise read or write operation mode, the corresponding switch MO5 of column switch cswo
Supplied directly to the gate of the FET. In addition, in the case of the serial read operation mode, the logic “1” is sent to the corresponding bit of the serial read shift register SRD as the start address in the serial read operation mode.
is written.

The column address buffer CADH takes in the Y address signals AYO to AYi supplied in synchronization with the column address strobe (K Cts S) via the address signal line AO=Ai, which is a full multiplex system, and performs complementary Internal address signals yO to ayr are formed and supplied to the column address decoder CDCH.In other words, the column address buffer CADH detects the fall of the column address strobe signal CAS in the timing control circuit T'C. A column address buffer C is activated by the generated timing signal φac and takes in Y address signals AYO to AYi supplied in synchronization with the column address strobe signal CXτ.
ADB is a complementary internal address signal 3yO~ which is made up of internal address signals ay□-ayi that are in phase with these external address signals and internal address signals 7Tτ~7T that are opposite in phase.
yi (hereinafter, for example, internal address signal ayQ and its inverted signal 17r are expressed as complementary internal address signal yO), and color air 1:res decoder CDC
Supply to R.

The row address decoder RDCR receives a complementary internal address signal ax supplied from the row address buffer RADB.
-axis to form a word line selection signal for selecting one word line of mesoria -1° and supply it to memory arrays M-ARYO to MARY3.

The above sense amplifier SA and clear circuit CLS.

The column switch CSW, data launch DL, serial readout column switch CSS, data output cover sofa DOB, data input cover sofa DIB, and serial readout amplifier circuit SRA are memory array M-ARYO.
~M-ARY3 is provided with four circuits each, and the initial value register CDR, clear mask shift register SRC, serial read shift register SRD, and each address decoder are connected to the four memory arrays M-A.
Commonly provided in RYO to M-ARY3.

The dynamic RAM of this embodiment further has an automatic refresh mode function for refreshing all memory cells at a predetermined period, and for this purpose, a refresh address counter REFC and an address multiplexer A are used.
MX is provided.

That is, in the case of a normal write or read operation (including a serial read operation), the row address strobe signal RAS falls from high level to low level, and after a slight delay, the column address strobe signal CA rises.
S falls from high level to low level. On the other hand, in the automatic refresh operation mode, the column address strobe signal CAS falls to a low level before the row address strobe signal RAS, and the row address strobe signal RAS falls to a low level a little later. As a result, the automatic refresh operation mode is identified, and the top refresh address supplied as the X address signals AXO to AXi is set in the refresh address counter REFC in synchronization with the falling of the row address strobe signal positive τ. Thereafter, every time the row address strobe signal RAS changes from high level to low level to 4i, the timing signal φC is generated by the timing control circuit TC. Refresh address counter REFC is incremented by this timing signal φC, forms refresh addresses cxQ to cxi for specifying the word line to be refreshed, and supplies them as one input signal of address multiplexer AMX. Using this automatic refresh operation mode, a rear operation is performed as described later.

An external address signal is supplied to the other input of the address multiplexer AMX via address signal input terminals AO to At. Address multiplexer AMX selects these address signals in response to timing signal φref supplied from timing control circuit TC and transmits them to row address buffer RADB in automatic refreshment operation mode. That is, the timing signal φr
ef is set to high level in the automatic refresh operation mode, thereby causing the address multiplexer AMX
selects refresh addresses cxO to cxi supplied from refresh address counter REFC and transmits them to row address buffer RADB. On the other hand, the timing signal φref is set to a low level in the normal write or read operation mode, so that the address multiplexer AMX is connected to the address signal input terminal AO.
The external address signal supplied to Ai is selected and transmitted to the row address buffer RADB.

The row address buffer RADB is activated by a timing signal φar generated in synchronization with the fall of the row address strobe signal RAS, and takes in an external X address signal or fresh share address signal inputted via the address multiplexer AMX. , row address buffer RADB forms complementary internal address signals axQ to axi based on these address signals,
Supplied to the row address decoder RDCH.

Timing control circuit] C is a control signal supplied from the outside, a row address strobe signal rτ1, a column address strobe signal CAS, and a write enable signal WE.
, the various timing signals described above are formed using the serial read mode signal SRM, the refresh clear mode signal CM, and the clock pulse signal CP, and are supplied to each circuit.

FIG. 1 shows a circuit diagram of an embodiment of a clear circuit CLSO and its peripheral circuits corresponding to a memory array MARYO.

The memory cells constituting the memory array M-ARYO are composed of an address selection MOS FETQm whose gate is coupled to the word lines W1 to Wm of the corresponding row, and an information storage capacitor Cs. Each complementary data line D1
．． D to Dn and Sl are coupled to input/output nodes of unit circuits 5AOI to 5AOn of the sense amplifier. Furthermore, in this embodiment, in order to speed up operations such as clearing, the complementary data lines D1. Clear circuit CL for DI etc.
It is coupled to the SO unit circuit CLSO1''CLSOn.

As described above, the unit circuit of the sense amplifier SAO receives the timing signal φp supplied from the timing control circuit TC.
When a word line is selected, the memory cell read minute signal outputted to each complementary data line is amplified. Further, the level of the stored information in the memory cell that is once destroyed by this read operation is restored by the active restore circuit included in each unit circuit of the sense amplifier.

Each unit circuit of clear circuit CLSO is
As represented by I, MO3FETs Q3 and Q5 are provided between the non-inverted signal line D1 of the corresponding complementary data line and the circuit power supply voltage Vcc and ground potential, and the inverted signal line DI and the circuit power supply voltage VCC. It is composed of MO3FETs Q6 and Q4 provided between the MO3FET and the ground potential. The gates of MO5FETQ3 and Q4 are commonly connected and coupled to the non-inverting output terminal Q of the corresponding bit of the clear mask shift register SRC via MO5FETQI. Similarly, the gates of MO5FETQ5 and Q6 are commonly connected and coupled to the non-inverting output terminal Q of the corresponding bit of clear mask shift register SRC via MO3FETQ2. MO5FE
The gates of TQI and Q2 are each MO3FETQ
dO of the initial value register CDR via 1B and Q19.
It is coupled to the non-inverting output terminal Q and the inverting output terminal of the bit. The output terminals Q and Q of other bits of the initial value register CDR are connected via MO3FETQ12 to Q17.
Corresponding memory arrays M-ARY l to M
A RY 3 (D clear circuit CLSI ~ CLS3
is combined with

Each input terminal of the initial value register CDH is an input/output terminal DO.
A timing signal φdr coupled to D3 and set at high level in the write mode of the initial value register CDH is supplied from the timing control circuit TC to the input trigger terminal of the initial value register CDR. Also, MO5FET
The gates of Q12 to Q19 (7) receive a timing signal φ that is set to high level in the refresh clear mode.
rci+ is supplied.

On the other hand, the input terminal of the clear mask shift register SRC is coupled to the input/output terminal D4, and the clock terminal receives a timing signal φsc generated by the timing control circuit TC in the write mode of the clear mask shift register SRC. Supplied.

From the above, the row-by-row clearing operation in the dynamic RAM of this embodiment is performed as follows.

+1) Writing of initial value register CDR The initial value data written to the memory cell to be cleared is
Prior to the clearing operation, the initial value register CDH is first written. This initial value data can be specified for each memory array, and thereby determines the color of the cleared portion on the CRT.

Writing to the initial value register CDH is performed when the column address strobe signal CAS is set to low level following the row address strobe signal RAS, and at the same time, the write enable signal E and the refresh clear mode signal RC are set to low level.
This is done by setting M to low level. When these control signal conditions are met, the timing control circuit T
Timing signal φdr is formed by C and supplied to initial value register CDH. Thereby, the initial value data dro-dr3 supplied to the input/output terminals DO-D3 are taken into the initial value register CDR.

(2) Which memory cell to clear among the memory cells coupled to each complementary data line is determined by selecting the write word line of the clear mask shift register SRC.
Specified by clear mask shift register SRC. That is, the memory cell connected to the complementary data line whose corresponding bit of the clear mask shift register SRC is set to logic "1" is cleared, and the initial value written to the corresponding bit of the initial value register CDH is cleared. Value data is written in. On the other hand, memory cells coupled to complementary data lines for which logic “O” is written in the corresponding bit of the clear mask shift register SRC are prohibited from being cleared and normal refresh operations are performed. will be held.

Mask information is written to the clear mask shift register SRC at the same time as writing to the initial value register CDH. That is, following the row address strobe signal RAS, the column address strobe signal CAS is set to a low level, and at the same time, the write enable signal WE and the refresh clear mode signal RCM are set to a low level. In addition, the clock pulse input terminal CP has
A clock pulse for shifting the clear mask shift register SRC is supplied. When these control signal conditions are met, the timing control circuit TC forms a timing signal φsc in synchronization with the clock signal supplied to the clock pulse input terminal, and supplies it to the clear mask shift register SRC.

The clear mask shift register SRC operates according to this timing signal φsc, and sequentially takes in the mask information serially supplied via the input/output terminal D4.

(3) Clearing operation The dynamic RAM of this embodiment uses the above initial value register CDR and clear mask shift register S.
By performing an automatic refresh operation after writing the RC, it is possible to continuously perform a partial clear operation on a row-by-row basis. That is, before the row address strobe signal RAS, the column address strobe signal CA
By setting S to a low level, the automatic refresh mode is identified, and at the same time, the address of the first word line supplied as the X address signals AXO to AXi is set in the refresh address counter REFC. Further, as the row address strobe signal RAS repeatedly changes from high level to low level thereafter, a timing signal φC is generated from the timing control circuit TC, and the refresh address counter REFC increments. From timing control circuit TC to address multiplexer AMX
Since the timing signal φref is supplied to the row address decoder RDCH, the address multiplexer AMX transmits the refresh and nosier addresses cxO to cxi sent from the refresh address counter REFC to the row address decoder RDCH. Furthermore, when the refresh clear mode signal RCM is set to a low level together with the row address strobe signal RAS at a low level, the timing signal ψram formed by the timing control circuit TC is set to a high level. This allows MO3FET to transmit the output signal of the initial value register CDR to the clear circuit CLSO.
Q12 to Q19 are turned on, and the initial value register CD
The H output signal is MO5FETQI, Q2 (Q?, Q8
) is supplied to the gate.

When the initial value data is logic “1”, the initial value data drQ
The high level of MO5FETQI (Q7) turns on, and the corresponding clear mask shift register S
When the RC bit is logic “L”, MO3FETQ3
And Q4 is turned on. Therefore, 6, the non-inverting signal line D1 is connected to a high level such as the circuit power supply voltage Vcc through the MO3FET Q3, and the inverting signal line Di is connected to the high level M
A low level, such as the ground potential of the circuit, is supplied via O3FETQ4. If the bit of the corresponding clear mask shift register SRC is logic “0”, MO5FET
The gate potentials of Q3 and Q4 become low level, and both M
Since both O3FETs are turned off, the previously stored information in the selected memory cell is refreshed.

On the other hand, when the initial value data is logic "O", the high level of the initial value data drO causes MOSFETQ2 (Q8
) turns on and the bit of the corresponding clear mask shift register SRC is logic “11”, the MO3F
ETQ5 and Q6 are turned on. Therefore, a low level such as the ground potential of the circuit is supplied to the nose inversion signal line D1 via the MOSFET Q5, and a high level such as the circuit power supply voltage Vcc is supplied to the inversion signal line DI via the MOSFET Q6. If the bit of the corresponding clear mask shift register SRC is logic '03, MO
The gate potentials of the 3FETs Q5 and Q6 become low level, and both MOSFE'i' are turned off, so that the previously stored information is refreshed and rewritten in the selected memory cell.

When clearing the portion indicated by diagonal lines in FIG. 3, the bits of the clear mask shift register SRC corresponding to the complementary data lines Dr-Ds are set to logic "O", and the other bits are set to logic "1". Further, initial value data for specifying the display color of the clear portion (shaded portion) in FIG. 3 is written into the initial value register CDH.

Next, the X address signals AXO to AXi are set as an address specifying the word line Wp, and the automatic refresher mode is started. By setting the column address strobe signal τ■1 to the low level earlier than the row address strobe signal Rτ1, the timing control circuit ゛rC performs the automatic reflex 7
Refresh address counter R
The leading address supplied as the X address signals AXO to AXi is set in EFC by the fall of the row address strobe signal RAS. Thereafter, when a refresh address corresponding to word lines Wp-Wq is designated, the refresh, clear & clear mode signal RCM is set to low level. As a result, among the memory cells selected by the word lines Wp-Wq, the complementary data line Dr
Initial value data specified in the initial value register CDH is written to the memory cell coupled to w D s.

The above clearing operation can also be performed row by row by setting the refresh clear mode signal RCM to a low level and performing the normal read operation mode or RAS-only refresh operation mode.

As shown in the above-mentioned embodiment, this invention can be applied to R for images.
When applied to a semiconductor memory device such as a dynamic RAM used as an AM, the following effects can be obtained. In other words, (11) a mask means corresponding to the data lines constituting the memory array, an initial value register indicating the data value at the time of clearing the memory building, and a mask means corresponding to the data lines constituting the memory array; By providing a clear circuit for signing a clear data value specified in the initial value register to all memory cells not specified by the masking means, all memory cells that are not specified by the mask means are connected to the selected word line. The advantage is that a predetermined clear data value can be written to any plurality of memory cells.

(2) By performing the clearing operation described in item +1) in parallel with the automatic refresh operation, it is possible to achieve the effect that partial erasure of the image RAM can be performed at high speed.

(3) According to the above (1) and (2), the image RA
By being able to clear any part of M to a predetermined initial value, any part of the display image can be displayed in a predetermined color, and by complementary clearing parts of two images, it is possible to create an arbitrary composition. The effect is that an image can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Needless to say, for example, in the case of this embodiment, four memory arrays M, ARYO to M-ARY3 are provided corresponding to the pixels of three colors and the luminance, but four sets of complementary data can be selected by one data line selection signal. The memory array may be configured as one by allowing the lines to be selected at the same time. In this case, correspondingly, 4Xn unit circuits of the clear circuit may be operated simultaneously. is necessary. Furthermore, the unit of writing and reading may be 8 bits or more, and the serial read shift register SRD and the clear mask shift register SRC may be used in common. In addition, in this embodiment, clearing of the memory cell of the corresponding complementary data line is prohibited by setting the blue content of the clear mask shift register input 5l (C) to logic "1". Conversely, clearing of the memory cell of the corresponding complementary data line may be prohibited by setting the bit of the clear mask shift register SRC to logic "0".

The specific circuit configuration of the clear circuit CLSO-CLS3,
Various embodiments can be adopted, such as combinations of control signals. Furthermore, the clear signal may be fixed, that is, the MO5FETQ3 to Q
6 (2) Among them, one set of (7) MO5FETs Q3 and Q4 or Q5 and Q6 may be provided and a fixed clear state may be set by selectively operating them using a mask register. .

In the above explanation, the invention made by the present inventor was mainly applied to a dynamic type RAM for images, which is the background application field, but it is not limited thereto. RAM
It can be similarly applied to etc.

(Effects of the Invention) The effects obtained by the typical inventions disclosed in this application can be simply explained as follows.In other words, masking means corresponding to data lines constituting a memory array; For all memory cells that are not specified by the masking means among the plurality of memory cells selected by the initial value register indicating the data value at the time of clearing the memory cell and the selection of one word line,
By providing a clear circuit for writing a clear data value specified in the initial value register, partial erasure of a semiconductor memory device such as an image RAM can be performed at high speed.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
A circuit diagram showing an example of a clear circuit and its peripheral circuits.
FIG. 3, a block diagram showing an embodiment of M, is a conceptual diagram for explaining partial erasure of the RAM for lii image. M-ARYO...Memory array, CLSO (CLS0
1~CLSOn)...Clear circuit (unit circuit), 5A
O (SA01~5AOn) ...Sense amplifier circuit (
A11th circuit), CDR...Initial value register, SR
C...Shift register for clear mask, Qm...MO3FE for address selection T% Cs...Information i1
Capacitor for M, Ql~Q19...N channel MO
5FET. cswo...column switch, DLO...data launch, csso...column switch for serial readout, SRD...shift register for serial readout,
RDCR...Row address decoder, CDCR...
Column address decoder, AMX...address multiplexer, RADB...row address buffer, CA
DB...column address buffer, DOBO...data output cover sofa, DIBO...data input cover sofa,
5RAO... Serial readout amplifier circuit, TC...
Timing control circuit, REFC...refresh counter.

Claims (1)

[Scope of Claims] 1. A masking means provided corresponding to a data line constituting a memory array, and a predetermined masking means that is activated in a substantial read mode and is provided for a data line indicated by the masking means. 1. A semiconductor memory device comprising: a clear circuit for supplying a write signal. 2. The semiconductor memory device is a dynamic RAM, and the masking means is a shift register in which each bit corresponds to a pair of complementary data lines constituting a memory array. The semiconductor memory device according to item 1. 3. The semiconductor memory device according to claim 2, wherein the clear circuit is activated when the dynamic RAM is in an automatic refresh operation mode.