JPS62274858A - Fault detection system - Google Patents

Fault detection system

Info

Publication number
JPS62274858A
JPS62274858A JP11813286A JP11813286A JPS62274858A JP S62274858 A JPS62274858 A JP S62274858A JP 11813286 A JP11813286 A JP 11813286A JP 11813286 A JP11813286 A JP 11813286A JP S62274858 A JPS62274858 A JP S62274858A
Authority
JP
Japan
Prior art keywords
test signal
circuit
line connection
switch
switch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11813286A
Other languages
Japanese (ja)
Inventor
Hideo Sunaga
須永 秀郎
Noriyuki Okamoto
岡本 宣之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11813286A priority Critical patent/JPS62274858A/en
Publication of JPS62274858A publication Critical patent/JPS62274858A/en
Pending legal-status Critical Current

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  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To reduce the operation of a maintainer and to shorten a time required for fault detection by using a rest signal generator and a test signal detector built in the titled system to detect a fault automatically. CONSTITUTION:A test signal is generated by a test signal generating means 51 and inputted to a line connection circuit 101 for executing a test through a switch circuit 30. In the circuit 101, the test signal is loop-backed by a loopback switch means 111. The loopback test signal is inputted to a test signal detecting means 52 through the switch circuit 30 and its falut is detected by the means 52. Said operation is automatically executed under control by a control means 40. Since a fault of the circuit 101, the switch circuit 3 or a path between both the circuits 101, 3 is automatically detected and informed to the maintainor, the operation of the maintainer can be reduced and the time required for the fault detection can be shortened.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 本発明は、データ通信の回線接続装置の障害検出方式に
関する。特に、複数の回線接続回路、4線を経由して回
線接続回路に接続されるスイッチ回路および回線接続回
路、スイッチ回路を制御する制御回路を備え、制御回路
の指示により任意の回線接続回路間を接続する回線接続
装置の障害検出方式に関する。
Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a fault detection method for a data communication line connection device. In particular, it is equipped with a plurality of line connection circuits, a switch circuit connected to the line connection circuit via four wires, a line connection circuit, and a control circuit that controls the switch circuit. This invention relates to a fault detection method for a connected line connection device.

〔概要〕〔overview〕

本発明は回線接続装置の障害検出方式において、運用中
でも自動的にパスの接続を行い、内蔵する試験信号発生
器および試験信号検出器を使用して自動的に障害の検出
を行うことにより、保守者の操作を少なくし障害検出に
要する時間を短縮するようにしたものである。
The present invention is a fault detection method for line connection equipment that automatically connects paths even during operation and automatically detects faults using a built-in test signal generator and test signal detector. This reduces the number of operations required by the operator and shortens the time required to detect faults.

〔従来の技術〕[Conventional technology]

第2図は従来例の障害検出装置のブロック構成図である
。従来、回線接続装置の障害検出装置では、第2図に示
すように、回線接続回路10と回線接続回路20との間
のパス接続をTIN認するためには、保守者が回線接続
回路10および回線接続回路20を閉塞し、強制的にス
イッチ回路30を駆動して回線接続回路10と回線接続
回路20との間を接続する。
FIG. 2 is a block diagram of a conventional failure detection device. Conventionally, in a fault detection device for a line connection device, as shown in FIG. The line connection circuit 20 is closed and the switch circuit 30 is forcibly driven to connect the line connection circuit 10 and the line connection circuit 20.

外部から試験信号発生器60を回線接続回路10につな
ぎ込み、また試験信号検出器70を回線接続回路20に
つなぎ込んで試験信号発生器60からの試験信号が試験
信号検出器70にて検出するか否かを確認することによ
って行っていた。
A test signal generator 60 is connected to the line connection circuit 10 from the outside, and a test signal detector 70 is connected to the line connection circuit 20, and the test signal from the test signal generator 60 is detected by the test signal detector 70. This was done by checking whether or not.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、このような従来例の障害検出装置では、試験回
路を外部から接続し試験を行って初めて異状が検出され
るために保守者の操作が多くまた障害検出に時間がかか
る欠点があった。
However, in such a conventional fault detection device, an abnormality is detected only after a test circuit is connected from the outside and a test is performed, so there are drawbacks that maintenance personnel have to perform many operations and fault detection takes time.

本発明は上記の欠点を解決するもので、保守者の操作が
少なく障害検出に要する時間が短い障害検出方式を提供
することを目的とする。
The present invention solves the above-mentioned drawbacks, and aims to provide a fault detection method that requires fewer operations by a maintenance worker and shortens the time required for fault detection.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、複数の回線接続回路と、この複数の回線接続
回路をそれぞれ相互に接続するスイッチ回路と、このス
イッチ回路および上記回線接続回路の接続制御を行う制
御回路と、上記回線制御回路および上記スイッチ回路の
障害検出を行う手段とを備えた障害検出方式において、
上記障害検出を行う手段は、試験信号を発生し、上記ス
イッチ回路に出力する試験信号発生手段と、上記スイッ
チ回路から上記試験信号を入力し、上記スイッチ回路に
折返す折返しスイッチ手段と、上記スイッチ回路から折
返された試験信号を入力し、障害を検出する試験信号検
出手段と、この試験信号検出手段、上記試験信号発生手
段および上記折返しスイッチ手段を制御する制御手段と
を含むことを特徴とする。
The present invention provides a plurality of line connection circuits, a switch circuit that interconnects the plurality of line connection circuits, a control circuit that controls connections between the switch circuit and the line connection circuit, and the line control circuit and the above line connection circuit. In a fault detection method comprising means for detecting a fault in a switch circuit,
The means for detecting the fault includes a test signal generating means for generating a test signal and outputting it to the switch circuit, a return switch means for inputting the test signal from the switch circuit and returning it to the switch circuit, and a return switch means for inputting the test signal from the switch circuit and returning it to the switch circuit, It is characterized by comprising a test signal detection means for inputting a test signal returned from the circuit and detecting a fault, and a control means for controlling the test signal detection means, the test signal generation means, and the return switch means. .

〔作用〕[Effect]

試験信号発生手段で試験信号を発生する。この試験信号
はスイッチ回路を経由して試験を行う回線接続回路に入
力される。回線接続回路では折返しスイッチ手段でこの
試験信号を折返す。この折返された試験信号はスイッチ
回路を経由して試験信号検出手段に入力され、試験信号
検出手段で障害検出が行われる。以上の動作は制御手段
の制御により自動的に行われる。上述のことにより保守
者の操作を少なくし障害検出に要する時間を短縮できる
A test signal is generated by the test signal generating means. This test signal is input to the line connection circuit that performs the test via the switch circuit. In the line connection circuit, this test signal is returned by a return switch means. This returned test signal is input to the test signal detection means via the switch circuit, and the test signal detection means performs failure detection. The above operations are automatically performed under the control of the control means. As described above, it is possible to reduce the number of operations required by the maintenance personnel and shorten the time required for failure detection.

〔実施例〕〔Example〕

本発明の実施例について図面を参照して説明する。 Embodiments of the present invention will be described with reference to the drawings.

第1図は本発明一実施例障害検出装置のブロック構成図
である。第1図において、回線接続回路10および回線
接続回路20がスイッチ回路3oに接続される。
FIG. 1 is a block diagram of a failure detection device according to an embodiment of the present invention. In FIG. 1, a line connection circuit 10 and a line connection circuit 20 are connected to a switch circuit 3o.

ここで本発明の特徴とするところは、一点鎖線で囲む試
験部分である。すなわち、制御回路4oは回線接続回路
10.20、スイッチ回路3oおよび試験回路50に接
続され、回線接続回路10と回線接続回路20との間の
パス接続がスイッチ回路30を経由して行われる。試験
回路50は4線を介してスイッチ回路30に接続される
Here, the feature of the present invention is the test portion surrounded by a dashed line. That is, the control circuit 4o is connected to the line connection circuit 10.20, the switch circuit 3o, and the test circuit 50, and a path connection between the line connection circuit 10 and the line connection circuit 20 is made via the switch circuit 30. Test circuit 50 is connected to switch circuit 30 via four wires.

φ  いま回線接続回路101の障害検出について説明
する。制御回路40の制御により、試験回路5oの試験
信号発生器51から試験信号がスイッチ回路3oを経由
して回線接続回路10.の折返しスイッチ11+の入力
に接続される。折返しスイッチ11.がら試験信号が試
験信号検出器52に接続され、障害検出が行われる。回
線接続回路10.20には上記折返しスイッチ111が
同様に設けられている。
φ Now, failure detection in the line connection circuit 101 will be explained. Under the control of the control circuit 40, a test signal is sent from the test signal generator 51 of the test circuit 5o via the switch circuit 3o to the line connection circuit 10. is connected to the input of the return switch 11+. Return switch 11. The test signal is connected to a test signal detector 52 to perform fault detection. The line connection circuit 10.20 is similarly provided with the folding switch 111 described above.

このような構成の障害検出装置の動作について説明する
。第1図において、回線接続回路10.と試験回路50
との間を接続し、その間のパスが正常であることを確認
するためには、制御回路4oが次の手順に従い、各回路
に指示を与えることにより行う。
The operation of the failure detection device having such a configuration will be explained. In FIG. 1, line connection circuit 10. and test circuit 50
In order to confirm that the path therebetween is normal, the control circuit 4o instructs each circuit according to the following procedure.

■ 回線接続回路101が使用中でないことを確認する
■ Check that the line connection circuit 101 is not in use.

■ 回線接続回路10+ 内の折返しスイッチ111 
を動作させスイッチ回路30からのパスをスイッチ回路
30方向のパスに接続する。
■ Return switch 111 in line connection circuit 10+
is operated to connect the path from the switch circuit 30 to the path toward the switch circuit 30.

■ スイッチ回路30を駆動させ回線接続回路101と
試験回路50とのパスを接続する。
(2) Drive the switch circuit 30 to connect the path between the line connection circuit 101 and the test circuit 50.

■ 試験回路50内の試験信号発生器51を動作させ試
験信号を送出する。
(2) The test signal generator 51 in the test circuit 50 is operated to send out a test signal.

■ 試験回路50内の試験信号検出器52が試験信号を
正常に受信することを確認する。
(2) Confirm that the test signal detector 52 in the test circuit 50 normally receives the test signal.

■ 項目■〜■で駆動したスイッチ類を「オフ」にし、
パスを解放する。
■ Turn off the switches operated in items ■~■,
Release the pass.

■ ただし項目■〜■の処理途中で回線接続回路10、
を他の回線接続回路と接続する必要が生じたときには、
項目■の処理に移り、試験のためのパスを解放し、すな
わち要求のある回線接続回路とのパス接続を行う。
■ However, during the processing of items ■ to ■, the line connection circuit 10,
When it becomes necessary to connect the line with other line connection circuits,
Moving on to item (2), the path for testing is released, that is, the path is connected to the requested line connection circuit.

項目■〜■の処理をずべての回線接続回路10.20に
ついて周期的に行う、自動的にかつ保守者の手をわずら
すことなく障害を検出することができる。
By periodically carrying out the processing of items (1) to (2) for all line connection circuits 10.20, failures can be detected automatically and without any maintenance personnel's intervention.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、回線接続回路スイッチ
回路または回線接続回路とスイッチ回路間のパスの障害
を自動的に検出し、保守者に通知することにより保守者
の操作を少なくし障害検出に要する時間を短縮すること
ができる優れた効果がある。また試験中または試験準備
中の回線接続回路を実際に使用する必要が生じたときは
速やかに試験を中止し実際の回線接続処理を行うことが
できる利点がある。
As explained above, the present invention automatically detects a failure in a line connection circuit switch circuit or a path between a line connection circuit and a switch circuit, and notifies the maintenance person, thereby reducing the number of operations required by the maintenance person and detecting the failure. This has the excellent effect of shortening the time required. Further, when it becomes necessary to actually use the line connection circuit that is being tested or prepared for the test, there is an advantage that the test can be immediately stopped and the actual line connection process can be performed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明一実施例障害検出装置のブロック構成図
。 第2図は従来例の障害検出装置のブロック構成図。 10.20・・・回線接続回路、11・・・折返しスイ
ッチ、30・・・スイッチ回路、40・・・1Ii11
′4n回路、50・・・試験回路、51.60・・・試
験信号発生器、52.70・・・試験信号検出器・ 実施例 −第  1  図 従来例 第2
FIG. 1 is a block diagram of a failure detection device according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional failure detection device. 10.20...Line connection circuit, 11...Return switch, 30...Switch circuit, 40...1Ii11
'4n circuit, 50...Test circuit, 51.60...Test signal generator, 52.70...Test signal detector/Example - Fig. 1 Conventional example No. 2

Claims (1)

【特許請求の範囲】[Claims] (1)複数の回線接続回路と、 この複数の回線接続回路をそれぞれ相互に接続するスイ
ッチ回路と、 このスイッチ回路および上記回線接続回路の接続制御を
行う制御回路と、 上記回線制御回路および上記スイッチ回路の障害検出を
行う手段と を備えた障害検出方式において、 上記障害検出を行う手段は、 試験信号を発生し、上記スイッチ回路に出力する試験信
号発生手段と、 上記スイッチ回路から上記試験信号を入力し、上記スイ
ッチ回路に折返す折返しスイッチ手段と、上記スイッチ
回路から折返された試験信号を入力し、障害を検出する
試験信号検出手段と、この試験信号検出手段、上記試験
信号発生手段および上記折返しスイッチ手段を制御する
制御手段と を含むことを特徴とする障害検出方式。
(1) A plurality of line connection circuits, a switch circuit that connects the plurality of line connection circuits to each other, a control circuit that controls connections between the switch circuit and the line connection circuit, and the line control circuit and the switch. In a fault detection method, the fault detection means includes a test signal generating means for generating a test signal and outputting it to the switch circuit, and a test signal generating means for generating the test signal from the switch circuit. a return switch means for inputting the test signal and returning it to the switch circuit; a test signal detection means for inputting the test signal returned from the switch circuit and detecting a fault; the test signal detection means, the test signal generation means, and the and control means for controlling the return switch means.
JP11813286A 1986-05-22 1986-05-22 Fault detection system Pending JPS62274858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11813286A JPS62274858A (en) 1986-05-22 1986-05-22 Fault detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11813286A JPS62274858A (en) 1986-05-22 1986-05-22 Fault detection system

Publications (1)

Publication Number Publication Date
JPS62274858A true JPS62274858A (en) 1987-11-28

Family

ID=14728835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11813286A Pending JPS62274858A (en) 1986-05-22 1986-05-22 Fault detection system

Country Status (1)

Country Link
JP (1) JPS62274858A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515545B2 (en) 2003-06-18 2009-04-07 Nec Corporation Signal repeater and switching device, method of detecting connecting relation between signal repeater and switching device and communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515545B2 (en) 2003-06-18 2009-04-07 Nec Corporation Signal repeater and switching device, method of detecting connecting relation between signal repeater and switching device and communication system

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