JPS622716A - Fet driving circuit for load drive - Google Patents

Abstract

PURPOSE:To attain a large amount of current for the load and at the same time to suppress the increase of the current consumption, by providing a switch circuit which is controlled by the data signal given from a logic circuit for each bit and supplying the power supply voltage higher than that of the logic circuit to a drive circuit via a switch circuit. CONSTITUTION:The power supply voltage of the 3rd power supply 7 is set at a level higher than the voltage of a power supply 1 of a logic circuit 2. The N channel FETs 8-1-8-n for switching are provided for each bit and therefore the gate voltage of an approximately fixed level is secured when the output N channel FETs 4-1-4-n are driven. Then it is conceivable that the variance of the ON voltage Von is produced by the effects of the manufacturing processes. Thus said variance of those ON voltages can be reduced. While the FETs 8-1-8-n are turned off for each bit when the N channel FETs 12-1-12-n receive the data signals from the circuit 2 and are turned on. Thus the increase of the power consumption of the 2nd power supply 7 can be suppressed by increasing enough the values of load resistances 9-1-9-n.

Description

Detailed Description of the Invention [Technical Field to which the Invention Pertains] The present invention relates to a load driving F' having a multi-bit drive circuit that drives a multi-bit load driving FIT, respectively.
This invention relates to an FiT drive circuit.

[Prior art and its problems]

This type of load driving FET driving circuit is used in MOB-C for driving a thermal head for plinking, for example, but in this MO8-IC for driving a thermal head,
The circuit consists of a logic circuit, a drive circuit, and an open-drain output N-channel FIT (field effect transistor), and the logic circuit and drive circuit are often used at a power supply voltage of 5V. Further, the drain of the output N-channel FET is connected to a flat voltage voltage (for example, 247) K via a heating resistor for printing. In this case, the gate voltage of the output N-channel/channel IFET is driven at 5V, and an output current corresponding to this drive voltage is obtained at the drain.

We will explain the conventional example and point out the problems with increasing the current. FIG. 2 is a circuit diagram showing a conventional example. In the figure, the logic circuit w&2 is connected to the power supply l (the voltage is Vnl), and the logic circuit w&2 corresponds to each output bit from the logic circuit w&2. Drive circuits 3 to 1 to 3-1, each consisting of a MOS inverter, operate in response to the respective data signals.
n is provided, and the power supply of the drive circuit of all the pits is the first
The power supply IK is connected. And the drive circuit llIr3-1
The output N-channel FET is driven by receiving the output signal of ~3-n at its gate.The drain of 4-1~4-n is
Fang 2 via external heating resistors (loads) 5-1 to 5-n
It is connected to the power supply 6 of.

The operation of this circuit is such that a data signal from the logic circuit 2 is sent to the corresponding output N-channel FFuT 4-1 to 4-n via the drive circuits 3-1 to 3-n for each bit.
Turn on, apply current to heating resistors 5-1 to 5-n,
The heat generated at this time is used to print on thermal paper. A bit number nl''t, 32 or 64 is used.

In this example, as mentioned earlier, the output N channels F
5■ is used as a drive power source for KT.

Therefore, in response to a request to increase the output current of the output N-channel FET,
channel width W must be increased. In this case, there is a problem that the chip size becomes large and the cost increases.

[Purpose of the invention]

This invention provides output N-channel FK for large VT flow.
We have developed a load driving FET drive circuit that can suppress the increase in current consumption due to changes in the drive circuit power supply (higher voltage) and drive circuit for the output N-channel r''ET without increasing the size of T. The purpose is to provide.

[Key points of the invention]

The present invention provides an FIT drive circuit having a plurality of bits of drive circuits each driving a plurality of bits of load driving FETs under the control of a data signal outputted from a logic circuit corresponding to each bit. By providing each drive circuit with a switch circuit controlled by the corresponding bit of the data signal, and supplying the drive circuit with a higher power supply voltage than the logic circuit through the switch circuit, In addition to enabling high voltage drive of the load driving FET to increase the load current, each switch circuit is turned off for each bit when the load is not being driven.
The aim is to reduce the increase in consumption by increasing the F.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as in FIG. 2 are given the same numbers.

In the figure, a first power supply 1 (power supply voltage tl-
vD! N-channel FETs 12-1 to 12-n are connected to N-channel FETs 12-1 to 12-n via buffers 13-1 to 13-n by a parallel plural n-bit data signal from this logic circuit 2. Driven. The drains of the N-channel FETs 12-1 to 12-n are connected to the load resistors 9-1 to 9-n and the gates of the switching N-channel FKTs 8-1 to 8-n, respectively. The other of the load resistors 9-1 to 9-n and the drains of the switching N-channel FKTs 8-1 to B-n are connected to the third power supply 7. The power supply voltage of this third power supply 7 is set higher than the voltage of the power supply 1 of the logic circuit 2. In addition, the above-mentioned N-channel F'ET for the switch
The P layer, which is the substrate of 8-1 to 8-n, is connected to ground, and a resistor 10-1-10-n is connected from its source, respectively.
The output N-channel FETs 4-1 to 4-n are respectively driven through the FETs 4-1 to 4-n. Furthermore, each resistor 11-1 to 11-
n is connected between the gate of the output N-channel IT 4-1 to 4-n and the ground, and this resistor 11-1 to 11-n connects the output N-channel FFjT 4-1 to 4 when the power is turned on.
- Prevent n from turning on. Then, one of the output N-channel FETs 4-1 to 4-n is connected to these FI
Heat generating resistors 5-1 to 5- connected to the drains of T4-1 to T4-n, respectively, and the other connected to the second power supply 6
energize n to generate heat. Alternatively, the second power supply 6 and the third power supply described above may be the same power supply.

Here, for each bit, the N-channel FICT for switching is
Since 8-1 to 8-n are provided, each output N channel PI! :The gate voltage when driving T4-1~4-n is almost constant, and these F'ET4-1~4-n
- The variation in the on-voltage Von of n can be considered to be only due to the influence of the manufacturing process, and can be suppressed to a small level. Regarding the current consumption of the second power supply 7, when the N-channel FETs 12-1 to 12-n receive the data signal from the logic circuit 2 and are turned on, the N-channel FETs 8-1 to 8-n for the switch turn on. OFF, and this is done for each pit, so the load resistance 9-1 to 9-nt
- By setting a sufficiently large value, the increase in current consumption can be reduced.

〔Effect of the invention〕

According to the present invention as described above, a switch circuit controlled by a data signal from a logic circuit is provided for each pit, and a power supply voltage higher than that of the logic circuit is supplied to the drive circuit through this switch circuit. As a result, the FIT for driving the load can be driven at a high voltage, allowing a large current to be applied to the load, and when not driving one load, the switch circuit is turned off for each pit, resulting in a small increase in current consumption. can be reduced. Furthermore, the gate voltage of the load driving FIT is almost the same when all bits or one bit is turned on, so variations in Von can be minimized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1.6.7...Power supply, 2...Logic circuit, 4-1
~4-n...Load driving FET, 5-1~5-n
...Load, 8-1~B-n-...FKT for switch
. Notebook 1 diagram/Ig2 diagram

Claims (1)

[Claims] 1) FE for driving multi-bit loads controlled by data signals output from logic circuits corresponding to each bit
In a load driving FET drive circuit having a plurality of bits of drive circuits each driving T, a switch circuit controlled by a corresponding bit of the data signal is provided in each of the plurality of bits of drive circuit, and a switch circuit controlled by a corresponding bit of the data signal is provided. A FET drive circuit for driving a load, characterized in that a power supply voltage higher than a power supply voltage of the logic circuit is supplied to the drive circuit.