JPS62271300A - Redundant semiconductor circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction at the time of applying a power source by connecting a writing negative potential source to a transistor side, further connecting the power source to the transistor side through a resistor, and making a serial connecting point as the reading end of a memory address. CONSTITUTION:At the time of writing, the power sources Vpp, Vcc are added and a control signal WC is brought into L level. Accordingly, if an address bit AB goes '0' (L level), the output of an OR gate G1 goes to L level, and the output of an inverter G2 to H level, the MOS transistor Q is turn on, a current is conducted in the sequence from the power source Vcc, a fuse F, the transistor Q and the power source Vpp and the fuse is melted. If the address bit AB goes to '1' (H level), the output of the OR gate G1 goes to the H level, the output of an inverter G3 goes to the L level, and the transistor Q is turned off and accordingly, the fuse F is not melted.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In a ROM circuit that electrically blows a fuse and programs it, a power supply having a negative potential is used as a power supply for blowing the fuse.

[Industrial application field]

The present invention relates to a redundant semiconductor circuit, and more particularly to a circuit for electrically blowing out a fuse in a ROM using a fuse.

[Conventional technology]

In semiconductor memory devices, as the capacity increases, the probability that some memory cells are defective increases, so extra memory cells are provided, and if a defective memory cell is detected during the manufacturing stage, the defective cell is replaced with a redundant cell. The defective chip is now replaced with a new one to make it a good product.

Replacing a defective cell with a redundant cell is performed by switching so that when a defective cell address is accessed, the redundant cell is accessed instead of the defective cell. Since defective cells are replaced in units of word lines or pin-line units, the defective cell address is the address of the word line or bit line. This address is stored in the ROM, and when accessing the memory, the access address is stored in the ROM. It is compared with the storage address, and if they match, the corresponding word line or bit is selected.

The selection of the bit line is stopped and a redundant word line or bit line is selected instead.

Fuse RO is a ROM that stores defective addresses.
A ROM in which M, that is, the memory cell is a fuse, is often used. The defective address is stored by blowing or not blowing the fuse by /8 in accordance with 1.0 of each bit of the address. FIG. 3 shows a conventional example of the fuse I disconnection circuit.

In FIG. 3, F is a fuse, and Q is an MO3t-transistor that is used to blow the fuse. A series connection point NF (fuse node) between the fuse F and the transistor Q is connected to an inverter G2, and is also connected to Vss (generally ground level) via a resistor R2. Fuse F requires a relatively large current to blow, so a high voltage (usually 1
A power supply Vpp of 0 to 15V) is prepared and is separate from the power supply Vcc (ijl is normally 5V) for other circuit elements. Power supply Vl)! ] is applied only when the fuse is blown, and otherwise only the power supply VCC is applied, so the fuse F is also connected to the power supply Vcc-1 via the resistor R+. G+ is a NOR gate, 1 pin h of write control signal WC and address signal A
B is added.

During writing, Vcc and Vpp are applied, and the control signal W
C becomes L (low) level, so address bit A
When B is "0" (L level), the output of Fazo hc+ becomes H (high) level, turning on transistor Q. Therefore, Vpp,,F,Q.

A current flows through the Vss (usually ground level) path, and fuse F blows. On the other hand, address bit AB
If is "1" (H level), the output of the fazo 1-G1 is at the L level, the 1-transistor Q is off, so the above-mentioned current does not flow, and the fuse F remains as it is (does not shut down).

When using the memory, the voltage tAVpρ is not applied and the power supply Vcc
However, the VC is connected to the fuse F via the resistor R+.
If the fuse F is not controlled exclusively, the node NF will be at H level (close to Vcc), and if the fuse F is exclusively controlled, the node NF will be at the L level (Vs
s level, and the note NF has the same H and L levels as the address focus AB written in IQ. Inverter G
2 inverts the level and outputs it to the next stage matching circuit (not shown). Note that the circuit in Figure 3 is based on 1 pin 1 of the address.
- minutes, and if the device has a redundant address length of 16 pins, 16 addresses are provided.

[Problem that the invention seeks to solve]

The circuit shown in FIG. 3 writes with the voltage aVpp, reads with the power supply Vcc, and has a resistor R1 in the reading circuit of the power supply VCC.
is included, so there is the following problem. In other words, when the power is turned on, charging of NF is performed in the path of Vec, R1, F, and NF (assuming that fuse F is not blown).
However, because of the presence of the resistor R1, the potential of the node NF rises slowly as shown in FIG. If the rise of the potential of the 7-no FNF is delayed, the detection of fuse blowing/non-blowing, that is, the reading of the redundant address will be delayed. There is a risk that malfunctions such as erroneous determination may occur.

The present invention aims to improve this point, to perform prompt operation even when the power is turned on, and to eliminate the possibility of malfunction.

[Means for solving problems]

As shown in FIG. 1, in the present invention, a high voltage power supply (Vpl) is connected to the source side of the transistor Q as a negative power supply. G
3 and R3 are the added inverter and resistor,
The rest is the same as in FIG. 3.

[Effect]

At the time of writing, power supplies Vpp and VCC are applied, and a control signal WC is applied. Therefore, Address Pino 1-A
If B is "0" (L level), the output of OR game 1-G1 is L level, the output of inverter C3 is H level, MO5I-Landisk Q is on, power supply Vcc, fuse F, 1-Landisk Q, power supply Vpp. Current flows through the path, and fuse F #8 is blown. On the other hand, if the address signal 1-18B is "1"<H level), the output of the OR gate G+ is a correct signal, the output of the inharter G3 is L level, the transistor Q is off, and therefore the fuse FL is ! Will not melt.

For reading, only the power supply VCC is applied and the control signal WC is set to H level. Therefore, the output of the OR game) G+ is at H level, the output of inverter G3 is at L level, and transistor Q is off. Therefore, the level of node NF is /8 of fuse F.
Determined by cut/non-cut, L level if cut, I if not cut.
(at level 1.0 of written address bits A and B)
Create a H1L level that corresponds to the situation. Inverter G2 inverts this and outputs it to the next stage matching circuit.

In this circuit, when reading, when the power is turned on, the node NF
is charged through the path of Vcc and F, and does not include the resistor R+ as in the conventional circuit shown in Fig. 3, so the rise of the node NF is steep as shown in Fig. 2, resulting in delays in reading redundant addresses and malfunctions. does not occur.

Since the power supply Vpp is the sum of the power supply Vcc and causes a current to flow through the fuse F, it does not need to be a high voltage. For example, if the fuse is to be fused at 10 to 15V as shown in FIG. 3, Vpp--5 to -10V may be used as Vcc=5V in FIG.

Inverter G] is necessary to turn off transistor Q. That is, the output of NOR gate Gl is at H level and V
cc, Vss at L level, connect this directly to transistor Q
When added to the gate of V ppm -5 to - during writing,
Since 10V is used, even if the output of G+ is at L level, the gate electrode viewed from the source electrode of transistor Q will be sufficiently at H level, and transistor Q will be turned on.

In this case, the fuse F will blow regardless of the address pin 1-AB being 1.0, which is a problem.

Insert an inverter G3, set its low potential power source to vpp, which is the same as the source of the transistor Q as shown in the figure, and also connect it to Vss through a resistor R3 (depending on the H and L outputs of the inverter G3). The transistor Q turns on and off, and they operate normally during reading.Resistor R3 prevents Vpp from being short-circuited to Vss.Resistor R1 in FIG. In addition to supplying Vpp to fuse F, there is a function to prevent Vpp from being shorted to VCC.

The gate G1 may be a NOR gate, and the output I11 may include Gl to connect two stages of in-harcs.

(Effects of the Invention) As described above, the present invention has the advantage that the fuse blows normally; and that the detection of whether or not the fuse I is blown when the power is turned on during reading can be quickly performed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the present invention, Figure 2 is an explanatory diagram of its operation. Figure 3 is a circuit diagram showing a conventional example; FIG. 4 is an explanatory diagram of the operation. In Figure 1, F is a fuse, Q is a transistor, and Vcc. Vss and Vpp are power supplies, and R is a resistance.

Claims (1)

[Claims] In a redundant semiconductor circuit that stores a redundant address using a fuse as a memory cell, the fuse F and a transistor Q that is turned on and off according to the redundant address bit are connected in series, and a circuit-use semiconductor circuit is provided on the fuse side. The positive potential power supply Vcc of the power supplies Vcc and Vss is connected to the transistor side, and the negative potential source Vpp for writing is connected to the transistor side.
A redundant semiconductor circuit characterized in that a power supply Vss is further connected to the transistor side via a resistor, and the series connection point serves as a read end of a storage address.